designing a dual-fuel motor management system with … · design a dual-fuel motor management...
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Designing a dual-fuel motor management system with Zynq
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Cereslaan 10b 5384 VT Heesch
+31 (0)412 660088 [email protected]
www.core-vision.nl
Frank de Bont Trainer / Consultant
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Customer Requirements Engine Management System LNG Supply Sensors / Actuators AR Electronic Control Unit Zynq Architecture Design Flow and Tools High-Speed ADC IP-block Software Partitioning and Communication Channels Why Linux with Xenomai eMMC Configuration Who is Core|Vision
Agenda
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Hardware Platform Caterpillar 3500 Diesel LNG (Liquefied Natural Gas)
High fuel efficiency Start up on Diesel and then switch over to a mixture with LNG
Easy to retrofit
NOx , SOx , CO2 and CH4 (methaan)
1 - 4
54255**slide
Design a dual-fuel motor management system with real-time control
Customer Requirements
Lowest possible emissions
Suitable for different qualities of LNG Still 100% Diesel as a fall back
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Hardware Platform Caterpillar 3500 Diesel LNG (Liquefied Natural Gas)
1 - 4
54255**slide
Focus on motor management control also called ArenaRed Electronic Control Unit
Customer Requirements cont
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Full controlled by the AR-ECU A full fail-safe system On-board diagnostics Power and Temperature sensors
LNG Supply
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Combustion in each cylinder is monitored by a set of cylinder pressure sensors
These allows the AR-ECU to optimize the combustion timing and gas mixture
In the exhaust are UEGO λ-sensors and temperature sensors to monitor the results of each combustion cycle
Sensors / Actuators
CompressorFilter
Turbo WastegateInlet
ManifoldIntercooler
Turbine
Gas
DieselT
P T
P
λ
P Pressure sensorT
λ Temperature sensorLambda (UEGO) sensor
PPP
Boost Wastegate
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AR Electronic Control Unit
[DL]CAT data link
[PWR]Power Supply Units
[STOP]Emergency stop
[PWR]Power Supply Units
Connectors
Zynq SoC[AO]
Analog Out 4-20mA
[CAN]CAN interfaces
CANPhy
MCP2551
[DO_HC]Digital Output High Current
[DO_LC]Digital Output Low Current
[ETH]Ethernet interfaces
[SHD]Remote
Shutdown
[EMD]Electromechanical Drivers
[DI]Digital Input
[AI_HS]Analog Input High
Speed
[AI_LS]Analog Input Low Speed
[POS]Position interfaces
Connectors
Injector PInjector N
16
16
216
UART
I/O C
ontro
ller
EMERGENCY STOP
JTAG
Conf
igur
atio
n
SPI Flash64Mb
Mem
ory
Cont
rolle
r
JTAGConnector
DDR32x 2Gb
4 32
Data Ctrl
43
SDIO
Co
ntro
ller
E-MMC32GB
Cloc
k
50 MHz
6
8 x LED
I/O C
ontro
ller
4
Internal Expansion Connectors
I/O C
ontro
ller
20
CANPhy
MCP2551
CANController
MCP2515
CANController
MCP2515
14
SPI C
ontro
ller
SPI C
ontro
ller 24
V/5A
Gen
eral
Pur
pose
O
ut+
Prot
ectio
n
I/O C
ontro
ller
2222
HALLinterrface
I/O C
ontro
ller
Rem
ote
Shut
down
MII
AR E
CU x
AR E
CU x
Gbit Phy
CA PulseSynchroniser
MagneticsMagneticsMagnetics
SWITCH (3 ports)
2 2 15
4 4 4 4
12
8
888
OBD
/Deb
ug
100M
b Li
nk
Casc
ade
100M
b Li
nkCa
scad
e
1
1
Shut
down
12
6 x RS422 PHY
RS422 PHY
HALLinterrface
VR Sensor Interface
VR Sensor Interface
Enco
der
HALL
sen
sor
VR
12 3 3
6 3 3
40 x 0-10V and 2x 4-20mA
Preamp
6 Ch
. ADC
MCP
3903
66
Ch. A
DCM
CP39
03SP
I Con
trolle
r
42
10
42
I/O C
ontro
ller
Rst
COND
8
+24V
5
1
ADC
+12V+5
V
Power Supply Units for internal supplies
+15V
+24V
I/O C
ontro
ller
I/O C
ontro
ller
I/O C
ontro
ller
4
RGM
II
SPI C
ontro
ller
10
CANPhy
MCP2551
SPI C
ontro
ller
SPI C
ontro
ller
COND
Digi
tal in
32
24V/
300m
AG
ener
al
Purp
ose
Out
+ Pr
otec
tion
I/O C
ontro
ller
3
3
1
I/O C
ontro
ller
Watchdog and health check uP
Power Supply Units for external supplies
+5V
+8V
+12V
-15V
+24V
DiagDiag
2 Ch
. ADC
AD
S836
32
Ch. A
DC
ADS8
363
Digital out
UART
2
Inte
rrupt
Co
ntro
ller
8 x EMD
ISOLATED
UART+24V
inj
8 8
Fire
8
Faul
t1
8 x EMD
ISOLATED
UART+2
4Vin
j
8 8
Fire
8
Faul
t1
1
Inte
rrupt
Co
ntro
ller
Diag
UART
2
2Ki
ll / IR
Q
2Ki
ll / IR
Q
I/O C
ontro
ller
4
Connectors
CAN
CAN
Cont
rolle
r
2 2CAN
CANPhy
MCP2551 CAN
Cont
rolle
r
2 2CAN
ESTOP
ESTOP OUT
Inte
rrupt
Co
ntro
ller
1
1
1
+15V
-15V
+5V
+12V
+8V
+8V
32
4
ADC
PWR
Vbat
t
Protection
+24V
+24V
inj
7332
Digital out
I/O C
ontro
ller
1
Gnd
+24V
Term
inat
ion
2
I/O C
ontro
ller
4-20
mA
drive
r
Analog out2 4
CAT Data Link
Diag
Diag
6 6
6
I/O C
ontro
ller
RS48
5 RX
4
RS48
5 TX
4
VR Sensor InterfaceRS485PHY
2
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AR Electronic Control Unit cont
General Interfaces DDR3 memory eMMC SPI Flash JTAG RS485 CAN Ethernet …
Monitor Interfaces 16x 12 bits ADC 2x UARTs 1x CAN 10x PWM outputs
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AR Electronic Control Unit cont
Electromechanical drivers High Voltage IO High Current IO
Digital Interfaces High Current IO Low Current IO Sensor Inputs
Analog Interfaces High Speed Inputs Low Speed Inputs Analog Outputs
Misc Interfaces LED bank Position Interface Expansion Connector
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Design Flow and Tools
FPGA hardware ADC IP Interface eMMC interface DDR3 memory IO JTAG ...
Tools Vivado Matlab ModelSim Altium ...
Software Real-time OS Drivers APIs ...
Tools Vivado SDK Matlab ...
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High-Speed ADC IP-block
High-Speed ADC to read pressure sensors
AXI streaming interface for transmitting ADC data completed with timestamp and crank angle
AXI slave interface for configuration
Interface to 2 ADC channels of the ADS8363
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Zynq SoC heart of the system
Software Partitioning and Communication Channels
Linux with Realtime extension Xenomai
Licensed & custom IP in FPGA PL Microprocessor for
Watchdog & Health Monitor
Software controlled EMD Injector Drivers
Communication cascading channel
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Multiple AR-ECUs can be cascaded so the system can control more than eight cyclinders.
Since Ethernet is non real-time by nature, crucial real-time signals will be routed over the four dedicated wires.
Cascading Channels
AR-ECU#1
Eth100 Mb
Eth1 Gb
Eth100 Mb
AR-ECU#2
Eth100 Mb
Eth1 Gb
Eth100 Mb
AR-ECU#3
Eth100 Mb
Eth1 Gb
Eth100 Mb
CA PulseSync
CA PulseSync
CA PulseSync
AR-ECU AR-ECU AR-ECU
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Why Linux with Xenomai
Zynq All Programmable SoC dual core Cortex-A9
Xilinx offers a kernel build and Linux kernel distribution by 3rd parties
Support Linux 3.14.17 with patches for real-time extension Xenomai 2.6.4 within SDK, version choice is limited
Xenomai offers greater flexibility and consistency because the real-time tasks can share the same drivers, synchronization primitives and memory as other non real-time tasks
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eMMC Configuration
Set boot mode pins of Zynq to JTAG (can be forced in initial
programming U-boot)
Download initial programming U-boot using JTAG
Start initial programming U-boot
Download initial programming kernel, ramdisk image and DTB
files using TFTP
Start initial programming kernel
Run initial programming shell scripts using rcS to download
from TFTP and program: • Running U-boot + FSBL to QSP • Running kernel to eMMC • Running ramdisk to eMMC • Running DTB to eMMC • Golden bitfile to eMMC • Update bitfile to eMMC
Set boot mode pins of Zynq to QSPI (can be forced in running
U-boot)
Download running U-boot using QSPI
Start running U-boot
Download golden or updated bitfile using eMMC
Download running kernel ramdisk image and DTB files using eMMC
Start running kernel
Updated bitfile
present in eMMC?
Program FPGA
succesful?
Start
Golden image
present in eMMC?
Stuck in U-boot, no valid FPGA
image found
Done, FPGA loaded succesfully
Program FPGA
succesful?
Yes
No
Yes
No
Yes
Yes
Initial Programming Running Bitfile Selection
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Flash Image Generation
Zynq Configuration
Wizard
PS Register Initialization
FSBL (source Code) User Created
FSBL (Executable)
PL Bitstream(s)
OS and/or Application Code & data
Golden Image (optional)
Flash Image Generator
BootHeader
FSBL
PL Bitstream(s)
OS and/or Application Code & data
Golden Image (optional)
Boot & Configuration Information
Flash Image
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Core|Vision
Our competences Core|Vision has more than 125 man years of design experience in hard- and software development. Our competence areas are:
System Design FPGA Design Consultancy / Training Digital Signal Processing Embedded Real-time Software App development, IOS Android Data Acquisition, digital and analog Modeling & Simulation ASIC Conversion & Prototyping PCB design & Layout Doulos & Xilinx Training Partner
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?
Cereslaan 10b 5384 VT Heesch
+31 (0)412 660088
www.core-vision.nl
Email : [email protected]
?
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Essentials of FPGA Design 1 day Designing for Performance 2 days Advanced FPGA Implementation 2 days Design Techniques for Lower Cost 1 day Designing with Spartan-6 and Virtex-6 Family 3 days Essential Design with the PlanAhead Analysis Tool 1 day Advanced Design with the PlanAhead Analysis Tool 2 days Xilinx Partial Reconfiguration Tools and Techniques 2 days Designing with the 7 Series Families 2 days
Training Program
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Training Program
Vivado Essentials of FPGA Design 2 days Vivado Design Suite Tool Flow 1 day Vivado Design Suite for ISE Users 1 day Vivado Avanced XDC and STA for ISE Users 2 days Vivado Advanced Tools & Techniques 2 days Vivado Static Timing Analysis and XDC 2 days Debugging Techniques Using Vivado Logic Analyzer 1 day Essential Tcl Scripting for Vivado Design Suite 1 day Vivado FPGA Design Methodology 1 day Designing with the UltraScale Architecture 2 days
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Designing with Multi Gigabit Serial IO 3 days High Level Synthesis with Vivado 2 days C-Based HLS Coding for Hardware Designers 1 day C-Based HLS Coding for Software Designers 1 day DSP Design Using System Generator 2 days Essential DSP Implementation Techniques for Xilinx FPGAs 2 days
Training Program
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Embedded Systems Design 2 days Embedded Systems Software Design 2 days Advanced Features and Techniques of SDK 2 days Advanced Features and Techniques of EDK 2 days Zynq All Programmable SoC Systems Archicture 2 days Zynq All Programmable SoC Accelerators 1 day C Language Programming with SDK 2 days Embedded Design with PetaLinux SDK 2 days Embedded C/C++ SDSoC Development
Environment and Methodology 1 day
Training Program