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Design RF Oscillator with Moderate Output Power using Solid State Device

Hina KadevalMaster of Engg.,E & C Engg.Dept.,

Parul Institute of Engg &Tech, Limbda [email protected]

Prof. Mary Grace ShajanProfessor, E & C Engg.Dept.

Parul Institute of Engg &Tech,[email protected]

Abstract

This paper discusses prototype of design and testing ofRadio Frequency(RF) that operate at 27MHz , emphasis is given to oscillator output power(5w) and frequency stability that is basic to application. The design approach is modular and consists of designing individual functional blocks of RF Oscillator and class E Power Amplifier using MRF134 and then integrating the same to produce the overall oscillator output power. It employs the single-ended configurationwith MOSFET transistor MRF134.The highest drain efficiency observed is 77.19% with 13.981 dB power gain atoutput power of 33.987dbm. When the power added efficiency drops to 60%, the output power obtained is 31dBm. The validation is done through ADS software before the design can be translated into building a practical working functional block.

Keywords-RF oscillator; Class E amplifier; Crystal resonator; Power Amplifier; Input matching network; output matching network.

I. INTRODUCTION

It is described to design & develop prototype model for RF oscillator design using solid state device at 27MHz having peak output power of

Figure 1.Basic block diagram

5w. Stable RF oscillator design using crystal with 20dBm(100mw) output at 27MHz. 5w Output power can be build up using class E power amplifier. it is proposed to carry out a software(ADS) base synthesis analysis to conform the RF performance of oscillator system that will meet the required specification.

I. DESIGN DESCRIPTION

Figure 2.Crystal resonator

A. Crystal Resonator design

This part of design process is to determine the required frequency of operation as 27MHz with loaded Q of 2000. Equivalent representation of crystal is shown in Figure2. The resulting value of motional inductance &capacitance is:

W0=2*pi*f0 (1)Cs=1/(Q*rs*W0) (2)Ls=Q*rs/W0 (3)

Q=2000; fo=27MHz

B.Block diagram of RF oscillator

V A RV A R 2

f o = 2 7 M H zQ = 2 0 0 0r s = 1 o h m

E q nV a r

LL 1

R = r sL = L s

V A RV A R 1w o = 2 * p i * f oC s = 1 / (Q * r s * w o )L s = Q * r s / w o

E q nV a r

CC 2C = C s

CC 1C = C p

P o r tP 2N u m = 2

P o r tP 1N u m = 1

National Conference on Recent Trends in Engineering & Technology

13-14 May 2011 B.V.M. Engineering College, V.V.Nagar,Gujarat,India

C. Crystal oscillator schematic

Figure3. Oscillator design

C. Oscillator simulation

Figure 5. Result of o/p power ,frequency and time domain waveform of crystal oscillator

When two circuit element (resonator and Amplifier) are connected together that loop phase will be zero. Oscport used to determine steady state oscillation condition. Theydetermine the oscillation frequency and power output.

III. CLASS-E POWER AMPLIFIER DESIGN USING MRF134

Design specifications of the amplifier are to achieve an output RF power of 5 W from an input driving level of 0.5 W, and drain efficiency of more than 75% at anoperating frequency of 27MHz

A. RF Power Device Selection and Characterization

The first step of the amplifier design procedure is theselection of the RF power transistor. For this design, theMotorola’s power MOSFET MRF134 has been chosen

Figure 6.1 Simulated DC characteristics of the MRF134 power MOSFET

This device is capable of delivering 5 W at 400 MHz with a typical power gain of more than 11 dB. It operatesfrom a 28 VDC supply and has a typical drain-to-source breakdown voltage of 65 V. The RF transistor library of the computer program ADS contains a SPICE model for this transistor which simplifies the simulation processThe simulated input DC characteristic (ID versus VGS) of the power MOSFET is shown in Fig. 6.1 with VDS = 28 V. It can be shown from this curve that the gate threshold voltage VGS(th) = 3.5 V. Fig 6.2 presents the simulated output DC characteristic (ID versus VDS) at several gate voltages. The drain ON resistance RD(on) can be estimated from Figure 6.2 as 12.5 Ω This relatively large value of RD(on) will cause a reduction in amplifier’s efficiency due to the dissipated power at the drain during the ON period of the power device

Figure 6.2 Simulated drain DC characteristics of the MRF134 powerMOSFET.

B. Design of the Biasing Network

The biasing network consists of the drain and gate RF chokes, bypass capacitors, DC blocking capacitors, in



addition to the gate and drain bias voltages. For 50% duty cycle operation, the transistor is biased at the threshold point, which means that VGG = VGS(th) = 3.5 V.

C .Load Network Design Equations

Several methods have been developed for the design of the load network for class-E RF power amplifier. Among those are the shunt capacitance , shunt inductance , finiteDC feed inductance , and parallel circuit techniques. The most popular configuration is the shunt capacitance technique due to its simplicity and design ability, which means that when the amplifier is built as designed, it works as expected .The schematic diagram of the class-Epower amplifier with shunt capacitance configuration is presented in Figure 7. In this circuit LG and LD represent the gate and drain bias RF chokes respectively, CB is a DC blocking capacitor, Cb1 and Cb2 are bypass capacitors, VGG is the gate bias voltage, VDD is thedrain supply voltage, C is the capacitor shunting the active device Q1, Lo and Co constitute a series resonant circuit tuned at the operating frequency, and R is the optimum resistance seen by the load network for therequired output power. The active device Q1 (power MOSFET in this case) operates as an ON/OFF switch.The load network of class-E power amplifier is notintended to provide a conjugate match to the transistoroutput impedance. Design equations for the load networkelements (C, C0, L0, and R) can be derived by writing time domain equations for the voltage vD(t) at the drain of the RF power MOSFET when it is OFF, and the current iD(t)passing through the RF device when it is ON.

Figure 7. Typical class-E power amplifier with shunt capacitance configuration

Following equations are used to calculate the values of the network elements at any output power and loadedquality factor QL. These equations are formulated as where Pout is the required output power, and f is theoperating frequency. The value of QL can be selected

based on a trade-off between operating bandwidth and harmonic distortion of the output signal

D. Calculation of the Load Network Elements

The design procedure begins by calculating the componentvalues of the load network using equations 4 to 7

R=0.5768(Vdd2/Pout)*(1-(0.451759/QL)- (0.402444/QL2) (4)

Cshunt =1/5.44658ωR(1+(0.91424/QL)-(1.03175/QL2)+0.6/ω2*LD (5)

C0=1/ωR(1/(QL-0.104823))(1+1.01468/(QL-1.7879))-0.2/(ω2LD) (6)

L0=(QL*R)/ω (7)

output power Pout = 5 W, operating frequency f=27MHz.

Calculated value of component using equation (4) to (7)

R = 80 Ω , C = 15.44 pF, C0 = 19.82 pF, and L0 = 2.35 uH.

E. Design of the Output Matching Network

An output matching network is needed to transform the 50 Ω amplifier impedance into the required load resistance ,which is set to be 80 Ω. This network has been designed with the aid of an admittance Smith chart, and is implemented in a L-section configuration, as shown in Fig.8 In addition to the transformation function of the output matching network, it also can be used to reduce the harmonic content of the output RF signal.

Figure 8. Configuration of the output matching network.

F. Design of Input Matching Network

The input matching network can be designed to match the large signal input impedance of the RF power device with the 50 Ω source impedance. Therefore, the large



signal input impedance of the RF transistor should be estimated at then nominal input power, operating frequency, and bias voltages with the existence of the load and output matching networks. The large signal input impedance of the power transistor consists of twoparts, resistance Rin and reactance Xin:

Zin = Rin + jXin (8)

Rin = real (Vin/ Iin) (9)

Xin = imag(Vin/I in) (10)

Where Vin is the fundamental component of the input voltage at the gate of the MOSFET, and Iin is the fundamental component of the current entering the gate of the transistor. Iin can be estimated using a current probe with the aid of ADS simulation capabilities. Input matching network improves the net input power delivered to the RFdevice. The amplifier circuit was simulated again after adding the input matching circuit using ADS. The outputpower of the circuit is displayed

Figure 9. Configuration of the input matching network.

IV. AMPLIFIER PERFORMANCE SIMULATION

The designed amplifier circuit has been simulated using ADS 2008.With a single tone input signal of 100mW power level and an operating frequency of 27Mhz.FromRF device’s drain voltage and current waveform from simulation shows peak values of drain voltage and current don’t exist simultaneously which minimizes the device’s power loss. However, at the ON time of the RF signal, the drain voltage is about3.5V due to the ON resistance at the drain, RD(on). This may degrade the overall efficiency of the circuit. During the OFF interval of the RF signal, a negative current flows through the power MOSFET’s output capacitance Cout.

Figure 10. Complete class E power Amplifier with i/p and o/p matching

In order to display the power amplifier’s performancecharacteristics, a sweep of the input power level has beencarried out from 10 to 24 dBm at the operating frequency as shown in Fig.12

Pout = real (0.5 *VL*IL) (11)

where VL and IL are the peak values of the fundamentalcomponents of load voltage and current respectively. Theoutput power is about 33.987 dBm at an input level of20dBm.at 27MHz as shown in output spectrum.

Figure 11.Output power spectrum of PA with 20dbm input RF power and its harmonics.

Power added efficiency can be evaluated from:

PAE = (Pout –Pin)/PDC (12)

where Pdc is the DC power consumed by the RF device



as shown in table.1

Figure 12.PAE Vs output power of Amplifier

Pdc = VDD * IDD (13)

where IDD is the DC component of the drain current.Complete simulation of PA with i/p and o/p matching n/w is shown in table. 1Table1.Simulation Results Using Linear Design Analysis

Table1.Simulation Results Using Linear Design Analysis

Gp(db) = Pout (dbm) –Pin (dbm) (14)

Figure 13.Power gain Vs output power in dbmNotice that the power gain is about 13.981 dB at an inputpower level of 20 dbm as shown in Fig.13 Figure 12displays a plot of the power added efficiency with outputpower. The amplifier efficiency is about 77.19% at output power of 33.987 dbm.

CONCLUSION

The performance of crystal oscillator design at 27MHz is obtained with required output power of 20dbm and The performance of Class E RF power amplifier using MRF 134 with a traditional shunt capacitance load network. It was shown that the high efficiency operation of such amplifiers is determined mainly by the output load network. However, with an accurate and proper design of the input matching network, the performance characteristics of the amplifier can be improved to get the desired output power of 33.987dbm with input power of 20dbm with gain of 13.987dB.For future work of high power oscillator design to generate 50w of output power using high power amplifier can be done using MRF151 RF power MOSFET. Which could be utilized in variety of RF transmitters and industrial application.

REFERENCES[1] D.M. Pozar, “Microwave Engineering”, 2nd Edition, 1998 John-Wiley & Sons.[2] R. Ludwig, P. Bretchko, “RF circuit design - theory and applications”, 2000 Prentice-Hall.[3] B. Razavi, “RF microelectronics”, 1998 Prentice-Hall, TK6560.[4] Microwave Circuit Design, George D Vendelin , An-thony M Pavio, Ulrich L Rhode, Wiley-Interscience, 1990[5] J. R. Smith, “Modern communication circuits”, 1998 McGraw-Hill.[6] R. J. Matthys, “Crystal Oscillator Circuits”. Revised Edition, Krieger Publishing Company, Malabar FL 1992.[7] M. E. Freaking, Crystal Oscillator Design and Temperature Compensation, Van Nostrand Reinhold Company, New York, [8] R. J. Matthys, Crystal Oscillator Circuits, Revised Edition, Krieger Publishing Comp[9]R. W. Rhea, Oscillator Design and Computer Simulation,2nd edition, Noble Publishing, Atlanta, GA[10] N.O. Sokal and A.D. Sokal,“Class E- A New Class of High-Efficiency Tuned Single-Ended Switching Power Amplifiers,” IEEEJ. Solid-State Circuits, Vol. SC-10,June 1975, pp. 168-176.[11] M.K. Kazimierczuk, “Class ETuned Power Amplifier with Shunt Inductor,” IEEE J. Solid-StateCircuit, Vol. SC-16, February 1981,pp. 2-7.[12] A. Grebennikov, “Switched-Mode RF and Microwave Parallel-Circuit Class E Power Amplifiers,”[13]A. Grebennikov and N.O. Sokal, Switchmode RF Power Amplifiers,Elsevier Inc., 2007, Chapter 5.



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