Digital IC Design Lab (Fall Sem 2014-15)

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Experiment Date:

Submitted Date:

Name:

M.Tech-VLSI DESIGN

15MVDxxxx

TITLE: Design of I/O PAD

OBJECTIVES:

1. To study the I/O PAD design and calculate the Power for Bidirectional I/O PAD i.e. I/O PAD as Input and Output.

CIRCUIT DIAGRAM:

Transistor Sizing:

PMOS Transistor (M1):- NMOS Transistor (M2):-

NMOS transistor: gpdk090_nmos1v NMOS transistor: gpdk090_nmos1v

Width: 310nm Length: 100nm Width: 120nm Length: 100nm

A) Schematic diagram of I/O PAD as Input

B) Power calculation for I/O PAD as Input :-

1. VDD = 1.5 V 3. Enable = 1 (1.5 V)

2. Data In

PULSE VOLTAGE (Vpulse) Data In

LOW LEVEL HIGH LEVEL WIDTH PERIOD DELAY TIME RISE TIME FALL TIME

0 V 1.5 V 10ns 20ns 0ns 1ps 1ps

Digital IC Design Lab (Fall Sem 2014-15)

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Transient Analysis of I/O PAD as Input

IC = 55.11 fA

Input Power= (VDD * IC)/No. of cycles

= (1.5 * 55.11)/3 fA = 82.67 fW

C) Schematic diagram of I/O PAD as Output

D) Power calculation for I/O PAD as Output

1. VDD = 1.5 V 3. Enable = 0 (0 V)

3. Data In

PULSE VOLTAGE (Vpulse) Data In

LOW LEVEL HIGH LEVEL PERIOD WIDTH DELAY TIME RISE TIME FALL TIME

1.5 1.5 20ns 10ns 0ns 1ps 1ps

Digital IC Design Lab (Fall Sem 2014-15)

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4. PAD In

PULSE VOLTAGE (Vpulse) Data In

LOW LEVEL HIGH LEVEL PERIOD WIDTH DELAY TIME RISE TIME FALL TIME

1.5 1.5 10ns 5ns 0ns 1ps 1ps

Transient Analysis of I/O PAD as Output

IC = 3.56 fA

Input Power= (VDD * IC)/No. of cycles

= (1.5 * 3.56)/6 fA = 890 pW

CONCLUSION:

1. Power Dissipation when I/O PAD work as Input is 82.67fW.

2. Power Dissipation when I/O PAD work as Output is 890 pW.