io buffers design - smdp-c2sd

INTRODUCTION TO IO BUFFERS (PADS) DESIGN IN IC COMMUNICATIONS

Venkata Reddy Kolagatla

Chip-Centre

Chip-Centre, CDAC Bangalore

Topics Covered • Basic Block diagram of IO communication – Introduction to IOs

• Buffered Vs Unbuffered

• Introduction to RC circuits

• Drive Strength Requirements of IC at particular speed with specified load

• Typical Driver Architecture

• OCD area dependency/crunch on pad

• OCD design for different drive strengths

• Process control of a driver

• Basic Input buffer (Receiver) design


Basic block diagram of IO Communication & Introduction to IOs


Generic Diagram of IO communication (IC to IC Communication)

Printed Wiring Board

Buffers

pack

age

pack

age

Receiver

Data

genera

tor

CMOS IC1 CMOS IC2


Introduction to IOs • Input/Output (IO) circuits enable a chip to communicate with the

external world.

• They are placed at the periphery of a chip and provide an interface between the chip and the external world.

• As the internal circuitry grows in speed and efficiency, it processes data faster.

• Matching IO circuits, in terms of speed and bandwidth, are critical to make sure that the processing power and efficiency of the internal circuitry or the core circuitry is best used.

• The electrical signal outside the chip is unknown and possibly unsafe for the internal circuitry.

• IOs help isolate the chip from such an environment and helps convert the external signal to a form where the internal circuit can process it.


Types of IOs

• The term ‘buffer’ is used alternately for “IO”, since IOs does not perform any logic operation on the signals!!

• Depending on the type of application, IOs can be classified into different types.

• Input

• Output (2 states or 3 states)

• Bi – directional


Input Buffer

• The input buffer passes external data to the core.

• It performs the level conversion from the external voltage to the core voltage level.

• It helps improve the signal by performing some kind of signal conditioning.

• ESD diodes associated with the input buffer help protect Integrated circuit (IC) chips from damage due to ESD events.

VCC

VSS

PAD To Internal

circuitry


Output Buffer

• The output buffer passes data from the core to the external world which is usually another component on the Printed Circuit Board (PCB) through a track.

• It performs level conversion from the core level voltage to the IO level output voltage (the motherboard voltage level).

• Output buffers can be either 2-state or 3-state depending on the application. For a 3-state buffer, the three states are logic low, logic high and high impedance.

• A 3-state buffer will have an enable signal which facilitates achieving high impedance (Hi-Z) at the PAD

• ESD diodes associated with the output buffer also help protect ICs from damage due to ESD events.

VCC

VSS

PAD

From Internal

circuitry

From Internal

circuitry


Bi-directional Buffer

• A bi-directional buffer functions as both an input and an output buffer.

• The enable signal which comes from the core determines if the buffer needs to be configured as an input buffer or an output buffer.

• It is designed such that when enabled as an input buffer, the PAD is at a high impedance state.

• There can be designs where both an input and an output buffer have separate enable signals.

PAD

From Internal

circuitry

From Internal

circuitry

VCC

VSS

To Internal

circuitry


Buffered Vs Unbuffered


Buffered Vs Unbuffered

Characteristics Buffered Unbuffered

Propagation Delay Low High

Noise Immunity/Margin Excellent Good

Output Impedance Constant Variable

Output transition time Constant Variable

Output oscillation for slow inputs Yes No

Input Capacitance Low High


Introduction to RC Circuits


RC Circuit


Low Pass RC – Circuit : Square Wave Input


RC Charging Table – Low Pass RC

Time Constant RC Value % of maximum

Voltage Current

0.5 time constant 0.5T = 0.5RC 39.30% 60.70%

0.7 time constant 0.7T = 0.7RC 50.30% 49.70%

1.0 time constant 1T = 1RC 63.20% 36.80%

2.0 time constants 2.0T = 2.0RC 86.50% 13.50%

2.2 time constants 2.2T = 2.2RC 90% 10.30%



5.0 time constants 5.0T = 5.0RC 99.30% 0.70% Chip-Centre, CDAC Bangalore

If Period = 10RC


If Period = 16RC


If Period = 4RC


Understanding it in frequency domain


High Pass RC – Circuit : Square Wave Input


0.00

50.00

100.00

150.00

200.00

250.00

1GHz 1GHz 1GHz 1GHz 1GHz 2GHz 2GHz 2GHz 2GHz 2GHz 3GHz 3GHz 3GHz 3GHz 3GHz 4GHz 4GHz 4GHz 4GHz 4GHz

1pF 2.5pF 5pF 10pF 20pF 1pF 2.5pF 5pF 10pF 20pF 1pF 2.5pF 5pF 10pF 20pF 1pF 2.5pF 5pF 10pF 20pF

Dri

ve S

tre

ng

th(Ω

)

Speed with Load Cap.

Drive Strength Requirement

R - calc if 4.4RC as T

R - calc if 10RC as T


Output Buffer/Driver/Transmitter Design


Basic O/P Buffer - Architecture • O/p 0 -> 1 : depends on PUN (Pull Up Network)

• O/p 1-> 0 : depends on PDN (Pull Down Network)

• To ensure the loading doesn’t affect the internal data.

• O/p drivers are large drivers that send a signal off chip (OCD).

• The widths of these devices in the range of 400 to 1000um (L would be around 0.24u to 0.6u).

• The size will depend on the frequency, power, voltage levels, current drive, functionality, etc.. of the buffer itself.

• These large transistors must be laid out with great attention in detail, because the area that they will require is highly sensitive and they can directly affect the chip size.

• The width of the bond pad o/p connection is based on many considerations : electro migration, resistance of the metal, impedance and inductance of the package connection, and equal load between the o/p transistors, among the all.

• In general o/p buffers are supplied with special or isolated power lines that are not connected to any other transistors and are connected directly to independent power pads, issues in minimizing the power supply resistance to these transistors.


Architecture of a Driver(O/P Buffer)

Pre Driver

PU

PD

PAD Data

CL

Gnd

Gnd Gnd

Vccq Vccq

PU

PD

PVT

Slew

CW

Gnd

CW = Bond wire cap + Via cap + layer cap + Next IC’s i/p cap

CL = Bond pad cap + wire cap + Self device cap

Current Design IC Chip-Centre, CDAC Bangalore

Progressive Sizing – Pre Driver requirement

• We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter

• The signal that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.

• So this results in slow rise or fall times .

• A unit inverter can drive approximately an inverter that's 4 times bigger in size.

• So say we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of output to input cap.

• This is the prime reason behind going for progressive sizing. Chip-Centre, CDAC Bangalore

Drive Strength Calculations

• Let us say 1.2v, with 1Gbps to drive 5pF load

• Assume that a minimum of 25ohm drive strength is required

• So, (*** R , Idrive , R α 1/width of the transistor α 1/Idrive )

𝐼 =𝑉𝑐𝑐𝑞/2

𝑅 =

1.2/2

25 = 24mA

• Let us say per micron width of a transistor (for both Pmos & nmos), I = 48uA, total of 500u is required in pull up and in pull down to achieve 25ohm drive strength.

• According to GDR(Geometric Design Rules), a transistor should not exceed a 10u(assume) width for a particular technology.

• So we have to connect such type of transistors in parallel as many needed accordingly, in order to get the specified drive strength.


Typical Driver

PD M1

M2

M3

M4

PU M5

M6

M7

M8

GND

Vccq

IOx


Typical Driver Design

VCC

VSS

PAD

From Internal

circuitry

From Internal

circuitry

500u

250u

Typically length would depend on the technology node – It is better to have maximum length such that it should have less leakage. Now -> PVT control ? -> tri-state control ? -> Design of diff. types of drive strengths? -> drive strength calculated at Vcc/2, why?


Input Buffer/Receiver Design


Definitions • Good receiver circuits (input buffers) in CMOS chips are required in

any high-speed, board-level design to change the distorted signals transmitted between chips (because of the imperfections in the interconnecting signal paths) into well-defined digital signals with the correct pulse widths and amplitudes.

• Input buffers are circuits that take a chip's input signal, with imperfections such as slow rise and fall times, and convert it into a clean digital signal for use on-chip.

• If the buffer doesn't "slice" the data in the correct position, timing errors can occur.

• If the input signal is sliced too high or too low, the output signal's width is incorrect.

• In high-speed systems this reduces the timing budget in the system and can result in errors.


Basic Requirements • The ‘switching point’ voltage is defined as the voltage at which the input and

the output transitions from logic high to logic low or vice versa

• If the switching point is too high, the output data has good low noise margin

• If the switching point is too low, the output data has high noise margin

• If the buffer doesn’t slice the data at the correct time instants, timing errors can occur i.e., the bits of data at the output of the buffer gets distorted.


Signal Noise and Removal Possibilities

• Noise can be removed from a signal with a circuit who has different switching points for low-high and high-low transition.

Hysteresis


Schmitt – Trigger Circuit

• The CMOS inverter circuit can be easily modified to obtain an inverting Schmitt-trigger circuit to reduce input-signal noise.


For Ex.. • Design and simulate a Schmitt trigger using the short-channel

CMOS process with VSPL = 400 mV and VSPH = 700 mV

• W1L2/W2L1 = ((1-0.7)/(0.7-0.25))^2 = 0.444, Assume L1=L2=1u W1 = 10u and W2 = 22.5u

• W5L6/W6L5 = ((0.4)/(1-0.4-0.25))^2 = 1.3, Assume L5=L6=1u W6 = 20u and W5 = 26u

• M3 and M4, we can set to 10/1 and 20/1(β3 ≥ β1 or β2/ β4 ≥ β5 or β6)


Applications of Schmitt Trigger

• A pulse with ringing is a common voltage waveform encountered in buses or lines interconnecting systems.

• If this voltage is applied directly to a logic gate or inverter input with a VSP of 0.5 V, the output of the gate will vary with the period of the ringing on top of the pulse.

• Using a Schmitt trigger with properly designed switching points can eliminate this problem.


A New Project Design Methodology

• Understand the root cause of all problems (signal-integrity, power-integrity, IO pad area requirements, slew-rates, pad cap etc..) and the general guidelines to minimize these problems.

• Translate the general guidelines into specific design rules for each specific custom product.

• Predict performance early in the design cycle by creating equivalent electrical circuit models for each component, critical net, and the entire system and by performing local and system-level simulation.

• Optimize the performance of the design for cost, schedule, and risk by modeling and simulating at every step of the design cycle, especially at the beginning.

• Use characterization measurements throughout the design cycle to reduce the risk and increase confidence of the quality of the predictions.


Source: Eric Bogatin Lectures

REFERENCES


References • https://uta-ir.tdl.org/uta-

ir/bitstream/handle/10106/24772/Abraham_uta_2502M_12777.pdf?sequence=1

• http://www.rnbs.hiroshima-u.ac.jp/RCNS/lecture/pdf/HJM_H20/OHP_CMOS_4(H20-5-2).pdf

• http://download.intel.com/education/highered/signal/ELCT762/Class17_18_IBIS_io_buffer_class.ppt

• https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4005e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__3rd_Edition.pdf

• http://www.ti.com/lit/an/scha004/scha004.pdf

• http://www.oldfriend.url.tw/article/SI_PI_book/Signal%20and%20Power%20Integrity%20-%20Simplified_2nd_Eric%20Bogatin_Prentice%20Hall%20PTR_2010.pdf

• https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwiLjfqX0KjUAhVMvo8KHQ1SBisQFgghMAA&url=http%3A%2F%2Fdownload.intel.com%2Feducation%2Fhighered%2Fsignal%2FELCT762%2FClass07_Using_Transmission_lines.ppt&usg=AFQjCNHaQAuOtX5kbH6C0T6qIs6dvyHJig


io buffers design - smdp-c2sd

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