design contest report - fpga climatic 2

FPGA ClimaticFPGA ClimaticDesign ReportDesign Report www.digilentdesigncontest.com

FPGA ClimaticOana Valentina Rusu

[email protected]

Submitted for the 2014 Digilent Design Contest

Cluj Napoca, Romania

17 May 2014

Advisor: Lecturer eng. Adrian-Vasile Duka PhD

“Petru Maior” University of Tirgu Mures, Romania

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Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners.

FPGA Climatic Design Report

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Contents

1.Introduction................................................................................................................................................................ 51.1. Abstract...........................................................................................................................................................................51.2. Objectives........................................................................................................................................................................51.3. Project Summary.............................................................................................................................................................51.4. Digilent Products Required.............................................................................................................................................61.5. Tools Required.................................................................................................................................................................61.6. Design Status...................................................................................................................................................................71.7. Why this project? Analysis of existing designs and contributions brought....................................................................71.8. Reference materials.......................................................................................................................................................8

2. Design........................................................................................................................................................................ 92.1. Design Overview..............................................................................................................................................................92.2. HDL Design....................................................................................................................................................................11

2.2.1. AHB-Lite SoC system..............................................................................................................................................12 2.2.1.1. AHB-Lite Master : ARM Cortex M0 Processor...............................................................................................16 2.2.1.2. AHB-Lite Slaves...............................................................................................................................................16 2.2.1.2. AHB-Lite Decoder and Multiplexer. Memory Mapping.................................................................................192.2.2. PModTmp Module.................................................................................................................................................192.2.3. IR Receiver Module................................................................................................................................................212.2.4. PWM Module.........................................................................................................................................................232.2.5. Temp_7seg_display Module..................................................................................................................................24

2.3. Software Design............................................................................................................................................................272.3.1. The menu display functions...................................................................................................................................272.3.2. The Heating Algorithm...........................................................................................................................................282.3.3. The Cooling Algorithm and PID controller.............................................................................................................292.3.4. NVIC. Interrupt Handling.......................................................................................................................................30

3. Discussions.............................................................................................................................................................. 323.1. Problems Encountered..................................................................................................................................................323.2. Engineering Resources Used ........................................................................................................................................323.3. Marketability.................................................................................................................................................................353.4. Community Feedback ...................................................................................................................................................353.5. Conclusions ...................................................................................................................................................................35

4. References............................................................................................................................................................... 36

Appendix A : Xilinx Project – HDL Design Part – Verilog Modules..................................................................................37Appendix B : Xilinx Project – HDL Design Part – Schematics ..........................................................................................67Appendix C : Keil uVision Project – Software Design Part .............................................................................................69Appendix D : List with Design Flow Charts.................................................................................................................... 88Appendix E : FPGA Climatic board description.............................................................................................................. 89




Abbreviations• FPGA – Field Programmable Gate Array ;

• HDL – Hardware Description Language ;

• AC – Air Conditioning ;

• AXI – Advanced eXtensible Interface;

• APB – Advanced Peripheral Bus;

• ATB – Advanced Trace Bus;

• AHB – Advanced High Performance Bus ;

• AMBA – Advanced Microcontroller Bus Architecture ;

• SoC – System on Chip ;

• IR – infrared ;

• PWM – Pulse Width Modulation ;

• PDM – Pulse Distance Modulation;

• uC – microcontroller ;

• IP – Intellectual Property ;

• PID – Proportional Integrative Derivative ;

• RCB – Relay Control Board ;

• PCB – Printed Circuit Board ;

• VGA – Video Graphics Array;

• KB – keyboard ;

• UART - universal asynchronous receiver/transmitter ;

• IRQ – Interrupt ReQuest;

• FSM – Finite State Machine;

• AGC – Automatic Gain Control;




1. Introduction

1.1. Abstract We live in a dynamic world where technology is developing very fast. But even a simple device can make our daily lives easier. The “FPGA Climatic” project is actually a climate control platform based on FPGA. It would replace the two devices used to control the heating and cooling system (the thermostat and the AC remote control) in our homes. Furthermore, it will provide an easier way to control everything since all the available commands and menus will be shown on a screen.

1.2. Objectives

The main objective of this project was to create a device which could be used in our daily lives. Technically speaking, I had the following objectives:

• Designing the hardware platform and HDL design in Verilog: Integrating the ARM Cortex M0 IP Core in a SoC system with AHB-Lite Peripherals; Creating custom SoC system to suite our needs ( adding and creating custom AHB

peripheral modules ); Modifying the AHB-Lite VGA module to allow cursor repositioning and screen clearing; Creating a module for the temperature sensor (PModTmp); Creating the IR receiver module; Creating a PWM fan control module; Creating a 7 segment display module ( displaying the temperature on Nexys 3’s 7

segment display );• Designing the software part and controlling algorithms:

Handling the IR receiver interrupt with Assembly and C code; Creating the design part : showing the menus on the screen and other options; Creating the heating and cooling control algorithm;

1.3. Project Summary The design of this project is complete and fully functional. It has been physically tested in all conditions. This project is divided in two parts:

1. The Hardware parts and HDL design which includes the following Verilog modules : the ARM Cortex M0 Core, the AHB-Lite SoC and custom made Verilog modules ( for temperature sensor, IR receiver, PWM control, 7 segment display );

2. The Software part which includes the menu design and heating/cooling system control algorithms.

Furthermore, this project design can be applied in practice. It can be used, with small modifications in modern houses, to replace the thermostat/air conditioning control. It could be use as a part or be extended to an “Intelligent House“ project. Usually, a basic Intelligent House project is very expensive and includes the following: KNX System, Light control, Light dim control, Temperature control, window control. Relative cheap components were used to prove that this system can be affordable for ordinary people too. At the same time, it has to be highlighted that in this project was designed only the control part, not the cooling or heating system itself. The above mentioned systems will be replaced with simple components, which could simulate the real ones.www.digilentinc.com page 5 of 89



1.4. Digilent Products Required

The Digilent products required are:

Product Quantity DescriptionNexys 3 Spartan-6 FPGA(XC6LX16-CS324) 1 As Main Board

PmodTmp 1 For measuring the temperature

1.5. Tools Required

Other hardware products required for our project:

Product Quantity Description100 Watt incandescent Light Bulb 1 Representing the heating system

PWM 92 mm PC fan 1 Representing the cooling systemRelay PCBs or Grid PCBs 2 To design relay control boards

TSOP 4838 IR Receiver 38 KHz 1 As the IR receiverIR Remote Control 1 IR Control Device

JQX-15F Relay 1 For the heating system controlLeg-5 Relay 1 For the cooling system control

2N3904 NPN Transistor 2 For Relay Control Board1N4148 Diode 2 For Relay Control Board

LED 2 For Relay Control Board1 K ohms resistors 4 For Relay Control Board10 K ohms resistors 2 For Relay Control Board

50 x 100 mm breadboard 1 For an easy circuit trace12 V 600 mA power supply 1 For the PC fan5 V 600 mA power supply 1 For relays

Wires, cables, screws, light bulb socket, plywood - For the rest of the designLaptop PC 1 To load files to FPGA

On the software part the requirements were:

Tool UsageXilinx ISE Design Suite 14.2 To design the SoC System and Verilog Modules

Keil uVision 5 To program the control algorithms, menu design functionalities and interrupt handling

Digilent Adept Suite 2.15.3 To load configuration files on FPGA boardARM Cortex M0 Design Start Microprocessor Core




1.6. Design Status

All features of this project have been implemented and tested in different situations. Any problems which occurred during the implementation and possible improvement will be discussed in a later section. In addition, most of the source code has been commented and structured. In some paragraphs of this project report will appear some code sequences which will represent the illustration for my concepts or explanations. Moreover, I have tried to fit in the time-limit with this project design. Future implementations could be:

• the possibility to control the system from distance through an internet connection (I consider using a Raspberry pi as a web server, it would be more efficient );

• the extension of this design to an Intelligent House Project.

1.7. Why This Project? Analysis of existing designs and contributions brought

There were a few reasons I have chosen to start this project. First of all, I wanted to learn something new by doing my first FPGA project. And I wanted to discover the usage and capabilities of an FPGA starting from simple to complex projects. Secondly, designing a useful platform for everyday usage was another goal too. With some small changes we can replace the heating/cooling system from our project board with a real heating system and an Air Conditioning device available in our homes. Furthermore, to highlight the reasons for choosing to work with the Nexys 3 board and integrating the ARM Cortex M0 core to it, I will illustrate the pros and cons to using a microcontroller or FPGA architecture for developing micro-systems.

1. FPGA :✔ Focuses on parallel execution ( ideal for time sensitive processes ) : you can have numerous

Finite State Machines ( FSM ) ;✔ The possibility to design your own digital circuits;✔ The possibility to integrate a soft core in it ( Microcontrollers );✔ High clock frequency;✔ Pins can be swappable;✔ Can connect a lot of devices and peripheral to it ( more than 32 digital pins, VGA , Ethernet ,

USB , USB- UART communication );✔ Possibility to reprogram the configuration file after a power loss without reloading it;✗ Power consumption : they use more power than an usual microcontroller do;✗ Hard to design circuits;2. Microcontroller :✔ Easy to program ( in C , C++ );✔ They are low-cost;✔ Possibility to re-run the loaded project after a power loss without re-loading it;✗ For complex projects, you need expansion shields which can be expensive;✗ Low frequency clock ( it takes more processor cycles to process a few instructions);

Similar designs have already been developed and implemented, despite the fact that they have several faults in many of their aspects. The “FPGA Climatic” project aims to improve the existing features and add some new ones at the same time.




The most common problems found at previous designs were:• Slow data processing;• Poorly designed User Interface;• Inflexibility and limitations in controlling options;• Inability to add more features to the design;

In comparison to previous designs and differences between two different devices (FPGA vs. uC), the decision to use a FPGA board for implementing a Microprocessor Core IP and a SoC were:

• Creating complex circuits in Verilog (converting/reading temperature module, decode/encode infrared signal module, PWM control module, show at the same time the current temperature on the 7segment display), so data could be parallel processed. On a microcontroller would be very complicated to do such things, because instructions on a uC are executed sequentially and would request more time for processing;

• The possibility to integrate on the FPGA a SoC system;• Easiness to connect much more peripherals comparing to an ordinary Microcontroller;• In-Built peripheral devices : leds, switches, 7 segment display, VGA, USB and Ethernet ports;• As a novice I could program complex algorithms in C and handle interrupts with a few lines of

code written in Assembly; The following new improvements were brought through this project:

• A practical user interface;• Parallel data processing;• New controlling options;• Capability to add new features or devices to this platform.

1.8. Reference Material

There were several books, datasheets and articles which helped me develop the project:• Nexys 3 Reference Manual :

https://www.digilentinc.com/Data/Products/NEXYS3/Nexys3_rm_V2.pdf ; • TSOP 4838 Datasheet : http://www.vishay.com/docs/82459/tsop48.pdf ;• PmodTmp Reference Manual;• DS1626 Datasheet;• Leg-5 Relay Datasheet : http://www.punchlight.com/files/relayLEG-5_datasheet.pdf?

PHPSESSID=b74e7ea0c06bd20c0a795c669e2ca461 ;• JQX-15F ( T90 ) Relay Datasheet : http://www.chinarelay.com/yzl/upload/file/20130520/pcb-

relay-T90.pdf ;• FPGA Prototyping by Verilog Examples - Pong P. Chu;• ARM Assembly Language- Fundamentals and Techniques;• http://soc.mit.edu/resources.html website;• http://wikipedia.org website;• http://infocenter.arm.com/help/ website ;• http://www.vishay.com/docs/ website;• http://www.arm.com/support/university/ip/index.php website;



http://www.arm.com/support/university/ip/index.php

http://www.vishay.com/docs/

http://infocenter.arm.com/help/

http://wikipedia.org/

http://soc.mit.edu/resources.html

http://www.chinarelay.com/yzl/upload/file/20130520/pcb-relay-T90.pdf

http://www.chinarelay.com/yzl/upload/file/20130520/pcb-relay-T90.pdf

http://www.punchlight.com/files/relayLEG-5_datasheet.pdf?PHPSESSID=b74e7ea0c06bd20c0a795c669e2ca461

http://www.punchlight.com/files/relayLEG-5_datasheet.pdf?PHPSESSID=b74e7ea0c06bd20c0a795c669e2ca461

http://www.vishay.com/docs/82459/tsop48.pdf

https://www.digilentinc.com/Data/Products/NEXYS3/Nexys3_rm_V2.pdf


2. Design

2.1. Design Overview

The design of this project is quite simple. The Nexys 3 FPGA board is the main component. It is used for data processing and to connect other components on it. As input devices we have the temperature sensor (PmodTMP) from which we will read the temperature, and the TSOP4838 IR Receiver which receives the signal from our remote control. We have a VGA output device on which we display the menu and control options of the platform. It can be any VGA compatible device (a TV or monitor display), preferable with a native resolution (800x600, 1024x768 etc). Furthermore, we will have some control outputs for the heating and cooling system. The heating system will have two states: ON or OFF. These states will be set by a relay control board connected to it. The relay control signal is sent by the FPGA board. For the cooling system two control options are provided. One is based on a relay control board which turns on and off the system) and the other one uses PWM control signal (initially calculated by a simple PID algorithm). In the figures below it will be illustrated the following: the design block diagram, the wiring diagram and RCB’s (relay control board) scheme.

Figure 1 - The FPGA Climatic Block Diagram




Figure 2 – Wiring Scheme of the project design

.Figure 3 - Relay Control Board Scheme




In the next sections it will be discussed in detail the HDL design part and software part.

2.2. HDL Design

The HDL design part contains the following modules:• AHB_Lite_SoC – the SoC system based on AHB-Lite protocol; this represents the

microcontroller component in which the ARM Cortex M0 core is integrated; this module processes the program loaded to control the heating and cooling system which is presented as the software design part;

• irreceiver – the modules which decodes the received signal and encodes the desired keys;

• PmodTMP – it converts and reads the temperature from the temperature sensor;• temp_7seg_display – displays the temperature read from the sensor on a 7 segment

display;• PWM – a module which handle the PWM signal generation ( it receives a value from

the PID controller); The structure (illustrated in figure 4) and implementation details of these components are presented in the following paragraphs. These modules operate in parallel. The FPGA permits that operations like decoding the IR signal, converting and reading the temperature or displaying the temperature on a 7segment display to be processed at the same time. The SoC system can receive data (which is already processed) from external modules (irreceiver, PmodTMP for example) at any time.

Figure 4 – HDL Design Top Level Structure




2.2.1. AHB-Lite SoC System AHB_Lite_SoC represents the integrated microcontroller architecture in our HDL design part. It has the following inputs and outputs:

• RsRx – Usb-RS232 Receive line;• RsTx – Usb-RS232 Transmit line;• LED – Led ;• relay_out – relay output, controls the heating system (turns it on/off);• relay_out2 – relay output, it is a part of the cooling system control (turn the system on/off);• hsync – horizontal synchronization signal (VGA output);• vsync – vertical synchronization signal (VGA output);• vga_red(2:0), vga_green(2:0), vga_blue(2:0) – RGB color signals (VGA output);• output_speed(5:0) – PID control 6bit output value;• temperature(7:0) – 8bit temperature input value;• remote_code(3:0) – 4bit remote code input value;• irq_remote – remote control IRQ input;• sw1 – switch ( for AHB-Lite SoC global reset );• sw2 – switch ( flash at Zero signal );• ps2d – PS2 data signal;• ps2c – PS2 clock signal;• RamCS, FlashCS, MemWR,MemOE, RamUB, RamLB, RamCre, RamAdv, RamClk, FlashRp,

MemAdr(26:1), MemDB(15:0), RamWait – memory/RAM/flash control and data signals; In today’s embedded processors a protocol called AMBA (Advanced Microcontroller Bus Architecture) [1] is being used as the on-chip bus for SoC designs. Nowadays it is used in a wide range of SoC designs, including application processors used in smartphones. This protocol (with its versions) is today a standard for embedded processors because they are well documented and can be used without royalties. Also, it can be considered as a good solution for the modules to interface with each other. The AMBA specification objectives:

• facilitate right-first-time development of embedded microcontrollers;• technology independency; it allows to reuse IP cores and peripherals;• facilitate the modular system design; • supports high performance and low power-on-chip communication;

The AMBA 3 specification defines four interfaces: AXI v1.0, APB3 v1.0, ATB v1.0, AHB-Lite v1.0; AHB [2] is a bus protocol which has been introduced in AMBA v2. It has the following features:

• single edge clock protocol;• split transactions;• several bus masters;• burst transfers;• pipelined operations;• single-cycle bus master handover;• non tristate implementation;• large bus-widths;




A simple transaction on the AHB bus consists in only two bus cycles: an address phase and a subsequent data phase. Access to the target device is controlled through a MUX (non-tristate), admitting bus-access to one bus-master at a time. In our project design was used the AHB-Lite protocol. It is a subset of AHB formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master. The main reason for using this protocol was to easily integrate the Cortex M0 Core and create or add simple peripheral slaves.

The main components of an AHB-Lite SoC based are:• Master Component;• Slave Components ;• An address decoder;• A multiplexor;

Below are illustrated the following block schemes:• AHB-Lite Master Scheme (Figure 5);• AHB-Lite Slave Scheme (Figure 6);• AHB-Lite generic SoC (Figure 7);• FPGA Climatic AHB-Lite SoC (Figure 8);

Figure 5 shows the block architecture of a Master controller and the interfacing signals (transfer response, address and control, data and global signals), as described in the specification of AHB-Lite AMBA 3 standard. This project uses as AHB-Lite Master the ARM Cortex M0 Design Start core. This core is connected to several slave modules. According to AHB-Lite specification, the general architecture of the slaves is presented in Figure 6. Based on this architecture several slaves have been developed.

Figure 7 represents a general AHB-Lite SoC architecture, with one Master module and several slave modules. It also illustrates the connection between them and connection with an address decoder and slave multiplexer.

Figure 5 - AHB-Lite master component and signals




Figure 6- AHB-Lite Slave component and signals

Figure 7 – an generic AHB-Lite SoC




Figure 8 - FPGA Climatic AHB-Lite Soc

Based on the architecture illustrated in figure 7, the SoC shown in figure 8 has been developed for this project. It is a microcontroller architecture in which ARM Cortex M0 has been integrated. This SoC system was required to facilitate some data processing such as:

• Menu display functionalities;• Heating system control algorithms;• Cooling system control algorithms;• Discrete PID controller calculations;

This SoC includes the following slave modules:• AHB2CTRL ;• AHBINPUT ;• VGA Controller ;• Memory Controller – it controls the PSRAM and FLASH memories ;• PS2-KB – keyboard controller;• Timer – can be used as counter;• UART - communication between FPGA and another device through UART;

The Keyboard, Timer and UART modules are optional because currently they are not used in the project design. They were included in case of project upgrades (adding control from keyboard or UART, using timer based functions, etc). These peripheral modules were included from the ARM Cortex M0 DesignStart Example Design Kit (EDK). The AHB-Lite Decoder, Multiplexer and VGA controller were modified to correspond to project specification. AHB2CTRL and Inputs (AHBINPUT) represent own creation. They will be explained in section 2.2.1.2.




2.2.1.1. AHB-Lite Master : Arm Cortex M0 Processor An AHB-Lite master provides address and control information to initiate read and write operations. The ARM Cortex M0 IP core [4] represents the Master Component in the AHB-Lite SoC. It has a few particularities comparing to other IP cores:• It does not generate BURST transaction ( HBURST[2:0] will be always 3’b000 );• It never generates locked transactions ( HMASTLOCK is always 1’b0 );• All transactions issued are non-sequential transfers ( HTRANS[1:0] is 2’b00 – idle or 2’b10 –

Non Sequential );• It has a 16 line NVIC ( Nested Vector Interrupt Controller) which is tightly coupled with

processor core ;• Priority of the IRQ can be modified in the interrupt vector:• assign IRQ={12'b0000_0000_0000, UART_IRQ, INPUTS_IRQ, KB_IRQ, TIMER_IRQ};• IRQ can be handled by writing code in Assembly or C;

2.2.1.2. AHB-Lite Slaves

An AHB-Lite slave responds to transfers initiated by masters in the system. The Slave uses the HSELx select signal from the decoder to control when it responds to a bus transfer. AHB2CTRL and AHBINPUTS are two AHB-Lite slave modules created for data processing. One of the modules included in the VGA controller was modified to improve some features. AHB2CTRL – it is a slave module which receives data from the master module and assigns it to outputs: the relays control bits (relay_out,relay_out2) and PID controller’s output value (output_speed[5:0]). So, it will receive data on the first byte of the HWDATA line of the data transfer phase : always @(posedge HCLK or negedge HRESETn) begin if(!HRESETn) rCTRL <= 8'b0000_0000; else if(rHSEL & rHWRITE & rHTRANS[1]) rCTRL <= HWDATA[7:0]; This slave will send a transfer response to the ARM processor : assign HREADYOUT = 1'b1; and received value will be assigned to output wires : assign CTRL = rCTRL; The number of controlled outputs can be modified by changing the rCTRL register, CTRL output widths.

AHBINPUTS – it is a slave module which reads data from inputs and sends them to the processor. As input lines we have: the remote control interrupt line (irq_remote), the remote code data bus (remote_code[3:0]), and temperature data bus(temperature[7:0]);The input_data port is being updates with new values:always @(posedge HCLK, negedge HRESETn) begin if(!HRESETn) input_data <= 16'h0000; else input_data <= INPUTSIN; end




which will be sent to the processor through HRDATA line: assign HRDATA[15:0]=input_data; Furthermore, the interrupt signal is assigned : assign inputs_irq= INPUTSIN[12]; The number of input lines can be modified by changing the input_data width.

VGA controller – it is an AHB-Lite peripheral which is responsible for VGA display. It contains the following modules:

• vgasync module;• vga_console module;• vga_image module;

A VGA port has five active signals : hsync, vsync , and RGB signals. The vgasync module [5] represents the synchronization circuit. It generates timing and synchronizations signals. Hsync and vsync signals are connected to the VGA monitor to control the horizontal and vertical scans. The signals are decoded from the internal counters, whose outputs are the pixel_x and pixel_y signals.These signals indicate the relative positions of the scans, and specify the location of the current pixel. The vga_console module is our interest actually. It is the module representing the text generation circuit. Here we can modify:

• the screen tiles: localparam MAX_X = 40; //Number of horizontal tiles

localparam MAX_Y = 10; //Number of tile rows• assign color for text :

assign font_rgb = (font_bit) ? 8'b11111111 : 8'b00000000; //white:blackassign font_inv_rgb=(font_bit)? 8'b0000000 : 8'b00000000; //black:black

• add or edit pressed-key logic;• cursor positioning;

In this module I have made the following modifications: • I have developed an invisible cursor;• I have provided custom cursor repositioning: in the cursor and pixel State Machine another

condition was added. If we have to display the 13th character from the font_rom module ( \r – carriage return) it will automatically reposition the cursor at the initial position (0,0): //State Machine for cursor and pixel buffer

always @ (posedge clk, negedge resetn) begin if(!resetn) begin cur_x_reg <= 0; cur_y_reg <= 0;

endelse if(din==7'b0001101) // if we have character 13 ( carriage return

) to display begin

cur_x_reg <= 0; cur_y_reg <= 0;

end




else begin cur_x_reg <= cur_x_next; cur_y_reg <= cur_y_next; pixel_x1 <= pixel_x; pixel_x2 <= pixel_x1; pixel_y1 <= pixel_y; pixel_y2 <= pixel_y1; end end

The dual_port_memory ram is the memory which contains the text to display on the screen. The font_rom module contains the 128 characters of the ASCII code. In our case the used font is 8-by-16 ( 8 tiles , 16 rows ): //code x02 11'h020: data = 8'b00000000; // 11'h021: data = 8'b00000000; // 11'h022: data = 8'b01111110; // ****** 11'h023: data = 8'b11111111; // ******** 11'h024: data = 8'b11011011; // ** ** ** 11'h025: data = 8'b11111111; // ******** 11'h026: data = 8'b11111111; // ******** 11'h027: data = 8'b11000011; // ** ** 11'h028: data = 8'b11100111; // *** *** 11'h029: data = 8'b11111111; // ******** 11'h02a: data = 8'b11111111; // ******** 11'h02b: data = 8'b01111110; // ****** 11'h02c: data = 8'b00000000; // 11'h02d: data = 8'b00000000; // 11'h02e: data = 8'b00000000; // 11'h02f: data = 8'b00000000; // The above mentioned modifications were required in the vga_console module for a better appearance and the implementation of the clear_screen() function. The logic behind this function is the following: when the 13th ASCII font_rom character is displayed the cursor is repositioned to its initial position. Then the dual_port vga memory will be “rewritten“ with empty characters (spaces) and then the cursor will be repositioned again by displaying again the 13th character. The function is being implemented in the software part, but it’s code is shown below:

void clear_screen(){printf("%c",13);for(i=0;i<8;i++)

printf(" ");

printf("%c",13);}

The vga_image module is useful if we want to draw an image to the screen. Also, it has a dual_port_ram memory module too.




2.2.1.3. AHB-Lite Decoder and Multiplexer. Memory Mapping

The decoder is the component which decodes the address of each transfer between the master and a slave. It provides a select signal for the slave that is involved in the transfer. Furthermore, it provides a control signal to the multiplexer. A decoder is always required if we have more than one slave in our SoC design. The multiplexor is required to multiplex read data bus and response signals from slaves to master. Memory mapping for each peripheral it is done according to the table 1.

Slave Name Start Address End Address Size Interrupt Capability

Memory 0x0000_0000 0x00FF_FFFF 16 MB NOAHB2CTRL 0x5000_0000 0x50FF_FFFF 16 MB NOUART 0x5100_0000 0x51FF_FFFF 16 MB YESAHBINPUTS 0x5200_0000 0x52FF_FFFF 16 MB YESVGA 0x5300_0000 0x53FF_FFFF 16 MB NOAHBKB 0x5400_0000 0x54FF_FFFF 16 MB YESTimer 0x5500_0000 0x58FF_FFFF 16 MB YES

Table 1 – Peripheral Memory Mapping

2.2.2. PmodTmp module Pmodtmp module reads the temperature from the sensor. It has the following inputs and outputs:

• clock – clock signal from 100MHz clk;• clock_conv – a clock signal for the sensor which is manually

generated through each state of the sensor state machine (see figure 12);

• rst_n – reset pin, it is active on logic “0”;• dq – bidirectional wire ( it sends the commands to the sensor

and receives the temperature bits );• temp_out(7:0) – 8bit temperature output;

The PmodTmp [6] peripheral is an interface board for the Dallas Semiconductor DS1626 3-wire digital thermometer and thermostat. This sensor is capable of transmitting the temperature with a 12-bit resolution between -55 and +125 degrees Celsius. For this project only 8 bits are used from the temperature register. Bit 11 (the sign bit) and bits 0, 1, 2 (which correspond to 2, 3 and 4 decimal part) are not used. Since the project is intended for domestic use, it is assumed that the measured temperature is always positive, lower than 100 degrees and only one decimal part (e.g. 23.5 C) is required. In the following figure the red rectangle marks the used bits (figure 10):

Figure 10 – DS1626 temperature register



Figure 9 – PmodTMP Block


During a temperature read cycle we will send two configuration registers on the dq wire (which is a tri-state in-out pin). These configuration register (1 byte long) corresponds to the following commands: start convert (0xAA) and read temperature (0x51).These are serial transmitted starting with LSB. The configuration register [7] has the following structure (figure 11):

Figure 11 – Configuration register All communication with the DS1626 are initiated by driving nRST signal high. Driving nRST low terminates communications and causes DQ to go to a high-impedance state. nRST must be toggled low after every communication sequence to ensure that subsequent commands are recognized by the sensor. When writing to the DS1626 data must be valid during rising edge of the clock. Data from DS1626 can be read on falling edge of clock signal and it remains valid through the following rising edge. The nRST will be high and then we will set the configuration register to Start Convert (51h) through dq line. It remains in high impedance until we send the Read Temperature command. Right after that we will start to read the temperature on each falling edge of the clock signal. For a better understanding, see figure 12 (describes 3-wire communication timing diagrams from the DS1626 reference manual) and figure 13 (which represents the generic State Machine for our module). This module performs only one conversion and read temperature cycle once. We have to drive reset high after each cycle. That is the reason I have implemented an autoreset module. The autoreset module (included in pmodtmp module) creates a 0.5 Hz clock signal (a period of 2 seconds).

Figure 12 – 3 wire communication timing diagram




Figure 13 – PmodTMP State Machine

2.2.3. IR receiver module The irreceiver module decodes the IR signal received from the remote control. It has the following inputs and outputs:

• clock – 100 MHz clock signal ;• remote_in – remote signal;• reset – reset input ;• irq_signal – it sends an IRQ signal to the SoC system;• remote_out(3:0) – sends an 4 bit code to the output

(represents the key code); The IR receiver used in the project design is a TSOP4838 38kHz IR receiver. TSOP4838 is a AGC2 legacy receiver, used forlong burst remote controls. It is not so recommended because it can deliver poor results in some environments.



Figure 14 – irreceiver block


The code which is sent from the remote control has the NEC IR format. The NEC format [8] uses PDM (Pulse Distance Modulation) technique. It is based on varying the pulse duty cycle for logic “1” and “0” while keeping the pulse active period constant. The period for each logical state: logic “0”- 1.12 ms and logic “1” – 2.25 ms. The NEC protocol [9] uses an 8-bit command and an 8-bit address length for each transfer. The command and address bits are transferred a second time with all bits inverted for increased reliability.So, the code transmitted by remote control should contain: a 9ms header code, a 4.5 ms off code, an 8-bit address code, an 8-bit inverse address code, an 8-bit data code and another 8-bit inverse data code. The NEC format code is described in the following scheme (figure 15):

Figure 15– NEC IR format TSOP4838 inverts the input signal, so it will be active in the low logic state. We have to examine when it goes down to logic low state. If it is, we have to examine 9ms later to see if the logic state is low (we will return back to the monitoring state). Else we will examine 4.5 ms later and if we have logic high state we will return to monitoring state, otherwise we will start reading the address bits, data bits and inverse data bits. Two logic states of data bits can be distinguished: if the signal is logic low and 1.2 ms later the signal will be low, then data bit will be 0. Else, data bit will be 1. In that case, we have to examine the line 2.2 ms later because after 1.2 ms the line will be low every time, each logic state starts with logic low. A state machine was implemented for decoding the remote code (see figure 16). The address bits and data bits are essential in key assigning. Address bits actually represents the Device Address and command code represents one of the keys pressed. Each key has assigned a 4 bit code. The following table contains the address bits, data bits and assignment code for each remote control key (table 2):

Key Name Address Code Data Code Value AssignedOn/Off 1111011100001000 00011011 7 (0111)

A 1111011100001000 00011111 1 (0001)B 1111011100001000 00011110 2 (0010)C 1111011100001000 00011010 3 (0011)O 1111011100001000 00000100 5 (0101)Up 1111011100001000 00000101 6 (0110)

Down 1111011100001000 00000000 4 (0100)Left 1111011100001000 00001000 8 (1000)

Right 1111011100001000 00000001 9 (1001)

Table 2 – Key assigning




Figure 16 – irreceiver State Machine

2.2.4. PWM module

This module is responsible for generating a PWM signal for our PC fan. It has the following inputs and outputs:

• clock – input clock signal (100MHz);• input_speed(5:0) – input speed received from the

AHB-Lite SoC. This value it is calculated by a discrete PID controller programmed in C.

• pwm_out – PWM signal output;• output_led(5:0) – displays on leds the value received • from the PID controller;

Before generating the PWM signal we had the following considerations: defining the signal period and duty cycle;



Figure 17 – PWM block


We have to determine the period with the following formula: P = t * fpga_frequency; (1)

where P - the period , t – time; In our case, Nexys3’s frequency clock is 100 MHz and I chose to have an 1 ms period: P = 0.001*100 000 000 = 100 000; (2) During the 1 ms period of the PWM signal the signal will have a logic 1 on period proportional to duty cycle . The duty cycle we will have two parameters: step_delay and input_speed.Input_speed is a variable parameter. It is a value on a 6bit bus received from the AHB-Lite SoC (an output value computed by a discrete PID controller). Step_delay is a constant. Its value represents the ratio between signal period (P) and the maximum values we can have as input value.

step_delay = P/SC (3) So,

step_delay=100 000 / 64 =~1560; (4) For our signal period we need a register counter whose size can be determined so:

counter_width=log2(P) =log(100 000) ~ 17 bits (5) The signal itself will be determined so: the pwm_out signal will be logic high state as long as our counter reaches the step_delay*input_speed value. Then it will drive low until the counter reaches 100000.

2.2.5. Temp_7seg_display It is useful to display the current temperature on the Nexys3’s 7segment display. It has the following inputs and outputs:

• temp_in(7:0) – 8 bit temperature value;• clk – clock signal (100MHz);• segout(6:0) , point , an(3:0) – 7 segment display outputs;

Figure 18 - temp_7seg_display block scheme

This module works independently to processor control. It is based on a time-multiplexed seven-segment display. Furthermore the following modules were built for this functionality:

• temp_value – receives the current temperature from an 8bit line and it divides it in tens, units and decimal parts. The binary code is transformed in a BCD value (see Figure 19); Only the




units and tens value are calculated so. The decimal part and degree sign are assigned as shown by the following code:always @* begin

case (temp_in[0])1'b0: begin

decimal=4'b0000; // zeroend1'b1: begin

decimal=4'b0101; // fiveend

endcaseend

assign degree=4'b1100; // degree sign (C)

Figure 19 – BIN to BCD output

• digitmux is a module which receives an input value (tens, units, decimal part or degree sign) and will transmit at once only one digit to output [10].

• The digits will be shown on the 7 segment display with an 7 segment decoder ( represented by display7seg module) ;

• digitselcounter represents a module which generates a clock signal with 2 cascaded counters and sends as output 4 values which corresponds to each individual 7seg digit (2’b00 for the first digit, 2’b01 for the second, 2’b10 for the third and 2’b11 for the last one).




• muxselect7seg module allows to display one digit at a time (see figure 20):always @*

begincase(selection)

2'b00 : an = 4'b1110;2'b01 : an = 4'b1101;2'b10 : an = 4'b1011;2'b11 : an = 4'b0111;default : an = 4'b0000;

endcaseend

furthermore, we have to display a point between the units and decimal part digits : always @*

begincase(selection)

2'b10 : point =1'b0;default : point =1'b1;

endcaseend

Figure 20 – Time multiplexed seven-segment display




2.3. Software Design

The software parts are written in two programming languages: ANSI C and ARM Assembly. The project itself contains 4 files:

• CM0-DS.h – header file , it contains the peripheral memory map ;• retarget.c – contains the implementation of some functions used to display the text;• cm0dsasm.s – contains the instructions which handle the interrupt vector;• MyProgram.c - contains functions used for menu display, heating/cooling algorithms

described in the following sections;

2.3.1. The menu display functions

In this part we have four functions which deal with displaying a interactive menu on the screen:• void show_menu() – displays the main menu with a cursor inline with the selected option; • void options_menu() – displays the “Options” menu; if we navigate on those lines the menu will

be “repainted” by calling the show_options_menu() function. If we want to increase or decrease a value at the selected option , the menu will be repainted by calling the option_menu_modified (int increase) function;

In figure 21 we have some screen captures.

Figure 21 – Screen captures




A distinct function is called when entering cooling/heating mode (heating_mode() or cooling_mode() functions): set_mode(). This function dispays the current temperature and helps the user to set a desired temperature. The system waits for the user to press a button. The desired temperature will be increased/decreased by pressing up/down keys. If we press the ok button it will call the correspondent control function: apply_cooling() or apply_heating(). If the on/off button was pressed, it will abort the current operation and return to the main menu. Some flowcharts submitted in the /flowcharts folder can be analyzed for a better understanding.

2.3.2. Heating Algorithm When the heating mode is selected, the current temperature is shown on the screen and a new setpoint (desired temperature) can be introduced. After that it will call the apply_heating() function which contains the heating algorithm (see figure 22 for the program diagram). In the heating process we have 3 states:

• active_heating – it compares the current temperature with the setpoint. If current temperature is lower than the setpoint, it will turn on the heating system; otherwise it will turn off the heating system and enter the pause_heating state;

• pause_heating – it background compares the current temperature with the setpoint. If the current temperature is threshold_value degrees lower than the setpoint , it will enter the active_heating state;

• exit_heating – whether we are in active_heating or pause_heating states, we can abort the heating process at any time by pressing the on/off button. It will return to the main menu;

The threshold value for each mode is set at 2 by default. These values can be modified by entering the options menu. They are shown as Heating Mode Threshold and Cooling Mode Threshold on the screen (see figure 21);

Figure 22 – Heating algorithm




2.3.3. Cooling Algorithm. PID controller.

This functionality behave opposite to the heating process (see figure 23). The algorithm is similar, the only difference is that we have a PID controller too. Cooling process states:

• active_cooling – it compares the current temperature with the setpoint. If current temperature is higher than the setpoint, it will turn on the cooling system; otherwise it will turn off the cooling system and enter the pause_cooling state;

• pause_cooling – it background compares the current temperature with the setpoint. If the current temperature is threshold_value degrees higher than the setpoint , it will enter the active_cooling state;

• exit_cooling – whether we are in active_cooling or pause_cooling states, we can abort the cooling process at any time by pressing the on/off button. It will return to the main menu;

Figure 23 – Cooling Algorithm




A PID controller [11] is a control loop feedback mechanism (controller) widely used in industrial control systems. It calculates an error value as the difference between a measured process variable and a desired setpoint. The controller attempts to minimize the error in outputs by adjusting the process control inputs. The PID controller algorithm contains three main blocks:

• Proportional block (P) – depends on the present error;• Integral block (I) – the accumulation of past errors;• Derivative block (D) – a prediction on future errors, based on current rate of change;

The weighted sum of these three actions is used to adjust the process via a control element (fan speed in our case):

Where:- e – error ( difference between setpoint and current temperature);- t – time;- Kp – proportional gain;- Ki – integral gain;- Kd – derivative gain;- - variable of integration ( takes on values from time 0 to the present t );

In our design, a discrete PID controller was implemented. The PID parameters (Kp,Ki,Kd) were set manually. The values were determined experimentally (Kp – 10, Ki – 0.1, Kd – 1). Reasons for choosing these values:

The proportional gain has a higher value because the fan speed must be proportional with the temperature difference (error) in a temperature interval;

In a time interval the current temperature may remain constant and could not reach so easy the setpoint. The proportional gain will increase in time the speed value;

The derivative gain is has a small value to have slight decrease of the fan speed. This block is not as important as the other ones.

2.3.4. NVIC. Interrupt Handling.

Cortex M0 Design Start supports seven exception types:• Reset – Processor reset input is asserted;• HardFault exception – can be any type of fault occurred (e.g. bus fault or undefined

instruction);• NMI – Non-Maskable Interrupt occurred;• IRQ – IRQ Interrupts occurred;• PendSV – Software Generated interrupt;• SVCall – execution of a SVC instruction;• SysTick – internal system timer caused interrupt;

Each exception has associated an exception number, vector address and priority level.




NVIC (Nested Vector Interrupt Controller) is the SoC interrupt controller. It has a NMI (Non Maskable Interrupt) and 16 prioritized interrupt lines. NVIC is tightly coupled with our processor core (Cortex M0). In figure 24, we have a scheme of the Vector Table and exception handling [12].The vector table contains the Handler vector addresses and initial value of the Main Stack Pointer (MSP). In the case of an exception the core will read the vector handler address for the exception from the vector table and branches to the handler.

Figure 24 – Handler Vector

In our project design we use the IRQ received from the remote control by pressing the ON/OFF button. It is represented by INPUTS_IRQ in the AHB_Lite_Soc system and it is the third IRQ from the IRQ vector, right after the keyboard IRQ. In the Vector Table INPUTS_IRQ’s handler has address 0x48 (corresponds to Interrupt #2 Handler Vector entry). To add and handle this interrupt we had to follow four steps:

• Assigning an entry in the IRQ bus from the AHB_Lite_SoC module:assign IRQ = {12'b0000_0000_0000,UART_IRQ,INPUTS_IRQ,KB_IRQ,TIMER_IRQ};

• Adding an entry to the Vector Table (in cm0dsasm.s Assembly file). Note: the entry must correspond with the entry from the IRQ bus mentioned earlier. So, our interrupt will have Interrupt #2 Handler Vector entry, right after keyboard IRQ :

DCD SysTick_HandlerDCD Timer_Handler

DCD KB_HandlerDCD Input_Handler

DCD UART_Handler DCD 0 DCD 0

• Writing the interrupt handler :

Input_Handler PROCEXPORT Input_Handler IMPORT INPUT_ISR




PUSH {R0,LR} BL INPUT_ISRPOP {R0,PC}ENDP

• Writing the C code for the ISR (Interrupt Service Routine) function, which is in our case is INPUT_ISR(). It helps us initialize the climate control system and turn it on/off:

void INPUT_ISR(){if((ir_code)==7){

on_off=!on_off;if(on_off==true)

turn_on_function();else if(on_off==false)

turn_off_function();end();

}}

3. Discussion

3.1. Problems Encountered During the project implementation, I have encountered a few minor problems which have been solved quickly. Most of them were caused by lack of experience and documentation.

3.2. Engineering Resources Used

For the project implementation, there was no need for other resources other than the resources mentioned in section 1.5. For documentation part were used:

• TinyCAD : for designing the RCB sketch;• Photoshop CS5 evaluation : for certain diagrams;

I spent about 300 hours to develop the project and this interval includes:• Learning Verilog basics;• Learning how to integrate ARM Cortex M0 IP core and creating a custom AHB-Lite SoC

system;• Creating AHB-Lite Peripherals : AHBINPUT and AHB2CTRL;• Developing the other Verilog specific modules (for reading the temperature , decoding IR

signal , generating PWM signal , displaying temperature on a 7 segment display);• Developing the software part in C (cooling and heating algorithms , user interface

functions) and Assembly (interrupt handling);• Hardware component design and assembling;• Making the project documentation;• Other improvements;

In the following table will be provided some design summary of the FPGA usage.




Device Utilization Summary [-]

Slice Logic Utilization Used Available Utilization Note(s)

Number of Slice Registers 1,478 18,224 8%

Number used as Flip Flops 1,469

Number used as Latches 8

Number used as Latch-thrus 0

Number used as AND/OR logics 1

Number of Slice LUTs 5,288 9,112 58%

Number used as logic 4,571 9,112 50%

Number using O6 output only 3,811

Number using O5 output only 226

Number using O5 and O6 534

Number used as ROM 0

Number used as Memory 673 2,176 30%

Number used as Dual Port RAM 664




Number used as Single Port RAM 0

Number used as Shift Register 9




Number used exclusively as route-thrus 44

Number with same-slice register load 34

Number with same-slice carry load 10

Number with other load 0

Number of occupied Slices 1,823 2,278 80%

Nummber of MUXCYs used 392 4,556 8%

Number of LUT Flip Flop pairs used 5,530

Number with an unused Flip Flop 4,159 5,530 75%




Number with an unused LUT 242 5,530 4%

Number of fully used LUT-FF pairs 1,129 5,530 20%

Number of unique control sets 169

Number of slice register sites lost to control set restrictions

783 18,224 4%

Number of bonded IOBs 97 232 41%

Number of LOCed IOBs 97 97 100%

Number of RAMB16BWERs 32 32 100%

Number of RAMB8BWERs 0 64 0%

Number of BUFIO2/BUFIO2_2CLKs 0 32 0%

Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%

Number of BUFG/BUFGMUXs 3 16 18%

Number used as BUFGs 3

Number used as BUFGMUX 0

Number of DCM/DCM_CLKGENs 0 4 0%

Number of ILOGIC2/ISERDES2s 0 248 0%

Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%

Number of OLOGIC2/OSERDES2s 0 248 0%

Number of BSCANs 0 4 0%

Number of BUFHs 0 128 0%

Number of BUFPLLs 0 8 0%

Number of BUFPLL_MCBs 0 4 0%

Number of DSP48A1s 0 32 0%

Number of ICAPs 0 1 0%

Number of MCBs 0 2 0%

Number of PCILOGICSEs 0 2 0%

Number of PLL_ADVs 0 2 0%

Number of PMVs 0 1 0%

Number of STARTUPs 0 1 0%

Number of SUSPEND_SYNCs 0 1 0%

Average Fanout of Non-Clock Nets 5.12

Table 3 – FPGA Usage Statistics




3.3. Marketability

This system could be easily integrated in a real-life system with minor modifications (besides some software tweaks, the light bulb and PC fan will be replaced by a heating unit, respectively AC unit).

3.4. Community Feedback

I have posted on the following forums: forums.xilinx.com, eevblog.com/forum/, forums.hackaday. com, community.arm.com,

I did not receive a solid feedback from the community, maybe because the project theme is common in everyday life use. On the eevblog site I have received a few answers. Some members recommended to use a microcontroller instead of FPGA. One user went further and suggested a specific microcontroller (Parallax Propeller [13] - a powerful microcontroller, with eight 32-bit RISC CPU cores, which has some special "video registers" for use in generating PAL, NTSC, VGA, servo-control, or other timing signals ). Another recommendation was to use a TSOP34438 or TSOP4438 instead of my TSOP4838 IR Receiver. The TSOP4838 IR receiver is an AGC2 legacy receiver and could cause trouble in some kind of environments. On the other hand, I have received positive feedback from persons who had a face-to-face contact with my project design. I had the following recommendations (which I have implemented):

• Finding a method to “erase” the text from the screen (creating a clear screen function which I have explained it in section 2.2.1.2).

• Displaying an interactive menu where I could navigate with arrows, without entering in a mode with A, B or other key buttons; in the initial phase I could enter in heating or cooling mode by pressing A or B button.

• Adding threshold values to an option menu; a threshold value in our case represents a value at which the heating/cooling system will start. For example, if the threshold value set for the heating system is 3, the heating process will exit passive and enter active state when the current temperature is 3 degrees lower than the setpoint. The cooling process behaves similarly (it will enter the active state when the current temperature is 3 degrees higher than the setpoint). Each mode has its own threshold value; this remains valid until turning off the whole system (it will reset threshold values to initial values).

• Displaying continuously the current temperature on the Nexys3’s 7segment display; for a general user, it is very helpful to see the current temperature at all time, without entering the menu displayed on the VGA monitor.




3.5. Conclusions

FPGA climatic is a project that can be easily implemented in our daily lives. I have demonstrated the reason for choosing Nexys 3 FPGA board and implementing the Cortex M0 Core IP. The following goals have been achieved:

• Learning Verilog basics;• Integrate ARM Cortex M0 Design Start IP core and creating a custom AHB-Lite SoC system

with peripherals;• Developing other Verilog specific modules ( for temperature measuring and display, IR

decode, PWM signal generation); • Developing clear_screen() function for C software; • Creating the cooling/heating algorithms in C;• Handling remote control IRQ in Verilog and Assembly;• Developing interactive user interface in C;• Hardware component design and assembling ;• Other improvements ;

4. References

[1] http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture#Advanced_High-performance_Bus_.28AHB.29 [2] http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture[3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0033a/index.html [4] http://www.hipeac.net/system/files/cm0ds_1_0.pdf [5] FPGA Prototyping by Verilg Examples – Pong P. Chu – page 312[6] PmodTMP™ Reference Manual – page 1[7] DS1626 Reference Manual - page 9[8] http://www.ti.com/lit/an/swra323/swra323.pdf [9] www. vishay .com/docs/80071/dataform.pdf [10] Nexys3 Reference Manual – page 19[11] http://en.wikipedia.org/wiki/PID_controller[12] http://web.mit.edu/clarkds/www/Files/slides1. pdf [13] http://en.wikipedia.org/wiki/Parallax_Propeller



http://en.wikipedia.org/wiki/Parallax_Propeller

http://web.mit.edu/clarkds/www/Files/slides1.pdf

http://en.wikipedia.org/wiki/PID_controller

http://www.vishay.com/docs/80071/dataform.pdf

http://www.ti.com/lit/an/swra323/swra323.pdf

http://www.hipeac.net/system/files/cm0ds_1_0.pdf

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0033a/index.html


Appendix A: Xilinx Project – HDL Design Part – Verilog Modules

Here is the structure and the source files of the HDL Design ( source files of the Verilog modules which are not own production or not modified were not included in this project documentation; source files which are not own IP and were modified are included here with a “modified” mention ). A part of the modules were included from the CM0DS-DesignKit and they have a copyright header in the project file.

Figure 25 – Xilinx Project StructureAHB_Lite_SoC.v :

module AHB_Lite_SoC(// clockinput wire CLK,// memory inout wire [15:0] MemDB,output wire [26:1] MemAdr,output wire RamCS,output wire FlashCS,output wire MemWR,output wire MemOE,output wire RamUB,output wire RamLB,output wire RamCre,output wire RamAdv,output wire RamClk,input wire RamWait,output wire FlashRp,// UART




input wire RsRx,output wire RsTx,

// board ledoutput wire LED,

//Nexys Board Inputs input wire sw1, input wire sw2,

// PmodTmp inputs input wire [7:0] temperature,

// IR receiver inputs input wire [3:0] remote_code, input wire irq_remote,

// PWM outputs output wire [5:0] output_speed,

// Relays output output wire relay_out, output wire relay_out2,

// VGA I/O output wire [2:0] vga_red, output wire [2:0] vga_green, output wire [1:0] vga_blue, output wire hsync, output wire vsync, //PS2 I/O input wire ps2d, input wire ps2c );// AHB-Lite master output signalswire HCLK;wire HRESETn;wire [31:0] HADDR;wire [31:0] HWDATA;wire HWRITE;wire [1:0] HTRANS;wire [2:0] HBURST;wire HMASTLOCK;wire [3:0] HPROT;wire [2:0] HSIZE;wire LOCKUP;wire TXEV;wire SLEEPING;wire [15:0] IRQ;

//AHB-Lite master input signalswire [31:0] HRDATA;wire HRESP;wire HREADY;




// select signalswire [3:0] MUX_SEL;wire HSEL_MEM;wire HSEL_CTRL;wire HSEL_UART;wire HSEL_INPUTS;wire HSEL_VGA;wire HSEL_KB;wire HSEL_TIMER;//slave read datawire [31:0] HRDATA_MEM;wire [31:0] HRDATA_CTRL;wire [31:0] HRDATA_UART;wire [31:0] HRDATA_INPUTS;wire [31:0] HRDATA_VGA;wire [31:0] HRDATA_KB;wire [31:0] HRDATA_TIMER;wire HREADYOUT_MEM;wire HREADYOUT_CTRL;wire HREADYOUT_UART;wire HREADYOUT_INPUTS;wire HREADYOUT_VGA;wire HREADYOUT_KB;wire HREADYOUT_TIMER;//SYSTEM GENERATES NO ERROR RESPONSEassign HRESP = 1'b0;// Cortex M0 interrupt signalsassign IRQ = {12'b0000_0000_0000,UART_IRQ,INPUTS_IRQ,KB_IRQ,TIMER_IRQ};assign LED = LOCKUP;// clock divider and resetreg rCLK;always @(posedge CLK)

rCLK <= ~rCLK;assign HCLK = rCLK;assign HRESETn = !sw1;

// cortex M0 DS- masterCORTEXM0DS u_cortexm0ds (

.HCLK (HCLK),

.HRESETn (HRESETn),

.HADDR (HADDR[31:0]),

.HBURST (HBURST[2:0]),

.HMASTLOCK (HMASTLOCK),

.HPROT (HPROT[3:0]),

.HSIZE (HSIZE[2:0]),

.HTRANS (HTRANS[1:0]),

.HWDATA (HWDATA[31:0]),

.HWRITE (HWRITE),

.HRDATA (HRDATA[31:0]),

.HREADY (HREADY),

.HRESP (HRESP),

.NMI (1'b0),




.IRQ (IRQ[15:0]),

.TXEV (),

.RXEV (1'b0),

.LOCKUP (LOCKUP),

.SYSRESETREQ (),

.SLEEPING ());

// AHB-Lite Adress DecoderAHBDCD uAHBDCD (

.HADDR(HADDR[31:0]),

.HSEL_S0(HSEL_MEM),

.HSEL_S1(HSEL_CTRL),

.HSEL_S2(HSEL_UART),

.HSEL_S3(HSEL_INPUTS),

.HSEL_S4(HSEL_VGA),

.HSEL_S5(HSEL_KB),

.HSEL_S6(HSEL_TIMER),

.HSEL_NOMAP(HSEL_NOMAP),

.MUX_SEL(MUX_SEL[3:0]));

// AHB-Lite Slave to Master MulitplexorAHBMUX uAHBMUX (

.HCLK(HCLK),

.HRESETn(HRESETn),

.MUX_SEL(MUX_SEL[3:0]),

.HRDATA_S0(HRDATA_MEM),

.HRDATA_S1(HRDATA_CTRL),

.HRDATA_S2(HRDATA_UART),

.HRDATA_S3(HRDATA_INPUTS),

.HRDATA_S4(HRDATA_VGA),

.HRDATA_S5(HRDATA_KB),

.HRDATA_S6(HRDATA_TIMER),

.HRDATA_NOMAP(32'hDEADBEEF),

.HREADYOUT_S0(HREADYOUT_MEM),

.HREADYOUT_S1(HREADYOUT_CTRL),

.HREADYOUT_S2(HREADYOUT_UART),

.HREADYOUT_S3(HREADYOUT_INPUTS),

.HREADYOUT_S4(HREADYOUT_VGA),

.HREADYOUT_S5(HREADYOUT_KB),

.HREADYOUT_S6(HREADYOUT_TIMER),

.HREADYOUT_NOMAP(1'b1),

.HRDATA(HRDATA[31:0]),

.HREADY(HREADY));

// AHB-Lite Memory Controller AHB2SRAMFLSH uAHB2SRAMFLSH (

.HCLK(HCLK),

.HRESETn(HRESETn),


.HSEL(HSEL_MEM),

.HREADY(HREADY),

.HSIZE(HSIZE[2:0]),




.HTRANS(HTRANS[1:0]),

.HWDATA(HWDATA[31:0]),

.HWRITE(HWRITE),

.HRDATA(HRDATA_MEM[31:0]),

.HREADYOUT(HREADYOUT_MEM),

.FlashAtZero(sw2),

.MemDB(MemDB),

.MemAdr(MemAdr[26:1]),

.RamCS(RamCS),

.FlashCS(FlashCS),

.MemWR(MemWR),

.MemOE(MemOE),

.RamUB(RamUB),

.RamLB(RamLB),

.RamCre(RamCre),

.RamAdv(RamAdv),

.RamClk(RamClk),

.RamWait(RamWait),

.FlashRp(FlashRp) ); // AHB-Lile slave output control peripheralAHB2CTRL uAHB2CTRL (

.HCLK(HCLK),

.HRESETn(HRESETn),

.HSEL(HSEL_CTRL),

.HREADY(HREADY),



.HWRITE(HWRITE),

.HRDATA(HRDATA_CTRL),

.HREADYOUT(HREADYOUT_CTRL),

.CTRL({relay_out,relay_out2,output_speed[5:0]}));

//AHB-Lite slave UART controllerwire UART_IRQ;AHBUART uAHBUART(

.HCLK(HCLK),

.HRESETn(HRESETn),




.HWRITE(HWRITE),

.HREADY(HREADY),

.HREADYOUT(HREADYOUT_UART),

.HRDATA(HRDATA_UART[31:0]),

.HSEL(HSEL_UART),

.RsRx(RsRx),

.RsTx(RsTx),

.uart_irq(UART_IRQ) );

//AHB-Lite slave INPUTS wire INPUTS_IRQ;




AHBINPUT uAHBINPUTS( .HCLK(HCLK), .HRESETn(HRESETn), .HADDR(HADDR[31:0]), .HWRITE(HWRITE), .HWDATA(HWDATA[31:0]), .HTRANS(HTRANS), .HSEL(HSEL_INPUTS), .HREADY(HREADY), .INPUTSIN({3'b0000,irq_remote,remote_code[3:0],temperature[7:0]}), .HREADYOUT(HREADYOUT_INPUTS), .HRDATA(HRDATA_INPUTS[31:0]),

.inputs_irq(INPUTS_IRQ) );

//AHB-Lite VGA controller AHBVGA uAHBVGA( .HCLK(HCLK), .HRESETn(HRESETn), .HADDR(HADDR[31:0]), .HWRITE(HWRITE), .HWDATA(HWDATA[31:0]), .HTRANS(HTRANS[1:0]), .HSEL(HSEL_VGA), .HREADY(HREADY), .HREADYOUT(HREADYOUT_VGA), .HRDATA(HRDATA_VGA[31:0]), .rgb({vga_red,vga_green,vga_blue}), .hsync(hsync), .vsync(vsync) );

//AHB-Lite Keyboard Controllerwire KB_IRQ; AHBKB uAHBKB( .HCLK(HCLK), .HRESETn(HRESETn), .HADDR(HADDR[31:0]), .HWRITE(HWRITE), .HWDATA(HWDATA[31:0]), .HTRANS(HTRANS[1:0]), .HSEL(HSEL_KB), .HREADY(HREADY), .HREADYOUT(HREADYOUT_KB), .HRDATA(HRDATA_KB[31:0]), .ps2d(ps2d), .ps2c(ps2c), .kb_irq(KB_IRQ) );

// AHB-Lite timerwire TIMER_IRQ; AHBTIMER uAHBTIMER( .HCLK(HCLK), .HRESETn(HRESETn),




.HADDR(HADDR[31:0]), .HTRANS(HTRANS[1:0]), .HWDATA(HWDATA[31:0]), .HWRITE(HWRITE), .HREADY(HREADY), .HREADYOUT(HREADYOUT_TIMER), .HRDATA(HRDATA_TIMER[31:0]), .HSEL(HSEL_TIMER), .timer_irq(TIMER_IRQ) );

endmodule

AHBDCD.v (modified):

module AHBDCD( input wire [31:0] HADDR, output wire HSEL_S0, output wire HSEL_S1, output wire HSEL_S2, output wire HSEL_S3, output wire HSEL_S4, output wire HSEL_S5, output wire HSEL_S6, output wire HSEL_NOMAP, output reg [3:0] MUX_SEL );

reg [15:0] dec;// //MEMORY MAP --> START ADDR END ADDR SIZE assign HSEL_S0 = dec[0]; //MEMORY MAP --> 0x0000_0000 to 0x00FF_FFFF 16MBassign HSEL_S1 = dec[1]; //MEMORY MAP --> 0x5000_0000 to 0x50FF_FFFF 16MBassign HSEL_S2 = dec[2]; //MEMORY MAP --> 0x5100_0000 to 0x51FF_FFFF 16MBassign HSEL_S3 = dec[3]; //MEMORY MAP --> 0x5200_0000 to 0x52FF_FFFF 16MBassign HSEL_S4 = dec[4]; //MEMORY MAP --> 0x5300_0000 to 0x53FF_FFFF 16MBassign HSEL_S5 = dec[5]; //MEMORY MAP --> 0x5400_0000 to 0x54FF_FFFF 16MBassign HSEL_S6 = dec[6]; //MEMORY MAP --> 0x5500_0000 to 0x55FF_FFFF 16MBassign HSEL_NOMAP = dec[15]; //REST OF REGION NOT COVERED ABOVE

always@*begin case(HADDR[31:24]) 8'h00: //MEMORY MAP --> 0x0000_0000 to 0x00FF_FFFF 16MB begin dec = 16'b0000_0000_00000001; MUX_SEL = 4'b0000; end 8'h50: //MEMORY MAP --> 0x5000_0000 to 0x50FF_FFFF 16MB begin dec = 16'b0000_0000_0000_0010; MUX_SEL = 4'b0001; end 8'h51: //MEMORY MAP --> 0x5100_0000 to 0x51FF_FFFF 16MB begin dec =16'b0000_0000_0000_0100;




MUX_SEL = 4'b0010; end 8'h52: //MEMORY MAP --> 0x5400_0000 to 0x52FF_FFFF 16MB begin dec = 16'b0000_0000_0000_1000; MUX_SEL = 4'b0011; end 8'h53: //MEMORY MAP --> 0x5300_0000 to 0x53FF_FFFF 16MB begin dec = 16'b0000_0000_0001_0000; MUX_SEL = 4'b0100; end 8'h54: //MEMORY MAP --> 0x5400_0000 to 0x54FF_FFFF 16MB begin dec = 16'b0000_0000_0010_0000; MUX_SEL = 4'b0101; end 8'h55: //MEMORY MAP --> 0x5500_0000 to 0x55FF_FFFF 16MB begin dec = 16'b0000_0000_0100_0000; MUX_SEL = 4'b0110; end default: //NOMAP begin dec = 16'b1000_0000_00000000; MUX_SEL = 4'b1111; end endcaseend

endmodule

AHBMUX.v (modified):

module AHBMUX( //GLOBAL CLOCK & RESET input wire HCLK, input wire HRESETn,

//MUX SELECT FROM ADDRESS DECODER input wire [3:0] MUX_SEL,

//READ DATA FROM ALL THE SLAVES input wire [31:0] HRDATA_S0, input wire [31:0] HRDATA_S1, input wire [31:0] HRDATA_S2, input wire [31:0] HRDATA_S3, input wire [31:0] HRDATA_S4, input wire [31:0] HRDATA_S5, input wire [31:0] HRDATA_S6, input wire [31:0] HRDATA_NOMAP,

//READYOUT FROM ALL THE SLAVES input wire HREADYOUT_S0, input wire HREADYOUT_S1,




input wire HREADYOUT_S2, input wire HREADYOUT_S3, input wire HREADYOUT_S4, input wire HREADYOUT_S5, input wire HREADYOUT_S6, input wire HREADYOUT_NOMAP,

//MULTIPLEXED HREADY & HRDATA TO MASTER output reg HREADY, output reg [31:0] HRDATA

);

reg [3:0] APHASE_MUX_SEL; always@ (posedge HCLK or negedge HRESETn) begin if(!HRESETn) APHASE_MUX_SEL <= 4'h0; else if(HREADY) // NOTE: ALL THE CONTROL SIGNALS ARE VALID ONLY IF HREADY = 1'b1 APHASE_MUX_SEL <= MUX_SEL; end

always@* begin case(APHASE_MUX_SEL) 4'b0000: begin // SELECT SLAVE0 RESPONSE & DATA IF PREVIOUS APHASE WAS FOR S0 HRDATA = HRDATA_S0; HREADY = HREADYOUT_S0; end

4'b0001: begin HRDATA = HRDATA_S1; HREADY = HREADYOUT_S1; end




4'b0101: begin HRDATA = HRDATA_S5;




HREADY = HREADYOUT_S5; end


default: begin HRDATA = HRDATA_NOMAP; HREADY = HREADYOUT_NOMAP; end endcase endendmodule

AHB2CTRL.v :

module AHB2CTRL(//AHBLITE INTERFACE

//Slave Select Signalsinput wire HSEL,

//Global Signalinput wire HCLK,input wire HRESETn,

//Address, Control & Write Datainput wire HREADY,input wire [31:0] HADDR,input wire [1:0] HTRANS,input wire HWRITE,input wire [2:0] HSIZE,

input wire [31:0] HWDATA,// Transfer Response & Read Data

output wire HREADYOUT,output wire [31:0] HRDATA,

// Controled Outputoutput wire [7:0] CTRL

);//Address Phase Sampling Registers reg rHSEL; reg [31:0] rHADDR; reg [1:0] rHTRANS; reg rHWRITE; reg [2:0] rHSIZE;

reg [7:0] rCTRL;

//Address Phase Sampling always @(posedge HCLK or negedge HRESETn) begin

if(!HRESETn) begin

rHSEL <= 1'b0;rHADDR <= 32'h0;




rHTRANS <= 2'b00;rHWRITE <= 1'b0;rHSIZE <= 3'b000;

end else if(HREADY) begin rHSEL <= HSEL;

rHADDR <= HADDR;rHTRANS <= HTRANS;rHWRITE <= HWRITE;rHSIZE <= HSIZE;

end end

//Data Phase data transfer always @(posedge HCLK or negedge HRESETn) begin if(!HRESETn) rCTRL <= 8'b0000_0000; else if(rHSEL & rHWRITE & rHTRANS[1]) rCTRL <= HWDATA[7:0]; end

//Transfer Response assign HREADYOUT = 1'b1; //Read Data assign HRDATA = {24'h0000_00,rCTRL}; // Assign value to output assign CTRL = rCTRL;

endmodule

AHBINPUT.v :

module AHBINPUT(input wire HCLK,input wire HRESETn,input wire [31:0] HADDR,input wire [1:0] HTRANS,input wire [31:0] HWDATA,input wire HWRITE,input wire HSEL,input wire HREADY,

input wire [15:0] INPUTSIN,

//Outputoutput wire HREADYOUT,output wire [31:0] HRDATA,output wire inputs_irq

);




//localparam [7:0] input_data_addr = 8'h00; reg [15:0] input_data; reg [15:0] input_data_next; reg [31:0] last_HADDR; reg [1:0] last_HTRANS; reg last_HWRITE; reg last_HSEL; integer i; assign HREADYOUT = 1'b1; // Set Registers from address phase always @(posedge HCLK) begin if(HREADY) begin last_HADDR <= HADDR; last_HTRANS <= HTRANS; last_HWRITE <= HWRITE; last_HSEL <= HSEL; end end // Update input_data ports always @(posedge HCLK, negedge HRESETn) begin if(!HRESETn) input_data <= 16'h0000; else input_data <= INPUTSIN; end

assign HRDATA[15:0] = input_data;

assign inputs_irq= INPUTSIN[12];

endmodule

vga_console.v ( modified ) :

module vga_console( input wire clk, input wire resetn, input wire video_on, input wire [9:0] pixel_x, input wire [9:0] pixel_y, input wire font_we, //font write input wire [7:0] font_data, //input 7-bit ascii value output reg [7:0] text_rgb, //output color output reg scroll //signals scrolling




);

//Screen tile parameters localparam MAX_X = 40; //Number of horizontal tiles localparam MAX_Y = 10; //Number of tile rows //Font ROM wire [10:0] rom_addr; wire [6:0] char_addr; wire [3:0] row_addr; wire [2:0] bit_addr; wire [7:0] font_word; wire font_bit; //Dual port RAM wire [11:0] addr_r; wire [11:0] addr_w; wire [6:0] din; wire [6:0] dout; //Cursor reg [6:0] cur_x_reg; wire [6:0] cur_x_next; reg [4:0] cur_y_reg; wire [4:0] cur_y_next; wire cursor_on; //pixel buffers reg [9:0] pixel_x1; reg [9:0] pixel_x2; reg [9:0] pixel_y1; reg [9:0] pixel_y2; wire [7:0] font_rgb; //color for text wire [7:0] font_inv_rgb; //color for text with cursor on top reg current_state; reg next_state; wire return_key; //carriage return or '\n' wire new_line; //move cursor to next line //reg scroll; reg scroll_next; reg [4:0] yn; //row count reg [4:0] yn_next; reg [6:0] xn; //horizontal count reg [6:0] xn_next; wire verify_char; //Module Instantiation font_rom ufont_rom( .clk(clk), .addr(rom_addr),




.data(font_word) ); dual_port_ram_sync #(.ADDR_WIDTH(12), .DATA_WIDTH(7)) uvideo_ram ( .clk(clk), .we(we), .addr_a(addr_w), .addr_b(addr_r), .din_a(din), .dout_a(), .dout_b(dout) ); //State Machine for cursor and pixel buffer always @ (posedge clk, negedge resetn) begin if(!resetn) begin cur_x_reg <= 0; cur_y_reg <= 0;

endelse if(din==7'b0001101) // if we have character 13 ( carriage return ) to

display begin

cur_x_reg <= 0; cur_y_reg <= 0;

end else begin cur_x_reg <= cur_x_next; cur_y_reg <= cur_y_next; pixel_x1 <= pixel_x; pixel_x2 <= pixel_x1; pixel_y1 <= pixel_y; pixel_y2 <= pixel_y1; end end

//Font ROM Access assign row_addr = pixel_y[3:0]; //row value assign rom_addr = {char_addr,row_addr}; //ascii value and row of character assign bit_addr = pixel_x2[2:0]; //delayed assign font_bit = font_word[~bit_addr]; //output from font rom //Return key found assign return_key = (din == 6'b001101 || din == 6'b001010) && ~scroll; // Return || "\n" //Backspace




assign back_space = (din == 6'b001000); //New line logic assign new_line = font_we && ((cur_x_reg == MAX_X-1) || return_key); //Next Cursor Position logic assign cur_x_next = (new_line) ? 0 : (back_space && cur_x_reg) ? cur_x_reg - 1 : (font_we && ~back_space && ~scroll) ? cur_x_reg + 1 : cur_x_reg; assign cur_y_next = (cur_y_reg == MAX_Y-1) ? cur_y_reg : ((new_line) ? cur_y_reg + 1 : cur_y_reg );

//Color Generation assign font_rgb = (font_bit) ? 8'b11111111 : 8'b00000000; //white:black assign font_inv_rgb = (font_bit) ? 8'b0000000 : 8'b00000000; //black:black //Display logic for cursor assign cursor_on = (pixel_x2[9:3] == cur_x_reg) && (pixel_y2[8:4] == cur_y_reg); //RAM Write Enable assign we = font_we || scroll; //Display combinational logic always @* begin if(~video_on) text_rgb = 8'h00; else if(cursor_on) text_rgb = font_inv_rgb; else text_rgb = font_rgb; end //Console state machine always @(posedge clk, negedge resetn) if(!resetn) begin scroll <= 1'b0; yn <= 5'b00000; xn <= 7'b0000000; current_state <= 1'b0; end else begin scroll <= scroll_next; yn <= yn_next; xn <= xn_next; current_state <= next_state; end //Console next state logic always @*




begin scroll_next = scroll; xn_next = xn; yn_next = yn; next_state = current_state; case(current_state) 1'b0: //Waits for a new line and the cursor on the last line of the screen if(new_line && (cur_y_reg == MAX_Y-1)) begin scroll_next = 1'b1; next_state = 1'b1; yn_next = 0; xn_next = 7'b1111111; //Delayed by one cycle end else scroll_next = 1'b0; 1'b1: //Counts through every tile and refreshes begin if(xn_next == MAX_X) begin xn_next = 7'b1111111; //Delayed by one cycle yn_next = yn + 1'b1; if(yn_next == MAX_Y) begin next_state = 1'b0; scroll_next = 0; end end else xn_next = xn + 1'b1; end endcase end //RAM Write assign addr_w = (scroll) ? {yn,xn} : {cur_y_reg, cur_x_reg}; assign din = (scroll) ? dout : font_data[6:0]; //RAM Read assign addr_r =(scroll) ? {yn+1'b1,xn_next} : {pixel_y[8:4],pixel_x[9:3]}; assign char_addr = dout;

endmodule

temp_value.v :

module temp_value(temp_in,degree,decimal,unit,tens);input [7:0] temp_in;output [3:0] degree;output [3:0] decimal;reg [3:0] decimal;output [3:0] unit;output [3:0] tens;




wire [3:0] c1,c2,c3,c4,c5,c6,c7;wire [3:0] d1,d2,d3,d4,d5,d6,d7;wire [7:0] value;assign value={1'b0,temp_in[7:1]};assign d1 = {1'b0,value[7:5]};assign d2 = {c1[2:0],value[4]};assign d3 = {c2[2:0],value[3]};assign d4 = {c3[2:0],value[2]};assign d5 = {c4[2:0],value[1]};assign d6 = {1'b0,c1[3],c2[3],c3[3]};assign d7 = {c6[2:0], c4[3]};add3 m1 (d1,c1);add3 m2 (d2,c2);add3 m3 (d3,c3);add3 m4 (d4,c4);add3 m5 (d5,c5);add3 m6 (d6,c6);add3 m7 (d7,c7);

assign unit={c5[2:0],value[0]};assign tens={c7[2:0],c5[3]};always @* begin

case (temp_in[0])1'b0: begin

decimal=4'b0000;end

1'b1: begindecimal=4'b0101;end

endcaseend

assign degree=4'b1100;endmodule

dcd7seg.v :

module dcd7seg( hexcode,segout );input [3:0] hexcode;output [6:0] segout;reg [6:0] segout;always @*begin

case(hexcode)4'b0001 : segout = 7'b1111001;4'b0010 : segout = 7'b0100100;4'b0011 : segout = 7'b0110000;4'b0100 : segout = 7'b0011001;4'b0101 : segout = 7'b0010010;4'b0110 : segout = 7'b0000010;4'b0111 : segout = 7'b1111000;4'b1000 : segout = 7'b0000000;4'b1001 : segout = 7'b0010000;




4'b1100 : segout = 7'b1000110;default : segout = 7'b1000000;

endcaseend

endmodule

muxselect7seg.v :

module muxselect7seg(selection,an,point );input [1:0] selection;output [3:0] an;reg [3:0] an;output point;reg point;

always @*begincase(selection)

2'b00 : an = 4'b1110;2'b01 : an = 4'b1101;2'b10 : an = 4'b1011;2'b11 : an = 4'b0111;default : an = 4'b0000;

endcaseend

always @*begincase(selection)

2'b10 : point =1'b0;default : point =1'b1;

endcaseend

endmodule

module digitmux(degree,decimal,unit,tens,out_value,selection );

input [3:0] degree; input [3:0] decimal; input [3:0] unit; input [3:0] tens; input [1:0] selection; output [3:0] out_value; reg [3:0] out_value; always @*begincase(selection)

2'b00 : out_value = degree;2'b01 : out_value = decimal;2'b10 : out_value = unit;default : out_value = tens;




endcaseend

endmodule

pmodtmp.v :

module pmodtmp(inout dq, // dq - we send commands to the

sensor and read the temperatureinput clock, // Nexys clock inputoutput reg clock_conv, // clock output used for PmodTmpoutput reg rst_n, // reset pinoutput reg [7:0] temp_out // output 8-bit temperature

);

/* Autoreset module - we use it to reset the sensor at every 1 second,in order to convert and read a new value.

*/

autoreset autoreset (.clock(clock), .reset(reset)

);

reg [11:0] temp; // temp register ( we store the 12bit temperature reading in it )

reg [7:0] data_out; // command registerreg [2:0] state;reg [3:0] bit_count; // counts bits sent and received reg [2:0] clk_count;reg command_byte; // 0 or 1,depending on which byte command is sent reg mode; // mode determines transmit/receive modeparameter Tr = 1'b1; // transmit parameterparameter Rec = 1'b0; // receive parameter

/* state parameters */parameter [2:0] START = 3'b000; parameter [2:0] LOAD_DATA = 3'b001; parameter [2:0] Tr_BYTE = 3'b010; parameter [2:0] Rec_TEMP = 3'b011; parameter [2:0] STOP = 3'b100;

// command parameters ( convert / read temperature )parameter [7:0] read_temp_command = 8'hAA; parameter [7:0] start_conv_command = 8'h51;

reg [11:0] temperature_reading = 0;reg temp_ready;reg [6:0] q;

// counter logic




always @(posedge clock, posedge reset) beginif(reset) q <= 0;else q <= q+1;

end

wire virtual_clk;assign virtual_clk = q[6]; // clk256

// Temperature State Machinealways @ (posedge virtual_clk or posedge reset) begin

if (reset) begin

rst_n <= 0; clock_conv <= 1; command_byte <= 0; bit_count <= 0; clk_count <= 0; temp_ready <= 0; state <= START; temperature_reading <= 0;temp <= 0;

end

else if (1) // if reset is 0 begin // state case //

case (state) /*

Start state :*/START: begin

rst_n <= 1;mode <= Tr; // transmit modestate <= LOAD_DATA; // jump to LOAD_DATA state

end/*

Load Data state*/LOAD_DATA: begin/*

If command_byte is 0 then we will send the convert command

else we will send the temperature read command*/

case(command_byte) 0: begin

data_out <= start_conv_command; // first it will be sent the start convert command

end 1: begin

data_out <= read_temp_command; // and after that the read temperature command

end endcase state <= Tr_BYTE; // jump to next state




end

/*Transmit Byte State

*/

Tr_BYTE: begin case(clk_count)

0: begin clock_conv <= 0;clk_count <= clk_count + 1;

end 1: begin // RISING EDGE CLOCK

if (bit_count > 0) begin data_out <= {1'b0, data_out[7:1]};

// transmitting commandend clk_count <= clk_count + 1;

end 2: begin

clock_conv <= 1;clk_count <= clk_count + 1;

end 3: begin

if (bit_count < 7) begin state <= Tr_BYTE; // return to

transmit byte state if we still have to transmit bitsbit_count <= bit_count + 1; clk_count <= 0;

end else if (!command_byte) begin

state <= STOP;bit_count <= 0; clk_count <= 0;

end else begin

state <= Rec_TEMP;bit_count <= 0; mode <= Rec; clk_count <= 2;

end end

endcase end/*

Receive temperature state*/Rec_TEMP: begin

case(clk_count) 0: begin

clock_conv <= 1; temperature_reading <= {dq,

temperature_reading[11:1]}; // receive temperatureclk_count <= clk_count + 1;

end




1: begin clk_count <= clk_count + 1;

end 2: begin

clock_conv <= 0; clk_count <= clk_count + 1;

end 3: begin // FALLING EDGE OF THE CLOCK SIGNAL

clk_count <= 0; if (bit_count < 12) begin // if we have

incoming data state <= Rec_TEMP; // return to

receive temperature statebit_count <= bit_count + 1;

end else begin

state <= STOP; // jump to stop state if we don't have any incoming data

bit_count <= 0; end

end endcase

end/*

Stop state*/STOP: begin

rst_n <= 0; if (!command_byte) begin

state <= START; command_byte <= command_byte + 1;

end else begin

state <= START; temp_ready <= 1;if(temp_ready)begin

temp <= temperature_reading;temp_ready <= 0;

endclk_count <= 0; clock_conv <= 1;

end // Temperature assignment ( positive temperature , with only one

decimal part : bits 10 to 3);temp_out[0]=temp[3];temp_out[1]=temp[4];temp_out[2]=temp[5];temp_out[3]=temp[6];temp_out[4]=temp[7];temp_out[5]=temp[8];temp_out[6]=temp[9];temp_out[7]=temp[10];end

endcase end




end

assign dq = (mode) ? data_out[0] : 1'bz;

endmodule

autoreset.v :

module autoreset(clock,reset);

/*Inputs and outputs

*/

input clock;output reset;reg reset;

/* Parameters

*/parameter period = 200000000; // 2 seconds for our 100 MHz clockparameter halfperiod = period / 2; // half periodreg [31:0] countvalue;

always@(posedge clock)begin

if(countvalue==period-1)begin

countvalue =0 ;reset =0;

endelse

countvalue=countvalue+1;if(countvalue==halfperiod)

reset =1;end

endmodule

irreceiver.v :

module irreceiver( input clock,

input remote_in, input reset, output reg [3:0] remote_out, output reg irq_signal );

/*

Parameters and registers */




reg [13:0] timer = 0; reg [2:0] state_reg = 0; // state register reg [2:0] next_state = 0; reg data = 0;

reg [7:0] bit_timer = 1; reg [9:0] q = 0; wire virtual_clk; reg [5:0]bit_counter = 34; reg [31:0] data_reading = 0; wire [23:0] data_in; parameter WAIT = 3'b000; // wait state parameter HEADER = 3'b001; // header state ( hearder code ) parameter OFF = 3'b010; // off state ( off code ) parameter DATA = 3'b011; // data state parameter DATA_OFF = 3'b100; //data off parameter DATA_NEXT = 3'b101;

// state FSM always @(posedge clock)

if(reset) state_reg <= WAIT;

elsestate_reg <= next_state;

// counter logic always @(posedge clock)begin

if(virtual_clk || reset)q <= 0;

else q <= q + 1;

end

assign virtual_clk = (q==999);

/*States

*/

always @(*)case(state_reg)

WAIT: begin // wait stateif(remote_in == 0) // if we have the first low logic

signal -> jump to next state ( HEADER )next_state <= HEADER;

else // else we will remain in WAIT statenext_state <= WAIT;

end

HEADER: begin // header code , we have to examine after 9 ms remote_in signal

if(timer == 9900 && remote_in == 1)begin




next_state <= OFF; // jump to next stateend

else if(timer == 9900 && remote_in == 0)next_state <= WAIT; // jump to wait state

elsenext_state <= HEADER;

end

OFF: begin // off codeif(timer == 9470 && remote_in == 0)begin

next_state <= DATA; // start reading dataend

else if(timer == 9470 && remote_in == 1) next_state <= WAIT; // jump to wait state

elsenext_state <= OFF; // jump back to off state

end// DATA , DATA_OFF and DATA_NEXT states are used to determine

the 1 and 0 logic statesDATA: begin

if(timer == 3200 && remote_in == 1)beginnext_state <= DATA_OFF;end

else if(timer == 3200 && remote_in == 0)beginnext_state <= WAIT;end

else next_state <= DATA;

end

DATA_OFF: beginif(timer == 0 && remote_in == 1)begin

next_state <= WAIT;endelse if(timer == 0 && remote_in == 0)

next_state <= DATA_NEXT;else

next_state <= DATA_OFF;end

DATA_NEXT: beginif(timer < 50 && remote_in == 0)begin

next_state <= DATA_NEXT;end

else if(timer == 0 && remote_in == 1)next_state <= WAIT;

elsenext_state <= DATA_NEXT;

endendcase

// timer logic always @(posedge clock) begin

if(reset) begintimer <= 10850;




endelsecase(state_reg)

WAIT: beginif(remote_in == 0) begin

timer <= 10850;end

end

HEADER: beginif(virtual_clk)

timer <= timer - 1;end

OFF: beginif(virtual_clk)


DATA: beginif(virtual_clk)


DATA_OFF: beginif(virtual_clk)


DATA_NEXT: beginif(timer < 50 && remote_in == 0) begin

timer <= 10850;endelse if (virtual_clk && timer > 0)


endcaseend

// Data reading logicalways @(posedge clock) begin

if(reset) beginbit_timer <= 1;bit_counter <= 34;

endelse if(state_reg == DATA && virtual_clk) begin

bit_timer <= bit_timer - 1;

if(bit_timer == 0 && remote_in == 0 && bit_counter > 0) begin

bit_timer <= 111; // 1,12 msdata <= 0;bit_counter <= bit_counter - 1;data_reading <= {data, data_reading[31:1]};




endelse if (bit_timer == 0 && remote_in == 1 && bit_counter >

0) beginbit_timer <= 223; // 2,24 msdata <= 1;bit_counter <= bit_counter - 1;data_reading <= {data, data_reading[31:1]};

endelse if(bit_timer == 0 && remote_in == 1 && bit_counter ==

0) beginbit_timer <= 1;

end end else if(state_reg == DATA_NEXT || state_reg == DATA_OFF)

bit_counter <= 0; else if(state_reg == WAIT)

bit_counter <= 34; end

assign data_in = (bit_counter == 0 ) ? data_reading[23:0] : 24'b0000_0000_0000_0000_0000_0000;

// key assignmentalways @* begincase (data_in)

24'b000110111111011100001000: begin // on/off key

remote_out = 4'b0111;

irq_signal = 1;end

24'b000111111111011100001000: remote_out = 4'b0001; // A key24'b000111101111011100001000: remote_out = 4'b0010; // B key24'b000110101111011100001000: remote_out = 4'b0011; // C key24'b000010001111011100001000: remote_out = 4'b1000; // left key24'b000001001111011100001000: remote_out = 4'b0101; //ok key24'b000000011111011100001000: remote_out = 4'b1001; // right key24'b000001011111011100001000: remote_out = 4'b0110; //up key24'b000000001111011100001000: remote_out = 4'b0100; //down key24'b000000000000000000000000: begin

remote_out = 4'b0000; // other case

irq_signal = 0;end

endcaseend

endmodule




PWM.v :

module PWM(clock,input_speed,output_led,pwm_out );

// Inputs , outputs input clock; // clock signal input [5:0] input_speed; // 6 bit input value from SoC system output [5:0] output_led; // output of the 6 bit value output pwm_out; // pwm signal output reg pwm_out; // Parameters parameter step_delay = 1560; // ( ~100000/64) reg [16:0] counter =0; assign output_led=input_speed;

// it generates the 1 ms pwm signal always @(posedge clock) begin

counter=counter+1;if(counter <= input_speed*step_delay) // duty cycle

pwm_out = 1; else

pwm_out = 0;if(counter>=100_000)

counter = 0; // counter resetend

endmodule

ARMSOC_S6.ucf :

Net "CLK" LOC=V10 ;

Net "FlashCS" LOC = L17 ; Net "FlashRp" LOC = T4 ;

Net "MemAdr<1>" LOC = K18 ; Net "MemAdr<2>" LOC = K17 ; Net "MemAdr<3>" LOC = J18 ; Net "MemAdr<4>" LOC = J16 ; Net "MemAdr<5>" LOC = G18 ; Net "MemAdr<6>" LOC = G16 ; Net "MemAdr<7>" LOC = H16 ; Net "MemAdr<8>" LOC = H15 ; Net "MemAdr<9>" LOC = H14 ; Net "MemAdr<10>" LOC = H13 ; Net "MemAdr<11>" LOC = F18 ; Net "MemAdr<12>" LOC = F17 ; Net "MemAdr<13>" LOC = K13 ; Net "MemAdr<14>" LOC = K12 ;




Net "MemAdr<15>" LOC = E18 ; Net "MemAdr<16>" LOC = E16 ; Net "MemAdr<17>" LOC = G13 ; Net "MemAdr<18>" LOC = H12 ; Net "MemAdr<19>" LOC = D18 ; Net "MemAdr<20>" LOC = D17 ; Net "MemAdr<21>" LOC = G14 ; Net "MemAdr<22>" LOC = F14 ; Net "MemAdr<23>" LOC = C18 ; Net "MemAdr<24>" LOC = C17 ; Net "MemAdr<25>" LOC = F16 ; Net "MemAdr<26>" LOC = F15 ;

Net "MemDB<0>" LOC = R13 ; Net "MemDB<1>" LOC = T14 ; Net "MemDB<2>" LOC = V14 ; Net "MemDB<3>" LOC = U5 ; Net "MemDB<4>" LOC = V5 ; Net "MemDB<5>" LOC = R3 ; Net "MemDB<6>" LOC = T3 ; Net "MemDB<7>" LOC = R5 ; Net "MemDB<8>" LOC = N5 ; Net "MemDB<9>" LOC = P6 ; Net "MemDB<10>" LOC = P12 ; Net "MemDB<11>" LOC = U13 ; Net "MemDB<12>" LOC = V13 ; Net "MemDB<13>" LOC = U10 ; Net "MemDB<14>" LOC = R8 ; Net "MemDB<15>" LOC = T8 ; Net "MemOE" LOC = L18 ; Net "MemWR" LOC = M16 ; Net "RamAdv" LOC = H18 ; Net "RamWait" LOC = V4 ; Net "RamClk" LOC = R10 ; Net "RamCS" LOC = L15 ; Net "RamCre" LOC = M18 ;Net "RamUB" LOC = K15 ;Net "RamLB" LOC = K16 ;

## LedsNet "LED" LOC = T11 ;

## SwitchesNet "reset" LOC = V9 ; Net "sw1" LOC = T10;Net "sw2" LOC = T9 ;

# Usb-RS232 interfaceNet "RsRx" LOC = N17 | PULLUP; Net "RsTx" LOC = N18 ;

## VGA ConnectorNET "vga_red<0>" LOC = U7 ; NET "vga_red<1>" LOC = V7 ; NET "vga_red<2>" LOC = N7 ;




NET "vga_green<0>" LOC = P8 ; NET "vga_green<1>" LOC = T6 ; NET "vga_green<2>" LOC = V6 ; NET "vga_blue<0>" LOC = R7 ; #NET "vga_blue<1>" LOC = T7 ;NET "hsync" LOC = N6 ; NET "vsync" LOC = P7 ;

##Pic USB-HID interfaceNet "ps2d" LOC = J13 | PULLUP; Net "ps2c" LOC = L12 | PULLUP;

## Input and output pinsNET "remote_in" LOC = K5;NET "relay_out" LOC = G3;NET "relay_out2" LOC = J6;NET "pwm_out" LOC = H3;Net "dq" Loc=V12;Net "clock_conv" Loc=P11;Net "rst_n" Loc=T12;

#led outputsNET "output_led<0>" LOC=U16;NET "output_led<1>" LOC=V16;NET "output_led<2>" LOC=U15;NET "output_led<3>" LOC=V15;NET "output_led<4>" LOC=M11;NET "output_led<5>" LOC=N11;

#7 segment display outputsNET "point" Loc=M13;Net "segout<0>" Loc=T17;Net "segout<1>" Loc=T18;Net "segout<2>" Loc=U17;Net "segout<3>" Loc=U18;Net "segout<4>" Loc=M14;Net "segout<5>" Loc=N14;Net "segout<6>" Loc=L14;Net "an<0>" Loc=N16;Net "an<1>" Loc=N15;Net "an<2>" Loc=P18;Net "an<3>" Loc=P17;




Appendix B: Xilinx Project – HDL Design Part – Schematics

Figure 26 - temp_7seg_display schematics

Figure 27 - digitselcounter schematics




Figure 28 – display7seg schematics




Appendix C: Keil uVision Project – Software Design Part

This part contains the other part of the project design. The retarget.c file and the part of the Vector Table Map and IRQ handlers from cm0dsasm.s are not part of my own work. They re used from the Cortex M0 Design Start - EDK.

CM0-DS.h:

// System memory

#define RAM_SIZE 0x1000000 // 16 MB of PSRAM on Digilent Board

#define RAM_START 0x0#define RAM_END RAM_START + RAM_SIZE

// Peripheral memory map //

#define AHB_CTRL_BASE 0x50000000#define AHB_UART_BASE 0x51000000#define AHB_INPUT_BASE 0x52000000#define AHB_VGA_BASE 0x53000000#define AHB_KEYBOARD_BASE 0x54000000#define AHB_TIMER_BASE 0x55000000

retarget.c:

#include <stdio.h>#include <time.h>#include <rt_misc.h>#include "./CM0-DS.h"

#pragma import(__use_no_semihosting)

// Implement a simple structure for C's FILE handle and // define the location of the output console (VGA)// define the location of the input (KB)

struct __FILE { unsigned char * ptr;};

FILE __stdout = {(unsigned char *) AHB_VGA_BASE};FILE __stdin = {(unsigned char *) AHB_KEYBOARD_BASE};int printchar(int ch){

unsigned char* VgaPtr;VgaPtr = (unsigned char*)AHB_VGA_BASE;*VgaPtr = (char)ch;return(ch);

}int fputc(int ch, FILE *f){



Figure 29 – uVision Project structure


return(printchar(ch));}int ferror(FILE *f){ return 0; }

int FromKeyBoard(){

char ch;unsigned char* KBPtr;KBPtr = (unsigned char*)AHB_KEYBOARD_BASE;ch = *KBPtr;printchar(ch);return((int)ch);

}

int fgetc(FILE *f){ return(FromKeyBoard());}

void _ttywrch(int ch){ fputc(ch,&__stdout); }

void _sys_exit(void) {while(1);

}

cm0dsasm.s :

Stack_Size EQU 0x00040000 AREA STACK, NOINIT, READWRITE, ALIGN=4Stack_Mem SPACE Stack_Size__initial_spHeap_Size EQU 0x00100000 AREA HEAP, NOINIT, READWRITE, ALIGN=4__heap_baseHeap_Mem SPACE Heap_Size__heap_limit; Vector Table

PRESERVE8 THUMB

AREA RESET, DATA, READONLY EXPORT __Vectors

__Vectors DCD __initial_sp DCD Reset_Handler DCD NMI_Handler DCD HardFault_Handler DCD 0 DCD 0




DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD SVC_Handler DCD 0 DCD 0 DCD PendSV_Handler DCD SysTick_Handler DCD Timer_Handler DCD KB_Handler

DCD Input_Handler DCD UART_Handler DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 DCD 0 AREA |.text|, CODE, READONLY;Reset HandlerReset_Handler PROC GLOBAL Reset_Handler ENTRY LDR R1, =0xE000E100 ;Interrupt Set Enable Register LDR R0, =0x0000007F STR R0, [R1]

IMPORT __main LDR R0, =__main BX R0 ;Branch to __main ENDP NMI_Handler PROC B . ENDP HardFault_Handler\ PROC B . ENDP SVC_Handler PROC B . ENDP PendSV_Handler PROC




B . ENDP

SysTick_Handler PROC B . ENDP Timer_Handler PROC EXPORT Timer_Handler

PUSH {R0,R1,LR} POP {R0,R1,PC} ENDPInput_Handler PROC

EXPORT Input_HandlerIMPORT INPUT_ISRPUSH {R0,LR}BL INPUT_ISRPOP{R0,PC}

ENDP

UART_Handler PROC EXPORT UART_Handler

IMPORT UART_ISR PUSH {R0,R1,R2,LR}

BL UART_ISR LDR R1, =0x51000000 ;UART LDR R2, =0x53000000 ;VGA LDR R0, [R1] ;Get Data from UART STR R0, [R2] ;Write to VGA

POP {R0,R1,R2,PC} ENDP

KB_Handler PROC EXPORT KB_Handler PUSH {R0,R1,R2,R3,LR} LDR R1, =0x56000000 ;KB LDR R2, =0x54000000 ;UART LDR R3, =0x53000000 ;VGA LDR R0, [R1] ;Read from KB STR R0, [R2] ;Write out on UART STR R0, [R3] ;Display on VGA POP {R0,R1,R2,R3,PC} ENDP ALIGN 4 AREA Test, CODE

ALIGN 4

; User Initial Stack & Heap

IF :DEF:__MICROLIB




EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap__user_initial_stackheap

LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR

ALIGN

ENDIF

END

MyProgram.c ://// This C file contains the :// * menu display functions ; // * cooling and heating algorithms ;//

#include "./CM0-DS.h"#include <stdio.h>#include <rt_misc.h>#include <stdbool.h>#define ir_code (int)((*(unsigned int*)AHB_INPUT_BASE&0x0F00)>>8) // ir_code pins#define ctrl_out (*(unsigned int*)AHB_CTRL_BASE) // output control

// Variablesint i; // index counter

int bittemp[8]; // to store the temperature from the 8-bit busfloat temperature; // temperature value with decimal part

bool on_off=false; // to know in which state is our control platformbool forced_exit=false;

// used to know what menu position to display on screenint index_menu=0; int index_options_menu=0;




int setpoint=0; // the desired temperature

// threshold valuesint threshold_heat=2; int threshold_heat_tmp;int threshold_cool=2;int threshold_cool_tmp;float threshold_temperature;

// Variables used for PID controllerfloat pid_error; // pid error ( the difference between the setpoint and the current temperature )float last_pid_err=0;float integrative_val=0;float derivative_val=0;float proportional_val=0;float pid_value=0;int dt=1;int ctrl_value; // pid output value

// Function prototypes

void INPUT_ISR(void);void turn_on_function(void);void turn_off_function(void);void set_mode(void);

void heating_mode(void);void apply_heating(void);

void cooling_mode(void);void apply_cooling(void);void pid_out(void);void control_block(void);

void show_menu(void);void options_menu(void);void show_options_menu(void);void option_menu_modified(int increase);

void end(void);void delay(int count);void clear_screen(void);

void show_temperature(void);void get_temperature(void);

void UART_ISR(void);

// Main function




int main(void) {while(1);

}

void UART_ISR() //{

printf("\n From UART \n ");}

// function called by ir remote IRQ/* If we pressed the on/off button (it has code 7 ) ,then it will turn on/off the system , depending on situation; */void INPUT_ISR(){

if((ir_code)==7){on_off=!on_off;if(on_off==true)

turn_on_function();else if(on_off==false)

turn_off_function();end();

}}

/* This is the clear_screen function. When we will print on the screen character 13 ( carriage return ),it will set the cursor to the original position (0,0) . After that we will fill the vga ram memory with empty spaces ( to overwrite the existing characters ) , and print the \r character again for cursor repositioning ;*/void clear_screen(){

printf("%c",13);for(i=0;i<8;i++)

printf(" ");

printf("%c",13);}

/* a rudimentary Delay function */void delay(int count){

for(i=0;i<count;i++);}

/* Function used to correct signal transmision of our remote control. */void end(){

while((*(unsigned int*)AHB_INPUT_BASE&0x0F00)!=0);}

/* Turn off function. Furthermore , it resets settings to default. */void turn_off_function(){




printf("\nTurning off... ");threshold_cool=2;threshold_heat=2;index_menu=0;index_options_menu=0;setpoint=0;delay(30000);clear_screen();

}

/* Turn on function. It display on the screen a menu from where we can choose one of the options it will dynamically display a certain "menu" according to selected option; */void turn_on_function(){

index_menu=0;index_options_menu=0;printf("\n \n Welcome!");delay(30000);clear_screen();printf("\n Options:\n > 1. Heating Mode \n 2. Cooling Mode\n

3. Options");while(ir_code!=5 && ir_code!=7){

while(ir_code==0); // wait until we receive a command/* according to what key we press ( down - 4, or up -6 ) it

will show the current menuwith an arrow indicating the current selection

*/if(ir_code==4){

clear_screen();index_menu++; // index_menu is used to know the position

we are in the menu and to know how to redraw the menuif(index_menu>2)

index_menu=0;show_menu();

}else if(ir_code==6){

clear_screen();index_menu--;if(index_menu<0)

index_menu=2;show_menu();

}

}

if(ir_code==5){ // if we pressed the okay button we will enter in the chosen option

printf("\n OK! ");delay(30000);




clear_screen();switch(index_menu){

case 0: heating_mode();break;

case 1: cooling_mode();break;

case 2: options_menu();break;

}}if(ir_code==7){

INPUT_ISR();}

}

/* Show menu function . Displays the menu "image" according to our index selection */void show_menu(){

switch(index_menu){case 0:

printf("\n Options :\n > 1. Heating Mode \n 2. Cooling Mode \n 3. Options");

break;

case 1:printf("\n Options :\n 1. Heating Mode \n > 2.

Cooling Mode\n 3. Options");break;

case 2:printf("\n Options :\n 1. Heating Mode \n 2.

Cooling Mode\n > 3. Options");break;

}

}

/* Set mode function. It displays the current temperature . We have the possibility

to set a desired temperature by pressing up or down keys. We can set a desired

temperature between 0 and 99. Furthermore, we can abort anytime our action and

return to main menu;

*/void set_mode(){




printf("Current temperature : ");show_temperature();printf("%cC\nSet your temperature : ",14);printf("%d%cC",setpoint,14);while(ir_code!=5 && ir_code!=7){

while(ir_code==0); // wait until we press a key;if(ir_code==6) // if we pressed up key ( increase ){

if(setpoint<10){ // if setpoint is lower than ten it will backspace 3 characters and display the increased setpoint

printf("\b\b\b");setpoint+=1;printf("%d%cC",setpoint,14);end();

}else if(setpoint<99){ // if setpoint is lower than 99 it

will backspace 4 characters and display the new valueprintf("\b\b\b\b");setpoint+=1;printf("%d%cC",setpoint,14);end();

}

}else if(ir_code==4) // if we pressed down key ( decrease ){

if(setpoint<10 && setpoint>0){ // if setpoint is lower than 10 and bigger than 0

// it will backspace 3 characters and display the new value

printf("\b\b\b");setpoint-=1;printf("%d%cC",setpoint,14);end();

}else if (setpoint>=10){ // if setpoint is bigger than 10

it will backspace 4 characters and display the new valueprintf("\b\b\b\b");setpoint-=1;printf("%d%cC",setpoint,14);end();

}}

}if(ir_code==7) // if we pressed the on off button, we will return to

the main menu{

forced_exit=true;printf("\n Operation aborted...");ctrl_out=0x00;




delay(30000);setpoint=0;

clear_screen();return;

}else // if we pressed the okay button{

forced_exit=false;printf(" OK! ");delay(30000);clear_screen();

}

}

/* Cooling mode function. */void cooling_mode(){

clear_screen();printf("\n Cooling mode on! \n");delay(30000);set_mode();if(forced_exit==true)

goto exit; apply_cooling();

if(forced_exit==true)goto exit;

exit: // returns to main menuturn_on_function();

}

/* Apply cooling function. It contains the cooling control algorithm */void apply_cooling(){

threshold_temperature=(float)setpoint+threshold_cool;while(ir_code!=7){

active_cooling:while(ir_code!=7){

printf("\nCurrent : ");show_temperature();printf("%cC\nSetpoint :",14);printf(" %d%cC",setpoint,14);if(((float)setpoint<temperature) && (ir_code!=7)){

pid_out();}else{

clear_screen();goto pause_cooling;




}for(i=0;i<30000;i++){

if(ir_code==7){

ctrl_out=0x00;clear_screen();goto exit_cooling;

}}clear_screen();

}

pause_cooling: ctrl_out=0x00;printf("Going to pause...");delay(50000);clear_screen();while(ir_code!=7){

i=0;while(i<9999){

i++;if(ir_code==7)

goto exit_cooling;}get_temperature();if(temperature>=threshold_temperature){

delay(20000);goto active_cooling;

}}goto exit_cooling;

}exit_cooling:

printf("\n Operation aborted .. ");setpoint=0;delay(50000);ctrl_out=0x00;integrative_val=0;proportional_val=0;derivative_val=0;pid_value=0;ctrl_value=0;clear_screen();forced_exit=true;return;

}

/* Pid out function; calculates the PID value for the PWM output */




void pid_out(){last_pid_err=pid_error;pid_error=temperature-setpoint;proportional_val=10*pid_error;integrative_val+=pid_error;derivative_val=1*(pid_error-last_pid_err)/dt;pid_value=proportional_val+(0.2*integrative_val)+derivative_val;control_block();

}

/* In this function we process the PID value and we send the final value to the

PWM verilog module through a 6bit bus data*/ void control_block(){

ctrl_value=(int)pid_value;if(ctrl_value>=63.0) ctrl_out=0x7F; // max speedelse if(ctrl_value<63.0)

ctrl_out=ctrl_value+64; }

/* Heating mode function. */void heating_mode(){

clear_screen();printf("\n Heating mode on! \n");delay(30000);set_mode(); // set temperature functionif(forced_exit==true) // If we aborted by pressing the on/off button

goto exit;apply_heating();if(forced_exit==true)

goto exit;exit: //returns to main menu

turn_on_function();}

/* Apply heating function. It contains the heating control algorithm */ void apply_heating(){

threshold_temperature=(float)setpoint-threshold_heat;while(ir_code!=7){

active_heating:while(ir_code!=7){

printf("\nCurrent : "); show_temperature();printf("%cC\nSetpoint :",14);printf(" %d%cC",setpoint,14); // if the temperature is lower than the setpoint the

heating system is turned on




if(((float)setpoint>temperature) && (ir_code!=7)) {

ctrl_out=0x80;}else // otherwise it enters the pasive state

( pause_heating){

ctrl_out=0x00;clear_screen();goto pause_heating;

}for(i=0;i<70000;i++){ // a small delay ( if we press

the on/off key we will abort this mode )if(ir_code==7){

goto exit_heating;}

}clear_screen();

}pause_heating:

printf("Going to pause...");delay(30000);clear_screen();while(ir_code!=7){

i=0;while(i<9999){ // delay ( if we press the

on/off key we will abort this mode )i++;if(ir_code==7)

goto exit_heating;}get_temperature();/* if the current temperature is lower or equal

to the threshold temperature it will enter the active state (active_heating). For example if

we have setpoint=29 degrees , a threshold value at 2 degrees , it means that if the current

temperature is equal or lower than 27 degrees( 27 = 29 -2 ) , then the heating system will

be turned on again.*/if(temperature<=threshold_temperature){

delay(20000);goto active_heating;

}}goto exit_heating;

}exit_heating: // aborts current operation




printf("\n Operation aborted .. ");setpoint=0;ctrl_out=0x00;delay(30000);clear_screen();forced_exit=true;return;

}

/* Options menu function. Here we can change the threshold values for cooling and heating modes */void options_menu(){

clear_screen();threshold_heat_tmp=threshold_heat; // we will store the last values

in some "temporary" variablesthreshold_cool_tmp=threshold_cool;printf("\n Options menu: \n > 1. Heating Mode Threshold : ");printf("%d%cC",threshold_heat_tmp,14);printf("\n 2. Cooling Mode Threshold : ");printf("%d%cC",threshold_cool_tmp,14);while(ir_code!=7 && ir_code!=5){

while(ir_code==0); // wait until we press a key// the menu display algorithm ( similar to the main menu )if(ir_code==4){

clear_screen();index_options_menu++;if(index_options_menu>1)

index_options_menu=0;show_options_menu();

}else if(ir_code==6){

clear_screen();index_options_menu--;if(index_options_menu<0)

index_options_menu=1;show_options_menu();

}else if(ir_code==8){ // if we press left or right key we can

increment or decrement threshold value for each modeclear_screen();option_menu_modified(1); // show modified values for

heating mode threshold value}else if(ir_code==9){

clear_screen();option_menu_modified(2); // show modified values for

cooling mode threshold value}

}




if(ir_code==7){

printf("\n Operation aborted...");delay(30000);

clear_screen();turn_on_function();

}if(ir_code==5)

printf("\n OK! Exiting to main menu...");threshold_cool=threshold_cool_tmp; // getting new valuesthreshold_heat=threshold_heat_tmp;delay(30000);clear_screen();turn_on_function();

}

/* This function displays the menu according to current selection */void show_options_menu(){

switch(index_options_menu){case 0:

printf("\n Options menu: \n > 1. Heating Mode Threshold : ");

printf("%d%cC",threshold_heat_tmp,14);printf("\n 2. Cooling Mode Threshold :

");printf("%d%cC",threshold_cool_tmp,14);break;

case 1:printf("\n Options menu: \n 1. Heating

Mode Threshold : ");printf("%d%cC",threshold_heat_tmp,14);printf("\n > 2. Cooling Mode Threshold :

");printf("%d%cC",threshold_cool_tmp,14);break;

}}

/* This function displays the menu and the new threshold value according to selected option.

The threshold value can vary between 1 and 9 degrees.

*/void option_menu_modified(int increase){

switch(index_options_menu){

case 0 : {if(increase==1){




if(threshold_heat_tmp>1){threshold_heat_tmp-=1;printf("\n Options

menu: \n > 1. Heating Mode Threshold : ");printf("%d

%cC",threshold_heat_tmp,14);printf("\n 2. Cooling

Mode Threshold : ");printf("%d

%cC",threshold_cool_tmp,14);end();}else{threshold_heat_tmp=1;printf("\n Options




%cC",threshold_cool_tmp,14);end();}

}else if(increase==2){

if(threshold_heat_tmp<9){threshold_heat_tmp+=1;printf("\n Options




%cC",threshold_cool_tmp,14);end();}else{threshold_heat_tmp=9;printf("\n Options




%cC",threshold_cool_tmp,14);




end();}

}break;

}case 1 : {

if(increase==1){if(threshold_cool_tmp>1){threshold_cool_tmp-=1;printf("\n Options

menu: \n 1. Heating Mode Threshold : ");printf("%d

%cC",threshold_heat_tmp,14);printf("\n > 2. Cooling


%cC",threshold_cool_tmp,14);end();}else{threshold_cool_tmp=1;printf("\n Options




%cC",threshold_cool_tmp,14);end();}

}else if(increase==2){

if(threshold_cool_tmp<9){threshold_cool_tmp+=1;printf("\n Options




%cC",threshold_cool_tmp,14);end();}else{threshold_cool_tmp=9;




printf("\n Options menu: \n 1. Heating Mode Threshold : ");

printf("%d%cC",threshold_heat_tmp,14);

printf("\n > 2. Cooling Mode Threshold : ");

printf("%d%cC",threshold_cool_tmp,14);

end();}

}

break;}

}}

/* Get temperature is a function which gets the temperature from a 8 bit data bus and converts it into a float variable */void get_temperature(){

for(i=0;i<8;i++){

bittemp[i]=(*(unsigned int*)AHB_INPUT_BASE&(1<<i))>>i;}

temperature=(bittemp[0]*0.5)+(bittemp[1]*1)+(bittemp[2]*2)+(bittemp[3]*4)+(bittemp[4]*8)+(bittemp[5]*16)+(bittemp[6]*32)+(bittemp[7]*64);}

/* This function is used to display the temperature. Unfortunately the SoC system cannot display on the screen a float or

double variable ( only integer or character ). */ void show_temperature(){

get_temperature(); if(bittemp[0]==0) // if the decimal bit is 0 , we will display the integer part of the temperature and ".0" characters

{printf("%d.0",(int)temperature);

}else // we will display the integer part of the temperature and

".5" characters{

printf("%d.5",(int)temperature);}

}




Appendix D: List with Design Flow Charts

Here is the list with the flowchart submitted along the project documentation (folder flowcharts):

Name Commentslegend.jpg Color Legend for flowcharts

apply_cooling.jpg apply_cooling() function flowchartapply_heating.jpg apply_heating() function flowchartclear_screen.jpg clear_screen() function flowchartcontrol_block.jpg control_block() function flowchartcooling_mode.jpg cooling_mode() function flowchartheating_mode.jpg heating_mode() function flowchart

option_menu_modified.jpg options_menu_modified() function flowchartoptions_menu.jps options_menu() function flowchart

set_mode.jpg set_mode() function flowchartshow_menu.jpg show_menu() function flowchart

show_options_menu.jpg show_options_menu() function flowchartturn_on_function.jpg turn_on_function() function flowchart




Appendix E: FPGA Climatic board description



design contest report - fpga climatic 2

Documents