Microelectronic Engineering 61–62 (2002) 681–686www.elsevier.com/ locate /mee

Design and fabrication of colloid-based vertical nanoscaledevices

a,b , a b*A.J. Parker , P.A. Childs , R.E. PalmeraSemiconductor Devices Group, Emerging Device Technology Research Centre, School of Engineering,

University of Birmingham, Edgebaston, Birmingham B15 2TT, UKbNanoscale Physics Research Laboratory, School of Physics and Astronomy, University of Birmingham,

Edgebaston, Birmingham B15 2TT, UK

Abstract

The design and fabrication of a vertical nanodevice with an active region based on gold colloidalnanoparticles deposited on a silicon nanopillar is presented. Devices are fabricated in parallel using naturallithography to create an array of silicon pillars. The nanoscale volume of the active region results from thecombination of silicon pillar technology coupled with well controlled vertical processing. The results in thispaper show the fabrication procedure at each stage, leading to a structure designed to demonstrate proof ofprincipal of our approach. 2002 Published by Elsevier Science B.V.

Keywords: Vertical nanodevice; Gold colloidal nanoparticles; Silicon nanopillar; Natural lithography

Following the experimental observation of coulomb blockade, a great deal of research has centredupon utilising the phenomenon within electronic devices. Many of the designs for these devices havefocused on the use of small, typically # 20 nm diameter, conducting clusters (either pre-formed anddeposited, or simply lithographically defined into the substrate), as these inherently exhibit a blockadeto electron tunnelling at elevated temperatures [1]. The patterning of clusters for devices is primarilyreliant on the relatively slow process of e-beam lithography, while the deposition of pre-formed, sizeselected, clusters from solution is both quick and parallel [2–4], making the latter extremely attractivein the industrial environment. The key challenge, however, in using solution-based clusters, is toreliably and with repeatability position a small number (preferably one) within the active deviceregions, whilst avoiding the formation of parasitic devices. Significant efforts have centred on theproduction of ordered films of clusters [5–11], and more recently on their selective area deposition[12,13], but such approaches still rely on the patterning of nanoscale device architectures prior tocluster incorporation. Vertical device designs, however, offer an interesting route toward high densityIC structures, with the advantage that vertical cluster growth can be restricted to monolayer formation

*Corresponding author.

0167-9317/02/$ – see front matter 2002 Published by Elsevier Science B.V.PI I : S0167-9317( 02 )00442-2

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[14]. A further benefit of this type of structure is that the critical vertical dimensions can be very wellcontrolled and not restricted by lithography, making the approach both parallel and, therefore, quick.

Here, the design and fabrication of a vertical nanodevice with an active region based on goldcolloidal nanoparticles deposited on a silicon nanopillar is presented. The overall size of our structureis larger than the device we wish to produce as the processing is intended to provide proof of principalof the fabrication procedure. Fig. 1 outlines the fabrication procedure of the vertical device. Theprocess begins with the formation of silicon nanopillars by natural lithography (Fig. 1a) [15–17](using polystyrene balls and sputtered chromium to define an etch mask). Each pillar is required to beelectrically isolated and the surface needs to be planarised (Fig. 1b), so that the pillar tops cansubsequently be accessed for colloid deposition. Exposure of the pillar tops (Fig. 1c), followed by ashort etch to lower the tops of the pillars below the height of the planarising layer (Fig. 1d), generatesnanoscale tubes in the planarised surface. Once the tubes on the surface have been generated, amonolayer of gold nanoparticles are positioned on top of the pillar; adhesion to the pillar is achievedby the growth of a self-assembled monolayer (SAM) which binds the colloids to the silicon (Fig. 1e).It is in this way, that control over the lateral size of the active device region is obtained, relying not onhigh resolution lithography, but rather the relatively simple fabrication of nanopillars. With thecolloids positioned on top of the pillar, the tube can be filled with a non-conducting polymer whichwill passivate the colloids in the pit and electrically isolate them so that a final top contact can beapplied to complete the device (Fig. 1f).

Silicon pillars were formed using the technique of natural lithography: 2 mm diameter polystyrene1spheres in aqueous solution were simply drop-deposited onto clean n -type (0.006–0.012 V cm)

silicon (110) wafers and chilled to slow the evaporation of the water. Once the polystyrene sphereshad precipitated onto the surface and self-assembled into hexagonal arrays [15–17], the sample wasexposed to a chromium sputter source and | 50 nm of metal deposited. The metal passes through theinterstitial sites in the polyball array leaving a triangular-based hexagonal array mirroring the initialmask. Each pillar will form an individual device, therefore, the number of devices created in parallelis simply dependent upon the size of this initial polyball array. After generation of the metal mask, the

Fig. 1. Schematic outline of the fabrication procedure for vertical device. (a) The generation of a nanopillar array by naturallithography; (b) isolation of the pillars and surface planarisation, (c) exposure of pillar tops, followed by (d) pillar etch for pitproduction. (e) SAM formation and colloid deposition atop the pillars and in the pits. The device is completed (f), with thefilling of the pit with an organic insulator and the evaporation of a top contact. The arrow indicates the flow of currentthrough the pillar to the colloids.

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sample is etched in a low pressure reactive ion etch (RIE) process of sulphur hexafluoride (SF ) and6

carbon tetrachloride (CF ) in the ratio 25:25 sccm at a power of 100 W for 120 s. This etch is highly4

anisotropic, with the CF forming a passivation layer which dramatically reduces the etch rate of the4

silicon surface parallel to the incoming species (i.e. normal to the surface) [18]. The results of thisetch can be seen in the scanning electron microscope (SEM) image of Fig. 2a, taken with an ISIDS-130F. The image, taken at 308 to the normal, clearly shows that the pillars are | 0.5 mm high andhave retained the triangular cross-section of the chromium mask.

The electrical isolation of the pillars and surface planarisation can best be achieved using a liquiddielectric, as this can be deposited with excellent reproducibility and will naturally form a planar

Fig. 2. SEM images showing various stages in the device production. (a) Hexagonal arrays of triangular pillars in silicon,each pillar is | 0.3 mm across and | 0.5 mm tall. (b) The photoresist planarising layer after blanket exposure reveals pillartops followed by the wet chemical etch to generate nanoscale pits in the resist film (c).

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surface. A simple dielectric liquid is photoresist, which can, by removal of the solvent, be transformedinto a pre-cast solid film and has the added advantage of being photo-processable. Microposit S1805(Chestech Ltd.) was deposited over the pre-fabricated pillar arrays, following standard procedure [19],at a spin speed of 6500 rpm to give a film of thickness | 0.5 mm. This film distorts around the pillarsand is observed to cover them. However, a 2-s blanket exposure to UV radiation, followed bydevelopment in Microposit MF319 (Chestech Ltd.) removes the top | 0.1 mm of the photoresist andleaves the pillar tops exposed (Fig. 2b).

The generation of pits in the surface of the photoresist is achieved by etching the silicon below thelevel of the resist. Unfortunately, the use of plasma etching is incommensurate with the photoresistfilm, as the resist is etched more rapidly by the plasma species than the silicon pillars. A wet chemicaletch which has complete specificity to the silicon over the photoresist was, therefore, used. The etchcomprised a mixture of 70% nitric acid (HNO ), 40% ammonium fluoride (NH F) and water (H O),3 4 2

in the ratio 126:5:60 and will etch silicon at a rate of | 300 nm/min, whilst leaving the photoresistfilm completely unharmed [20]. Fig. 2c shows the result of exposing a sample, such as that shown inFig. 2b, to the etchant for 30s. Clearly observable are the triangular-shaped tubes, or pits, in thephotoresist surface at the position of a pillar prior to the etch. This image shows quite clearly thelateral confinement that is achieved following this fabrication route, the maximum device area issimply the width of the etch pit, in this case, | 0.3 mm.

Once the etch pit has been formed, a SAM of 3-aminopropyltrimethoxysilane (APTMS) isdeposited following the method by Sato [14]. The silane group is used to bind the molecule to thehydroxylated surface formed on top of the pillars following the growth of a native oxide duringexposure to the atmosphere. The amino group will bind the gold colloids, when deposited in aqueoussolution on the surface, thereby positioning and fixing them to the pillar top. The SAM is deposited bydiluting the APTMS with distilled water to a concentration of | 0.5% (by volume), and then simplyimmersing the sample for 2.5 min. Once the SAM has been formed, the sample is placed into anaqueous solution of 15 nm diameter gold colloids for at least 24 h. The results of this deposition canbe seen in the SEM images of Fig. 3. The first image (Fig. 3a) shows a plan view of a pillar at thebottom of a shallow etch pit in the photoresist film covered by a film of 15 nm gold colloids. Thelarger triangular outline observed around the pillar is a result of charging in the photoresist film duringimaging with the SEM, and possibly signals some degree of film distortion. It is evident that thedeposition of colloids has not been limited to the silicon pillar but also covers the resist film.Fortunately, this design is tolerant to such extra structure, as it is the colloids positioned on top of thepillar that will determine the operation of the device. Fig. 3b, shows an SEM image of one of thepillars from the array shown in Fig. 3a after the photoresist has been removed by exposure to acetonefor 30 s; the image was taken at an angle of 308 to the normal. This clearly shows the intendedstructure; the colloids, which will form the active region of the device, are bound to the top of thepillar.

In conclusion, we have demonstrated the feasibility of constructing a vertical nanoscale deviceutilising colloids on silicon pillar arrays as the active region of the device. The methods employedduring device processing obviate the need for expensive lithographic techniques and are commensu-rate with current semiconductor processing. While the structure presented in Fig. 2a does notconstitute a fully working device, exposure of such a sample to some form of long alkane chain thiolor amine will bind such molecules to both the colloid and the SAM atop the pillar. In this fashion, thepillar and cluster will be electrically isolated from a top contact [21], which can be produced by

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Fig. 3. (a) Top view of a pillar in an etch pit which has been exposed to APTMS SAM with subsequent exposure to 15-nmcolloids. (b) After removal of the photoresist layer, by exposure to acetone, the structure of colloids atop pillars is clearlyevident.

simply evaporating a metal over the surface. A further modification to this structure would be theinclusion of an annular layer of metal around the active region to provide transistor action. Finally,this structure can be reduced in size laterally by simply using smaller polyballs in the initial array, andgenerating narrower pillars. The 2-nm colloids, rather than the 15-nm colloids used here, could bedeposited into the pits, with the further advantage that the structure should show coulomb blockadelimited transport at temperatures approaching 273 K.

Acknowledgements

The authors would like to thank the UK Engineering and Physical Sciences Research Council forfinancial support for this project.

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