deep sub micron modelling

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DESIGN AND MODELING OFDEEP-SUBMICROMETER MOSFETS

byMin-Ch e Jeng

Mem orandum No. UCB/ERL M90190October 2,1990


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DESIGN AND MODELING OFDEEP-SUBMICROMETER MOSFETS

byMin-Chie Jeng

MemorandumNo. UCBERL M90/902 October 1990

ELECTRONICS RESEARCH LABORATORYCollege of EngineeringUniversity of California, Berkeley94720


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PhcD

Design and Modeling ofDeep-Submicrometer MOSFETsMin-Chie Jeng

ABSTRACTA photoresist ashing technique has been developed which, when used in conjunction with

conventional optical lithography, permits controlled definition of the gate of deepsubmicrometer MOSFETs. 'Ihis technique can also be extended to other lithographicprocesses, such as e - b nd x-ray. Comprehensive studies based on the pedormance andhotelectron reliability hwe shown that the basic physics d a t e d with deepsubmi-devices is similar to that of their longer


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V

Table of Contents

Chapter 1: INTRODUCTION ......................................................................L.......-.. 11.1. design n... ........n........n.........n..-...n...n...n...n...n....n...n...n...n.....-..-.. 212. evicemod$ing ......................... ............................................................... 4

57

13 t l ine .................... ....................... ................................... ..........................-.1.4. References .................................................................. ........................................ ....

Chapter 2:DEVICE FABRICATION ....... .................................................................... 1111.1. Fabrication process ........................................................................................ .........

2 2 Photoresist-ashing technique .......................................................................... .........22.1. Wder ppati0a ................................................ ................................... U.....2 2 2. tchiDg process .......................... .....................................................................2 2 3 l3primataI results ...._............................................................................. .....

23 Device chamAenstics ....................................... .................................................. ..2.4. References ........................................ _...................................... ....... ................Chapter 3:PERFORMANCE AND HOT-ELECTRON RELIABILITY OFDEEP-SUBMICROMETER M O M ................... ........................... ......................

3 2 2 ubthreshold swing .......................................................................... .........3 3.CmeQt driving capability .......................................................................................

121414152327

282937284848


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Chapter 1INTRODUCTION

In the last decade, MOS devices have been miniamid to acbieve higher packing derpsity, higher integration levels, and higher current drive. Recent advances in process technology(1.1-1.71 have made deepsubmicrometer MOSFETs potential candidares for next generationULSI designs. However, by demasing channel length while maintaining the current powersupply voltage, the electric fields in the device will m e r ncrease, causing the device charac-teristics to deviate from the long-channel behavior and also creating reliability problems.

The two high-field effects most pronounced on device performance are the mobilitydegradation due to vertical-field [1.8-1.111 and the carrier velocity saturation [1.12,1.13]. Botheffects cause the MOSFET drain current drive to increase at a slower rate than that predictedby simple scaling theories. The threshold voltage shifiand subthreshold swing IVC also largerat shorter channel lengths and high drain voltages [1.14-1.20) which make short-channel MOStransistors more difficult to turn off. Such parameter variations have a severe impact on worstcase circuit design rules and pose serious problems in VLSI proccss control.

More consequences of the high electric fields in submicrometer devices are the hot-electron effects [1.21,1.22) due to impact ionization in the velocity saturation (piich-oft)region. The injection of energetic electrons released by impact ionization into the Si-SO,interface generates interface traps that degrade the device characteristics, and results in long-term reliability problems [123-1.27]. TIe substrate current, which is composed of impact-ionization-generated holes, can overload the substrate-bias generator and causes snap-back andCMOS atch-up [1.28,129]. In addition to the performance and hotclcctron reliability,whicharc two major concern for the feasibility of deepsubmicrometer MOSFETs in circuit applica-tions, the increasing complexity in circuit designs and fabrication processes is another subjectto consider in developing VLSUULSI systems.


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To avoid the 'ITL compa!ibility pmblans, the wnstant-voltage (CV) nd quasiconstam-voltage (QCV) Seatings w a e proposed. Under these scaling laws, tfre device dimensions arealso scaled by the same factork as in thc CE case,but thc power supply is kept constant (CV)or scaled down by a factor of * QCV). Although these nonconstant field scaling laws aremon practical and result in better device and circuit performance, thc bot-clectron effectsammuch more severe because the channel electric field in the velocity saturation region is incnas-hg rapidly as the device channel length is reduced. .For this reason, it has been generallyrecognized that as long as the power supply remains high for practical considerations, sometype of hotelectron-resistant smcture, like LDD, s needed for submicrometer MOS ransis-tors.

In reality, however, some device parameters, such as the source and drain junctiondepths, are relatively unscalable for most technologies, and the power supply can not be easilyscaled. All of these scaling laws are difficult to apply in practice. They a~ only used as con-ceptual guidelines for minimizing the short-channel andlor hot-clectron effects. Practical scal-ing approaches should be developed based on device performance limitations and constraints asproposed by Masuda (1.331, Bnws [1.34], and Shichijo [1.35] for near-micron devices.Because of technology advances, these design curves and conclusions are not applicable in thedeepsubmicrometer regime. More recent studies for 0.5p.m devices were reported by Takeda[1.36] and Kakumu [1.37]. However, these studies are incomplete as only few design con-straints were considered. For deepsubrnicromekr devices, more physical effects are becomingimportant and should be taken into considerations when developing design guidelines.

In the first part of this report, a comprehensive study of the performance and reliabiityconstraints on the device dimensions and power supply of deepsubmicrometer MOSFJTs ispresented. A set of design cuwes, extracted from experimental results, are developed based onthe following considerations: shortchannel and drain-induced-barrier-lowering effects, off-stateleakage current, hot-electron reliability, timedependent dielectric breakdown, cumnt drivingcapability, voltage gain, and switching speed. Although these design curves are only for n-


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simulations are inadequate in modeling the output nesistuKx tnb the weak-inversioncharac-tenstics, which are very important for analog applications. Since decpsubmiaon devices ypi-Cany have thin gate oxides, the inversion-layer capadtancc becomes comparable to the gatecapacitance, which is an important factor to Consider m circuit simulations. In order to bridgethe gap between deepsubmicrometer devices and circuit simulatia& 1MOSFEI' drain cumntmodel accurate down to quarter-micron channel kngths, suitable for digital as well as analogapplications has been developed bascd on an improved physical understanding of dcepsubmicrometer MOS transistors.

1.3 OutlineChapter 2 describes the fabrication process and some of the characterization procedures

for the deep-submicrometer MOSFETs used in this study.Chapter 3 describes some device characterization methods important to thc short-channel

devices.Chapter 4 presents a set of design cufves derived from experimental results based on a

wide range of design considerations. These design curves provide comprehensive designguidelines for deepsubmicrometer devices. The relative importance of various mechanisms isalso identified.

Chapter 5 describes a deepsubmicrometerMOSFET rain current model suitable for bothdigital and analog simulations. The basic algorithm and theory for parameter extraction arealso briefly described.

Chapter 6 concludes this dissertation.


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Power supply(VdGate oxide (T,J

1/k 1 l/JElk 1bE ltk

Channel length (L)Channel width (W)

Ilk ltk ltkIlk 1/k I/k

Junction depth (xi)Doping concentration (Nm)Threshold voltage (VJ

Ilk l/k l/kk k kIlk 1 l/JE

I I

Saturation current (IDSAT)

Table 1.1 Results of various scaling laws.

Ilk * 1Transconductance (&dOutput resistance (%113

I1 JE JE1 m 1 ~ 4

IPower density (Pm) 1Subthreshold Swing (S) 1

P P1 1


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chap. -9-r1-20]

[1.21]

[1.221[1.231

[1.24]

[1.251

[1.261

(1.271

[1.281

[1.29)

(1.301

of I.mulated-Gate.R. Troutman and S.N. chalrravarti, "S u bb& O ldQlaraaefisbcsTansistoft," IEEE ?"ran. OLI Cirarit T ~ O I Y ,OL m-20, p.659, Nov.,

. .Rdd1973.T.H. Nmg, P.W. cook,RH. ennard, C.M. Osbum, S.E. Schuster, and IN.Yu,"p MOSFE" VLSI Technology,Parr IV. H o t - E l m n Design Constmins," IEEETran. on Electron Devices, voL ED-26, p.346-353,1979.C. Hu, "Hot-Electron Effects in MOSFT's," IEDM Tech Dig., pp.176-181, 1983.H. Gesch, J.P. LebuRon, and GB.Donla, "Generation of Interface States by Hot-Electron Injection," IEEE Tran. on Elcctron Devices, VOL ED-29, .913,1982.E.Takeda and N. Suzuki, "An Empirical Model for Device Degradation due to Hot-Carrier Injection,"IEEE Electron Device Letters, vol. EDL-4, pp.111-113, 1983.E. Takeda,A. Shimizu, and T.Hagiwara, "Role of Hot-Hole Injection in H o t - M e rEfects and the SmallDegraded Channel k a o n n MOSFET's," IEEEElectron DeviceLetters, vol.EDL4, no.9, Sep, 1983.F.C.Hsu and S. Tam."Relationshipbetween MOSFET Degradation and Hot-ElectronInduced Interface-State-Generation," IFlEE Elecmn Device Letters, voL EDL-5, p.50,1984.K-L. Chen, S.A. Saller, I.A. Groves, and D.B.Swtt, "Reliability Effects on MOSTransistors due to H o t - M e r IEEETran. n Electron Devices, voL ED-32,~p.386 -393 , 985.Y.W. Sing and B. Sudlow, "Modeling and VLSI Design Constraints of SubstrateCumnt," IEDM Tech.Dig., p.31, 1975.J. Matsunaga, "Characterization of Two Step Impaa Ionization and It's M u m a onNMOS and PMOS VLSI's," IEDM Tech Dig., p.736, 1980.R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Rideuit, E. Bassous, and AS.LcBIanc, "Design of Ion-Implamtcd MOSFET's with Very Small Physical Dimen-


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Chapter 2DEVICE FABRICATION

-1 1-

The devices used in this study we= n-chand mn-LDD transistars fabricated using anNMOS technology with a photoresist-ashing technique l2.1) to define the gates of deepsubmicrometer devices. Since most steps of this p r o p s arc common to those of standardfabrication processes, only the major procedulles are described. A complete process flow isgiven in Appendix A.

2.1 Fabrication processThe starting wafers have ptype substrates with 15-30 S2pm bulk resistivity. A blanket

boron (B11) implant of 1.5 x lo'* cme2 at 70 KeV was used for both field and punchthmughcontrols. The active area was defined using LQCOS. The field oxide thickness of 2800was grown in wet oxygen at 95OoC and annealed in nitrogen for 20 minutes at the same tcm-perature. The enhancement thmhold implant dose (B11 at 30KeV) were chosen to yield alongchannel threshold voltage around 0.65V for all gate oxide thicknesses. An array of deple-tion implant dose (As, 50KeV) wen used for these wafers because of the difficulty in deter-mining the threshold voltage due to seven shortchannel effeds in depletion-mode devices.

Various gate oxide thicknesses, 3.6,5.6, 7.2, 8.6, and 15.6nm, wen grown in dry oxygenat 800-900"C, depending on the oxide thickness. Immediately after the gate oxidation, a layerof 2500 ds , phosphorusdoped polysilicon was deposited using LPCVD. After the gatedefinition, which will be described in more detail in next section,the n+ sourcddrain regionswere implanted (As, x lOI5 ern-', SOKcV) with 8 inclination to avoid asymmetric devicecharacteristics [2.2]. Then, a layer of 3OOO undo@ LTO was deposited at 450C anddensified at 900 "C for 20 minutes in dry oxygen. After etching the contact hole, 2500 51


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chap2 -12-

ptmsphorus-cioped polysilicon was deposited at 650"~mi u3ivrted in nitmgcn at 9 0 0 " ~ or15 minutes. This po1ysilicon mcd as 1M e r layer to prevent rhunium from spikingthrough the soumidrain region into the substrate. FinaUy, the conaxing metal (Al with 2%Si)was sputtered and d e W , followed by an et& of the plysilicon outside the amtactuu.

In order to minimize the junction depth, all of b e subsequent thermal cycles after thesource/drain implantation w en limited to 900C or below, and tbe total amount of timerequired by these thermal cycles was less than 60minutes. 'Ihe junctiondepth was determinedto be 0.18p rom spreading resistance technique. The lateral diffusion was estimated to beabout 0.025p.m from SEM pictures.

2.2 Photoresist-ashing techniqueBecause of the limited resolution of conventionaloptical lithography, e-beam dimWrit-

ing and X-ray lithography have been the principal techniques used to fabricate deepsubmicrometer devices [2.3,2.4]. However, both techniques an complicated and expensive. Inaddition, their irnpact on the long-term device reliability as a result of exposing the device tohigh-energy radiation has yet to be fully charaucriztd

In this study, a photoresist-ashing technique has been developed which, when used inconjunction with conventional g-line optical lithography, permits the controlled definition of thegates of deepsubmicrometer devices. Although this ttchnique dots not help to improve tbecircuit layout design rules, it does provide an alternative, economical,and efficient means fordevice-level studies of deepsubmicrometer MOSFETs. When this technique is applied to anexisting p it will improve the circuit performance because of the enhanced devicecurrent drive due to smaller channel length beyond lithography limits. Since most polymer-based resist materials are ashable with oxygen plasma, this photoresist-ashing technique canalso be extended to supplement other lithographic process, such as those of e-beam and X-ray.


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-13-

oxygen plasma

polysilicon

polysiI con


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The basic idea of this photoresist-ashing technique is very Simple as is fig.2.1. First, photo- with near-micron sizc was defined using conventionalopcicrir lithographyand developed (Fig. 2.h). Tbcn the wafers an sompically etched in oxygen plasma at a cali-brated mte until the designated pattern size is achieved (Fig. 2.lb). Since the kft and rightsides of the photoresist arc etched at the same time, the horizontal dimension is etched at twicethe rate of the vertical dimension. Tht photoresist after etching has an ultra-fine pattern butstill with enough thickness to define the polysilicon gates.2.2.1 Wafer preparation

Kodak 820 photoresist was spun at 4600 rpm for 25 seconds and soft-baked for 1 minuteat 100C, resulting in a photoresist thickness of 1.1 pm before etching. Transistors gates withmask-level lengths ranging from 0.5 to 1.6 p, ith 0.1 pm increment., wen defined usingGCA 6200 1OX wafer stepper (g-line, 1 436~11).developed, and hard-baked at 12OoC for15 minutes. Since the resolution of g-line optical lithography is only about l p , the pho-toresist pattern with lengths less than 1p would not have sharp edges under nominalfocus andexposure. To obtain consistent photoresist profiles and step coverage for all mask-level dimen-sions, a focus-exposure test using specially designed test pattern was performed on GCA 6200wafer stepper before the wafers we= exposed. By examining t h a photoresist test patternusing various focusexposun combinations, optimal values were determined. This calibrationprocedure was the most critical step in the process Depending on the condition of the lightsource, the optimal exposure and focus deviated as much asSO%nd %%, respectively, fromtheir nominal values.2.23 Etching process

Although this photoresist ashing process could have been done in any oxygen plasmaetching system, the Technics-C plasma etcher was used in this study because it has been usedin descuming the photoresist in the Micro-Elecuonics Fabrication Laboratory. The optimaletching wndition for this purpose is st i l luntnomhowever, it was found that high conmlla-


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QW.2 -1s-

bility and uniformity could be achieved at an oxygen pnssure of 300 mTorr and an RF powerof SOW. A horizontaletch rate (per &be) of O.O35cLm/min rrnd vertical etch ntt of O.WCl/minunder these etching conditions wen obsewed. The diffehg etch rates wen due to 1 slightanisotropy of th e systan.22.3 Experimental results

Fig. 2.2 shows SEM-measured gate length (LSBM) versus ashing time for four differentThe lateral etching rate was calculated from the slopes ofask-level gate lengths

these lines and the vertical etching rate was calculated h a he photomist thicknesses beforeand after etching using an Alpha-Step profiler. These parallel lines indicate that the etching ratewas relatively constant during the process and is independent of the initial photoresist size andprofile. In preparing these samples, an exposure about 15% under nominal exposure wasdetermined to be the optimal exposure value. This under exposure explains why the pho-toresist lengrh ka s slightly larger than the mask-level length before ashing (ashingtime = 0 min) in Fig. 2.2.

Due to the slow etch rate, this ashing process was easily controlled and reproduced. Theintegrity of the photoresist profile was also preserved throughout the ashing process. Fig. 2.3displays the effective channel length as a W o n f& or two different ashing times.These parallel lines suggest a consistent photoresist profile for all mask-level channel lengthsthat is independent of ashing time, which demonstrates that the correct focus and cxposurtvalues were used. The effective channel lengths,h,ere extracted using a capacitance tech-nique [2.5]. Another independent method to derive Lcff which measures the resistance of thegate polysilicon l i s lso confirms the d t s n Figs. 2.2 and 2.3.


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- 0 2 4 6 8 10 12Ashing Time [min ]Fig. 2.2 SEM measured gate length versus ashing time for various mask-level channel

lengths.1.61.41.2

" II,A

0- 0 .2 .4 .6 J 1 1.2 1.4 1.6 1.8 2Lad-Fig. 2.3 Transistoreffective channel kngth versus mask-level hannel length before andafter the photoresist-ashingprocess.


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Fig. 2 5 SEM picture of the cross-section of a photo~esistine after 8 minutes of ashing.

,

Fig. 2.6 SEM picture of a photoresistcovered ply si lico n line lying over alternated fieldand active regions.


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-21-

Fig. 2.8

mE0r:0vo r (EuoE;

EW0E

bDEar(

10'8

io",

0.0 0.2 0.4 0.6 0.8 1oDepth (pm)

Typical channel doping profile of l i l is p m


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-24-

Fig. 2.10 SEM pi- of a transistorcross Section with 0 . 2 2 ~ffective channel length.The junction depth is 0 . 1 8 ~nd the source/drain lateral diffusion is about0.05Jm


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-25-

15 vt v

03 v0.0 0.6 1.2 1.8 2 4 3.0Drain Current (mA)

(a1

. v,-3v

N-Channd MOSFmW = 2.2 p m=0.ISp mv,-ov

-0.2 0 0.2 0.4 0.6 0.8Gate Voltage (v)

(b)

Fig. 2.11 Characteristics of a transistor with T = 3.6nm andinversion, (b) subthreshold = 0 . 1 5 p . (a) strong-


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Fan-in- 1Fan-out = 17delay = 21 pshtage

Fig. 2.12 Output Waveform of an NMOS 101-stage enhancementldepletion type ringoscillator.


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Qlap.3Chapter 3

-28-

PERFORMANCE AND HOT-ELECTRON RELIABILITYOF DEEP-SUBMICROMETER MOSFETSRecent advances in process tezhnology (3.1-3.7) have made deepsubmimmekr MOS-

FETs potential candidates for next generation ULSI dqsigns. However, the emphases of mostprevious reports have been to demonstrate the feasibility of fabricating these devices with littlediscussion of the physics. It is still unclear whether the basic physics associated with deep-submicrometer devices is the same as that of their longer-channel counterparts. The lack ofphysical understanding is one of the reasons preventing deepsubmicrometer devices frombeing used in current VLSI system designs. One of the goals of this study is to establish animproved understanding of deepsubmicrometer devices and to provide a basis for devicedesign guidelines. Since performance and hot-electron rt l iabi i are the two major concerns indeepsubmicrometer device designs, they arc carefully studied in this chapter. More devicecharacteristics are presented in the next chapter.

The effective channel length, h,s probably the most important parameter among allMOSFE" parameters. Since the device characteristics and even some other device Parameters,.e.g the threshold voltage, are sensitive functions of the channel length, Ld has been com-monly used to identify a technology. In the deepsubmicrometer regime, accurate determina-tion of L d s more crucial, because i n c o w determination of L,.J~may lead to wrong conclu-sion or interpretation of a physical phenomenon such as velocity overshoot. From a circuitdesigner's point of view, using incorrect channel lengths in simulation may cause large errorsbetween simulation results and actual circuit performance. Therefore, the first section of thischapter will be devoted to discussions of the various methods for extracting La in this study.

Another important subject that should be included in deepsubmicrometer study is thesource/drain parasitic resistance Rm effect The voltage drop across Rm effectively reduces


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w . 3 -31-

1500

1200

900600

300

00.0 0.32 0.64 0.96 1.28 1.6Drawn Channel Length (elm)

15v2v2sv3v

0.4 0.44 0.48 0.52 0.56 0.6DrawnChannelLRngth (pm)

(a) Measured channel resistance versus drawn channel length for various gatevoltages, (b) enlarged area near the intersection.


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chap.3 -33-(B) Medified SUC~U'Sethod

Unlike the channel-nsistancemethod, this method is insensitive to the p a d t i c resistanceof individual device, but an I-V model is nquind. The accwacy of this method is affected bythe I-V model used. Since the mobiity model used in the original method proposed by Such(3.101 is too crude to be applied to deepsubmicrometer devices that typically have thin gateoxides, an improved I-V model is used. The basic theory of this modified method is d e s c n ibelow.

The drain current of a MOSFET with R s ~ffect includedcan be expressed as

where

Rs is Le parasitic resistance on the sourcesL. an( -(3.6)

are coefficients of the mobilityreduction due to vertical field. Note that the Ub term in (3.3) is the modified mobility term.The meanings of U, and U, are explained in chapter 5. When V, is small, Eq. 3.3) can besimplified and re-arranged as

V a =-+(Rs* + )Va+. -vab 2Bo Bo Bo (3.7)where VG,= V a V Since (3.7) has the form of "y = a + b x + c x2", the coefficientsR s ~ + u & , nd u b for each device can be extracted by fitting (3.7) through a kast-squafe fitroutine. This fitting procedure is similar to that shown in section 5.4.3. Since is propor-tional to Wd/ La , AL, can be obtained from the x-intercept in the plot of l& versus Ldnm forfixed channel width as shown in Fig. 3.3. Similarly, AW can be obtained from Bo versus


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Qlap.3 -34-W plots, but AW's extracted from this method represtnts m "8vcraged" value that doesmt show ~ r yate-voltage *I&=.obtained by plo#ing RsD+U& VCISUS I& The devi- uscd in Fig. 3.3 o l l ~ dentical

when rll ut ~xtracttd,Rm ud U, an be

those used in Fig. 3.1. TheALb derived from both methods an very similar.

0.0 0.32 0.64 0.96 1.28 1.6Drawn Channel Lcngth (pm)

Fig. 3.3 Reciprocal of the channelconductance versus drawn channel length


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0 . 3 -37-

.

52

39

- 2 6

13

0 0.96 1.28 1.6.0 0.32 0.64Drawn Channel Length

Measwed net channel capacitance versus drawn channel length.

3.2 Short-channel effectThe short-channel effect is one of the major c o ~ mn MOSFET caling, because dev-

ice parameter variations caused by the shortchannel effect poses difficultyin both process con-trol and circuit design. In this section, two most short-channel-sensitive parameters, thresholdvoltage and subthreshold swing, art examined.32.1 Threshold voltage

Threshold voltage shift AV, due to source/drain charge sharing and drain-induced-Wrlowering (DIBL) is the most commonly observed shortchannel effect in MOSFETs and hasbeen widely used as an indicator for measuring the extent of the shortchannel effect for a


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-39-

v .&\ D""Ai""'Xry

OS

long-channel

1....... .....

ov

Eg.3.6 (a) AMOSmcross d o n howiqg the depletion region and the Gaussianbox. The depletion region is assumedto beunifom cross the&d.)Theenergy diagram of the surface potential -the sauccto the drain forboth alongdamel and a short- &vice.


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chap3 -41-

The channel potentials for a long- and a short-channel device for a given gate and drain vol-tages an plotted in Fig. 3.6b. As the channel length is reduced, the minimum channel poten-tial decreases as shown in Fig. 3.6b. when the minimum channel potential is equal to OS, thecorresponding gate voltage, which is de6ned as the hreshold voltage V,(L) can be calculated

where R = V b - 4 ~ . For Vm 51, the second exponential tern in (3.16) can be neglected and (3.16) reduces to aform similar to those given in [3.22,3.23]. For very short channel lengths, the accelerated Vbreduction can be explained by the second exponential tern in (3.16).(B) experimental results

Fig. 3.7 shows threshold voltage versus effcctive channel length at several drain and sub-strate biases. The symbols are measured data and the curves = he model. In general, dev-ices with thicker gate oxide and high substrate bias exhibit more threshold reduction due tolarger characteristic length 1 according to (3.11). The accelerated V, reduction phenomenon atshorter chaMel length can be observed in Fig. 3.8 where AVth is plotted against La in loga-rithmic scale. Note that the measured data deviates from the simple exponential expressionwhen is smallerthan about 51 which translates to AV* = 0 .W. Since most AVb data aretaken around O.lV, this slope-increasing behavior at shorter channel length is important inaccurately modeling V,. Without taking into account this accelerated V, reduction at shorterchannel length, it would lead to an underestimation of the shonchannel effect or result inincorrect extraction of 1 .


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42-

05

0.0 0.0 .A 13 1s ' uEllcctive Channel Length Qm)

Fig. 3.7 'Ihreshdd vdtalge versus dTective channel length ab various drain mdsubstradebiases for scpefal techndogies. The symbols are measured data and the mcsarcthemodel.


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chap3 45 -The same approach can also be applied to LDD structures, but the boundary COndi t iOI l s

should be modified to be suitable for the n-4 junctions. Since the built-in potendal of an n-hjunction is smaller than that of an n'h, LDD devices generally show less V shWt than m-LDD devices. The voltage dropacmtk n region also decreases th effective drain voltageapplied to the channel and reduces the DIBL e m

Kg. 3 9 Measured cbara%edstic length versus depletion layer thichess for &exeattechnologies.


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47-

Hg. .11

"1 V,=O.lV1s

rn110

100

90

8m

m

-6-vm = 3v

Subthreshold swing versus effective channel length for four oxi& thiclmessts.(a) V -O.lV, (b) Vm - 3V.


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0 . 3 4 8 -32.2 Subthreshold swing

The ncrease of subthnshold swing, S,at shorter channel lengths I3.301 is another factorcausing shortJlanne1 devices to be more difficult to turn off. Therefore, the subtluesbldswing also serves as an altcmative way to monitor the extent of short-channcl effects. 'Ibesubthreshold swing versus for this process at a low and I igh drain voltage ut shown inFig. 3.11a and 3.llb, nspectively. Unlike the threshold voltage, s u m l d wing is fairlyconstant even when AV,,,starts to show up, but suddeply increases to a large value when thedevice is near punchthrough. Also, the s u m l d wing is less sensitive to the drain voltagethan V, Theoretical value of the subthreshold swing is given by

[3.17]

where CD is the depletion-layer capacitance. The subthreshold swing decreases as the gateoxide thickness is reduced as predicted by (3.17). For thin gate oxides, higher channel dopingconcentrations are required to maintain a 0.65V threshold voltage which also inclrcases C,This explain why the longchannel subthreshold swings for 3.6nm and 5.6m gate oxide dev-ices are very close.

3.3 Current driving capabilityThe improved current drive of short channel devices is one of the motivations for MOS-

FET scaling. Because of the d e r elocity saturation effect, draii saturation current increasesonly s u b l i i l y with l / r , in the submicrometer regime but the design and fabrication over-heads increase drastically with d u c i n g the channel length. Therefore, a quantitative study ofthe current driving capability of deepsubmicrometer devices is another important procedure inoptimal device designs. When the channel length is smaller than 0 . 2 ~nd the power supplyis not proportionally scaled (3V or higher), the velocity saturation region extends into a substantialfraction of the channel and a considerable portion of electrons in the velocity saturation


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chap.3 4%q i o n move with a velocity higher than the SatuzBtion velocity Y It was claimed that thecurrent driving capability of deepsubmicrometer devices would be enhanced by this velocity-overshoot effect [3.31,3.32]. A straight forward way to examine whether the current drivingcapability of deepsubmicromem devices is enhanced or affected by new carrier transportmechanisms is to compare experimental data with existing physical models. Tbc drain cwmtmodel used here was developed by KO 3.33], improved by Toh [3.34], and has been success-futly applied to devices with channel length longer than 1p.m. Some of the model equationsare listed below.

(3.18)and

where g is the saturation transconductance,

2v,E,=-and& is the effective vertical field in the channel that can be approximated by

(3.19)

(3.20)

(3.21)

(3.23)

QB s the depletion bulk charge, I& = 0.67MV/an, n = 1.6, p, = 670cm2/V stc, and v, =8~lO'~cm/sec.The measured drain saturation current INAT,saturation transconductance g and the

model for an array of devices with channel length down to 0 . 1 S p are shown in Fig. 3.12.


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The same model parameters wen used for all device dimensions and oxide thicknesses. Thesymbols n Fig. 3.12 are measured data and the solid curves arc themodel. The data shown mFig. 3.12 have been comcted br the sourWdrain parasitic &stance (=uM/side). Acomprehensive study of the souWdrain parasitic resistance effect on device performance isgiven in the next section. The nversion-layer capacitanceeffect [3.35],which is mon impor-tant for thin-oxide devices at low gate bias, was also not included in these equations.

The well-behaved trends of and and.- good agreement between measureddata and the model indicate that the basic physics of deepsubmicrometer devices is rather wellundemood. Although Monte Carlo simulations show the existenceof velocity overshoot in thevelocity saturation region, it has little effect on the MOSFET current driving capability, at leastdown to 0 . 1 5 ~ - .el length. This observation also coincides with the conclusion of anotherindependent study L3.363, which used an improved mobility model (extended driftdiffusionmodel) to simulate the velocity overshoot effect in the velocity saturation region. According totheir simulations, the velocity overshoot effect is of little importance to the MOSFET curcntdriving capability for devices with channel length longer than 0 . 0 6 ~ .

Since the basic physics in deep-submicmmeter devices is essentially unchanged, the basicframework of most existing drain current models can be kept without major modifications.The drain current model used in this section, while simplistic in formulation, still providesgood physical as well as quantitative understanding of the current performance of MOS devictsdown to the deepsubmicrometer regime and can serve as a means for process conml anddiagnosis.


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-5 1-

0 .1 9 3 .4 .S .6 .7 d J 1 1.1 1 1 13 1.4Effective Channel Length1pm-1

Fig. 3.12 (a) Measured drain d o n urrtnt d Va-V, versus effective c h dlength for v ~ o u sxide thicknesses, (b) meawed transcoaductance v ~ f l ueffective channel length. 'Ihe data have been corre&xi, to the first orda, orthe pamitic I l s h m c e&at


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3.4 Sourcddrain parasitic resistance effect32-

lhe parasitic sourcddrain resistance is one of the device parameters mat can not be pro-portionally scaled. As MOSFET channel lengrhs are scaled down to the deepsubmicrometcrregime, device performance reduction due to parasitic source/drain resistance (RJ bccomts animportant factor to consider in MOSFET scaling r3.37-3.401. A quantitative study of &effects is essential, since it can provide guidelines for both MOSFJT scaling and contact tech-nology development.

It was claimed that as the device channel length is scaled below 0.5 pm, the cumnt driveand transconductance starts to decrease rather than increase with the reduction of the channellength [3.38] implying that the parasitic resistance poses a limit on MOSFET scalability. Butthis statement has been shown to be incornct because of the recent improvements in devicetechnology. Previous reports [3.37-3.391on this subject, based on near-micron technologies,also may not be applicable to the deepsubmicrometer regime. More mently, Ng and Lynch[3.40], using computer simulations, studied the R,,, effects in the deepsubmicrometer regimebut with only little experimental results. In this section, experimental studies of the R,,, effectson deepsubmicrometer n-channel non-LDD MOSFETs is presented. Thc reduction in draincurrents and ring oscillator speed for various channel lengths and & values is examined. n#effect of salicide technologies on device performance is also discussed and projections of theultimate achievable device performance are givm3.4.1 Experimental procedure

Intrinsic Device Performance Measurement Procedure: In order to determine theamount of performance reduction due to b*he following calibration procedure was per-formed. me drain cuknt in tht linear ID^) and saturation (IDSAT) regions and the maximumsaturation transconductance @J were measured. In Fig. 3.13the measured I ~ Ts plottedagainst RSD; different RSD values were achieved by attaching external resistors (%3, equdy


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chap.3 -53-divided between the source and drain, to tach device, Le. Rm = Rsw +&. The circles indi-cate meaSund data. Tbc solid lines represent the simple physical drain current modcldescribed in section 3.3. A calibration constant (in the range between 1.0 to 1.1 for all dev-ices) is multiplied to themodel to best fit the measured data for each channel length. To obtainhigher accuracy, parasitic resistance effects were included in the drain current model throughiteration; parasitic resistance-induced body effect, which was neglected in (3.401, was alsoincluded in the calculation. The theoretical drain c u n y t s at RSD = 0 are taken as the inuinsiccurrent ( ID,^ and I ~ A T ~. The percent drain c u m t reduction from the intrinsic value as afunction of RSD is given by the alternated curves.3.4.2 Experimental results

(A) Saturation region: Fig. 3.14 shows IDSAT versus & or a power supply of 3.3V.The symbols indicate measured data; the curves are the calculated intrinsic (RSD= 0) draincurrent obtained in the manner shown in Fig. 3.13and the corresponding current derating,Idu,/Iw Because of the slightly different parasitic resistance between wafers, RSD valueswere adjusted to be about 600Rpm for all oxide thickmsses using external resistors. Similarresults were also obtained for the transconductance We observed that the current (transcon-ductance) derating decreases as La and/or T, decreases because the debiasing (source fol-lower) effect of RSD is stronger as IDS (gJ increases. However, the derating is st i l l about87% even at & = 0.2pm, if & s kept at 6OORpn.

(B) Linear region: Fig. 3.15shows IDm ersus Ld t VDS= 0.1V and VGS= 3.3V.The drain current derating in the linear region is significantly lower than that in the saturationregion. The derating can be as low as 50% at L& = 0 . 2 ~ . his is because in the linearregion& reduces the current through both the effective VG s and V while in the saturationregion it only reduces the current through the effective V Also, the current derating is lesssensitive to TOxhan in the saturation region. This is because IDm s less sensitive to T, dueto the transverse-field-induced mobility reduction than IDSAT, which is mainly determined by


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h q 3 . 3

d e r aturation velocity that is insensitive to the transverse field.

800

c*z 200Ei

0

TOx= 8.6nm Leff= 0.3pm .,.

-54-

0.0 1Ooo.o 2000.0 3000.0 4OOO.OParasitic resistance (Rpm)

Fig. 3.13 Drain saturation current versus parasitic resistance. The circles axeddata and the sdid m e re the results of the calibrated model. Ihe dashedh e s ndicate the percentage drain curreat reduction.


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-5s-

Fig. 3.14(a)

1200

lo00

800

600

400

200

0

Tox5.6nm8.6nm15.6nm

Data Model0 .........

vcs = 3.3v VDS = 3.3vI I I I I I

0.0 0.2 0.4 0.6 0.8 1 o 1.2 1.4Effective channel length (pm)

Drain saturation ament and the &rating versus dective channel leagth. 'Ihesymbols are measured drain CuITent and the curves 81t thek correspondingintrinsic values mdd e d n g s .


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\\ A Tox= 15.6~1

I I a I I 1 I 1 I 8 I I I0.0 0.2 0.4 0.6 0.8 1o 1.2 1.4Effective channel length (pm)

Fig. 3.14(b) Saturation transconductEnccand the derating versus effective channd length.'Ihe symbols an -dataandthe cwves are their corresponding inlxjnsic


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-57-

200

150

100

50

0

Tox5.6m8 . 6 ~ 115.6nm

Data00A

m 8 I 1 m0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Effective channel length (pm)

Fig. 3.15 Linear region drab curzent and the derading vems effective channel length.intrinsicIhe symbols are measured data d t h e cwes are their c o m q o d qvalues and derapings.


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-59-

wN 15pmOx= 8.6nrn --C, = 0.1pF Wp - 30pm

1 Opm

0.7pm

0.0 1000.0 2000.0 3000.0 4000.0 5000.0Parasitic resistance (Qpm)

Fig. 3.16 SPICE s b l a t d d riag oscillator delay timc versus parasitic resistance forseveaal channel l


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Fig. 3.17 A schematic diagran showing the various components of the parasitic nsis-tmce.100

#)

8Me-u r n-B

m

a 40.0 100.0 m.0 #w10 400.0 m.0 600.0 R (Rpm)+ non-sallcided non-LDD+

+ alicldednon-LDD -w+ on-sallcided LDD++ alclded LDD+Fig. 3.18 Deraeing versus parasitic nxistance.The projected parasitic resistanceeffect 00vadous ~ O g i e sreiodicatbd


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chaP.33.5 Hot-electron effects

-61-

It is well known that the h o t c l m n induced device degradation poses Circuit dhbilityproblems. Therefore, device degradation is the most discussed topic among all hot-clcctmeffects. Because of the extremely high electric 6led in the channel due to the unscaled powersupply, hotelectron effects arc more severe in deepsubmicrometer devices and have gainedmore attention than ever in MOS scaling. In this section, the substrate m n t nd the devicelifetime are discussed.35.1 Substrate current

When camers pass through the velocity saturation region, electron-hole pairs are gen-erated by impact ionization. The holes are collected by the substrate and constitutes the sub-strate current Ism. Since many hot-electron phenomena, including device degradation, haveclose comlations with Ism, the substrate current is widely used to monitor the hot-electroneffects. In Section 3.3, we have shown that the basic physics of deepsubmicrometer devices isunchanged. In this section, this statement w i l l be demonstrated again fn#n the hot-electronpoint of view. A commonly used substrate current model (3.421 in the literature is used forthis purpose. The model equations are summarized below.

where

(3.24)

o+ and pi are impact ionization coefficients whose typical values are 2E6cm-l and 1.7E7V/cm,respectively (1E7cm-' and 3.7E6V/cm for PMOS). For long channel and thickgate oxide dev-ices, an empirical expression for 1 has beenobserved l3.43.3.441.

I =o.22T2xjlJ3 (3.26)


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0 . 3 -62-

1oms 1 o . 1.510-81

0 Effective Channel'kngth c~m 1.

Fig. 3.19 Peak substrate current veasus effective c h d ength rt V - 3V for fouroxide thiclmesses.


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n . . . .0 1 2 3 ' 4 S 6 . 7

Fq. 20 Substrade m n t charaderistics for different c W engths. As &e c h dlength decreases, he gate voltagemtrolwed the substrate ament reduces.


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chap.3

Gate3elocity -Saturated DrainRegion

Short ChannelThin OxideQn hallow JunctionLong ChannelQ, Thick Oxideeep Junction

YE

I

/ c-- E, = E d + AE

1LD Effective Non-Overlap Length

Effective Lateral Electric Field Length

Rg. 321 Schematic diagram showiag thc cuaeat-cmding bdxxd weak gade contrdeffect 13.481. (a) cross section of a MOS transistor, @) mobile charge densityas a functionof the channd position, (c) the e l e d c fidd 85 a fuoctim of thechannd positioa


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when Taaand Xj arc in centimeters.The peak substrate c u m ersus effective channel length at V B = 3V for severaloxide

thicknesses is shown in Fig. 3.19. 'Ihe substrate cuncnt peak is higher for a device withshorter channel length and thinner gate oxide as predicted by (3.24H3.26). Fig. 3.20 showsIm - VG S characteristics for T,, = 8.6nm at various channel lengths. At longer channellengths > I.-), the shape of the Ism characteristicscan be modeled. However, as thechannel length is reduced, the substrate current becomes less sensitive to the gate voltage thatcan not be explained by the model

Several modifications [3.45-3.47)o the Ism model have been proposed to describe thedeviation of measured Ism from the simple theory. These modifications are usually imple-mented by making the impact ionization coefficients functions of applied voltages throughsome empirical expressions. The physical basis for them is the non-local impact ionizationeffect and the non-equilibrium conditions in the high-field region near the drain.

Another proposal is the s o d e d "cunent-cmwding induced weak gate control" 13.48)which can be schematically explained in Fig. 3.21,where the cross section and the dopingprofile of the drain of a MOSFET are shown. When the drain current is small,as in long andthick gate oxide devices, the mobile charge density required to cany the drain current in thevelocity saturation region is negligible compared to the drain doping concentration. Therefore,the boundary of the velocity saturation region is very close to the edge of the drain junctionThe peak channel elecuic field is inside the velocity saturation region and can be approximatedby (3.24). For shortchannel and thin gate oxide devices, the drain current is large and themobile charge density in the velocity saturation region is comparable to the doping concentra-tion of the drain region. Therefore, the velocity saturation region extends into the drain andthe peak channel electric field also occurs inside the drain. As a result of the extra depletionregion in the drain, the peak electric field is higher than that given in (3.24)by AE.

LD qlDSAE=-(--ND)~d Xjvm (3.27)


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Qlap.3 -66-

where ND s the average drain doping concentratiai, is the length of the weak gate-controued ngion. The magnihde of Lo d e w n the drain struchm, usually in the range of0 - 10nm. Detailed description of h i s cumntcrowding induced weak gatecontrol cau befound in r3.48).

More informative figurcs of 1s- an SV$IM vcrsus l / ( V B - V m T ) plots as shown inFig. 3.22. The straight lines in Fig. 322 suggests that the basic physical mechanism for'hot-electron effects still pnvail in deepsubmicrometer devices. According to the hot-eltctronmodel, the slopes of the lines (= I) in Fig. 3.22 an independent of the channel length andhave a one-third power dependence on gate oxide thickness. However, it is found that whenthe effective channel length is smaller than about 0.5p. he slope (1) decreases with La seeFig.3.22a). We suspect this channel length dependence of 1 have to do with the encroachmentof the linear region into the velocity saturation region as tht channel length decnascs. It isalso found that, when the gate oxide thickness is smaller than about l S m , 1 is very weaklydependent on T (see Fig. 3.22b). One explanation to this weak gate oxide dependence of I isthe finite depth of the current path in the velocity saturation region. In deriving (3.21)-(3.23),it is assumed that the impact ionization occurs at the Si-Si02 interface. In the velocity satura-tion region, the actual drain current path, and thereby the peak impact ionization, is at aboutIO-3Onm below the interface. Therefore, an effective gate oxide thickness Tk. which consistsof T and the cunent depth should be used in (3.23). When the gate oxide thickness is com-parable to or smaller than the cumnt deph, Tk s limited by the current depth and I becomesa weaker function of T An empirical e x p s i o n for 1 is determinedto be

I =1.7~10- m m m, Xj for Ldf i


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-67-

Fig. 322(a) log(lsv$r,) versus lWm--VmT) plots for & - 03pm and four oxidethicknesses. 'Ihe slopes of these lines are ploportional to the impad ionizationcoefficient.


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-68-

-2.0

n.IL5- -3.0cnm>" 4.0In>een-ij -5.0CI\aav)cb 4.00LIdLI

-7.0

ToX BSA

Fq. 2 ( b ) log(Isu$lrs) vusus w m V ~ T )lots forT = 8511mand several channdlengths. "he slopes of these lints arc pmpoxtiond to the ;mpact ionizationCotffiCialL


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Qlap-3 -69-

35.2 Device lifetimeA detrimental effect of the high channel elcuric deld is tk injection of cneqctic elec-

trons into the Si-Si% interface that generates interface traps and results in device degradation[3.49,350]. How to reduce hot-electron device degradation has been the goal of many hot-electron studies. A common quantity to measure the immunity of a device to the hotclectmneffect is the device lifetime, which is usually defined as 3% (sometimes 10%) forward draincurrent change in the linear region afkr hot-elecuon stress t3.421. Previous studies on near-micron devices showed that the device degradation is technology dependent and is relativelyindependent of the channel length under the same stress conditions (3.511. However, in thesubmicrometer regime, the effect of device degradation on the device performance is moreprominent as indicated by the strong channel-length-dependentdevice lifetime shown in Fig.3.23 t3.521. Similar results are also observed for other oxide thicknesses. This channel lengthdependence of lifetime can be qualitatively explained in Fig. 3.24. If we assume that the hot-electron created damage (the dark region) is independent of the channel length for the sameamount of stress ( I ~ B time = constant), then the ratio of the damaged interface area to thetotal channel area increases as the channel length is reduced and the device lifetime decreasesbecause the relative amount of degradation increases.

.

A useful variation of Fig. 3.24 which provides direct device design guidelines is shownin Fig. 3.25, where the extrapolated maximum supply voltage to ensure a 10-year device life-time for 8.6nm gate oxide is plotted against the channel length. As a result of shorter life-times, the maximum supply voltage is smaller for short channel devices. For a quarter-microndevice with 8.6m gate oxide, the maximum supply voltage is about 2.5V, suggesting thatsome kind of hot-elecmn-resistant structures arc still needed even if the power supply islowered to 3.3V.


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-71-

Substrate

Long Channel

Substrate

Short Channel


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-n-

s.5

3

2 5

, I - - - - ' - - - - ' - - - - ' - - - -- 0 .5 1 15 2Effective Channel Length [Ccm 1

Maximum supply voltage to ensun a 10-year device lifetime vemu effectivechannel length for 8.6nm gate oxide. "he devioe lifetimeis defined s % ftmward drainaurrnt degraaatioain the linearregioa


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-3 -73-3.6 References

W. Fichtncr, RK Watts, D.B. Fraser, R L ohnston, and S.M.Sze, "0.15 pan--Length MOSFEI'S Fabricated UsingE B C ~sthography," IEDM Tcch Dig.,~p.272-725, 1982.W. Fichtncr, EN. PI&, R.L. Johnston, RK. Watts, and W.W.Wcick, "OptimizedMOSFETs with Subquartexmicron Channel &@E," EDM Tech. Dig., pp.384-387,1983.T. Kobayashi, S. Horiguchi, and K. Kiuchi, "DeepSubmicron MOSFET Characteris-tics with 5nm Gate Oxide," IEDM Tech Dig., pp.414417, 1984.S.Horiguchi, T. Kobayashi, M. Oda, and K. Kiuchi, "Extremely High Transconduc-tance (Above SOOmS/mm) MOSFET with 2 . 5 ~ 1 ate Oxide," IEDM tech Dig.,pp.761-763, 1985.S.Y.Chou, H.I. Smith, nd D.A. Antoniadis, "SublOo-nm Channel-LengthTransistorsFabricated Using X-Ray Lithography," J. of Vacuum Science Tech. B, vol. 4, m. 1,pp.253-255, Jan/Feb 1986.J. Chung, M.-C. Jeng, J.E.Moon, A.T. Wu, T.Y.Chan, P.K. KO, nd C. Hu, "DeepSubmicrometerMOS Devict Fabrication Using a Photoresist-Ashing Technique," IEEEElectron Device Letters,vol. 9, no. 4, pp.186-188, April, 1988.G.A. Sai-Halasz, M.R.Wordeman, D.P. Kern,E.Ganin, S.Rishton, D.S.Zicherman,H. Schmid, M.R. Pol&, H.Y. Ng, P.J. Restte, T.H.P. Chang, and R.H. Dennard,"Design and Experimental Technology for 0.1 pm Gate-Length Low-TemperatureOperationFET's," IEEE Electron Device Lettcrs, voL EDL-8, no. 10,W,987.K. Terada and H. Muta, "A New Method to Determine Effective MOSFET channelLength," Japanese J. Applied Phys., vol. 18,no. 5, pp.953-959, May, 1979.J.G.J. Chem, P. Vhang, RE M o a and N. Godinho, "A New Method to Detemim


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(3.111 K L Peng and M.A. Afromowitz, "An mprovedMethod to DetermineMOSFET Chan-nel Length," IEEEElectron Device Letters, vot' -3, no. 12, p.360, Dec., 1982.

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(3.131 J. Whitfield, "A Modification on *An Improved Method to Determine MOSFEI' Chan-nel Length'," IEEE Electron Device Letters,vol. EDL-6, no. 3, p.109, March,1985.

(3.14) M.J.Thoma and CR. Wcstgate, "A New AC Measurement Technique to AccuratelyDetermine MOSFET Constants," IEEE Tran. on Electron Devices, vol. ED-31, no. 9,p.1113, Sep., 1984.

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p-channclMOS devices for VLSI," Solid-state Elearon, voL 26, m. 10, p. 969,1983.(3.401 KK Ng and W.T. Lynch, Th e impact of intrinsic series mistance on MOSF'ET scal-

ing," IEEET m on Electron Device,vol ED-34,m. 3, p. 503,1987.(3.411 K.Mayaram, J. Lee, and C. Hu, A model for the electric field in lightly doped drain

structures," IEEE Tran. on ElectronDevices, ED-34, oL 7 , p. 1509,1987(3.421 C. Hu, S. Tam, E-C. Hsu, P.K. KO, T.Y. Chan, and K.W. T e d , "Hot-Electron-

Induced MOSFET Degradation - Model, Monitor, and Improvement," IEEE Tran. onElectron Devices, voL ED-32, p.375, Feb. 1985.

[3.43] T.Y. Chan, Electron Device Letters,vol. EDL-6, p.551, Oct 1985.[3.44] M. akumu, IEDM Tech Digs., p.399, 1986.[3.45] C.G. Hwang, R W . Dutton, J.M. Higman, and K.H a s , "Accurate Modeling of Impact

Ionization Effect in Submicron MOSFET," IEEETran. on Electron Devices, vol. ED-34,no. 11, p.2385, Nov. 1987.

[3.46] B. Meinenhagen and W L . En@, "The Influence of the Thermal Equilibrium Approxi-mation on the Accuracy of Classical Two-Dimensional Numerical Modeling of SiliconSubmicrometer MOS Transistors," IEEE Tran. on Electron Devices, vol ED-35, no. 5,pp.689-697, May 1988.

[3.47] M. Tomizawa, K. Yokoyama, and A. Yoshii, "Nonstationary Carrier Dynamics inQuarter-Micron Si MOSFET's," IEEE Tran on Computer-Aided Design, vol. CAD-7,no. 2, pp.254-258, 1988.

(3.481 J. Chung, M.-C. Jeng, G. May, P.K.KO, nd C.Hu, "Hot-Electron Currents in DeepSubmicrometer MOSFETs,"IEDM Tech Digs., p.200, 1988.

(3.491 F.C.Hsu and S.Tam, "Relationshipbetween MOSFET Degradation and Hot-ElccmnInduced Interface-State Generation," IEEE Electron Device Letters, vol. EDL-5, 50,1984.


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-3 -78-[3.50] H.Gesch, LP. eburton, and G.E. Dwda. Generationof Interface States by Hot Hole

Injection in MOSFET's," lEEE Tran. an Elecaon Devices, v d 29, noJ, p.913,May 1982.

[3.51] T.Y. Chan,P.K. KO, nd C. Hu, A Simple Method to Qlaracteriz Substrate Cumntin MOSFET's," IEEE E l m n Device Leaem, voL EDGS, no. 12, pJOS, 1984.

13.521 M.-C. eng, J. Chug, AT. Wu, T.Y.Chan, J. Moon, G. May, P.K. KO, nd C Hu,"Performance and Hot-Electron Reliabilityof I)eep-SubmicrometcrMOSFEI"L"IEDMTech Digs., p.710, 1987.


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Chaps4 -79-

Chapter 4DEEP-SUBMICROMETER MOSFET DESIGN

Although deepsubmicrometer MOSFFTs with excellent characteristics have been demon-strated and the basic device physics of these devices has been shown to be essentiallyunchanged, deepsubmicrometer devices arc stin restricted to device level studies because nodesign guidelines are available. For longerchannel devices, previous studies [4.14.3] haveproposed design guidelines based mainly on the threshold voltage shift due to short-channeleffects, subthreshold cumnt, and hotelectron reliability considerations, but the different trade-offs between reducing oxide thickness, channel length, and power supply are still not clear.This chapter attempts to provide comprehensive design guidelines for MOSFETs in the deepsubmicrometer regime by investigating a wide range of performance and reliability constraintson device dimensions and power supply. The mechanisms examincd in this study are: short-channel and drain-induced-banier-lowering (DIBL) effects, the punchthrough and gate-induceddrain leakage (GIDL) [4.44.6] currents, hotelectron reliability, timedependent dielectric +breakdown P D B ) [4.74.9], currentdriving capability, voltage gain, and switching speed.Using this set of performance and reliability constraints, design curyes are developed based onmeasurements of n-channel non-LDD deepsubmicrometer devices. The relative importance ofeach mechanism for a given technology and design criteria is compared. The five basic param-eters in MOS scaling are: effective channel length La, xide thickness T power supply VDD,junction depth X3 and channel doping concentration N m . For most technologies, Xj is rela-tively constant compared to other parameters. Once Tm and the threshold voltage is deter-mined, Nsm is fixed. Therefore, onlyb, and VD Dare considered in this study. Xj isfixed to about 0.18p.m and Nsms arc adjusted such that the long-channel threshold voltagesfor all oxide thicknesses are around 0.65V. The design considerations included are dividedinto two categories. One sets device limitations and the other sets performance constraints.


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4.1 Device limitations4.1.1 Threshold voltage

Fig. 4.la and 4.lb show the threshold voltage shift due to shon-channel and DJBLeffects. As mentioned in Section 3.2 that thcse two effects a ssentially om, hey arcseparated here for easy description. In Fig. 4.lb, only T = 8.6nm data are shown.Similatresults are also observed for other oxide t h i c h ~ . he threshold voltage shift AV,,, isdefined as the difference between the measured threshold voltage at a given drain voltage and. its corresponding lon-channel value(Vd t a drain voltage of 5OmV. Although the thresholdvoltage model derived in section 3.2 showed that AV& deviates from a simple exponentialexpression for AVh > O.lV, straight Iines are drawn to fit measured data for simplicity. Thedashed lines in Fig. 4.14.8 demarcates the performance and reliability criteria (Table 4.1) usedin this study to obtain the design curyes (Fig. 4.9-4.11); the arrows indicate the acceptableregions. As an example, for T = 8 . 6 ~ 1nd VDD= 3V, he minimum allowable Lctrin thecircuit is a b u t 0 . 2 8 ~urely based on thc threshold voltage shift consideration.4.1.2 Off-state leakage current

The off-state leakage current is also sensitive to the short-channel effects and was used asone of the criteria for MOSFE" miniatuxization [42]. As shown in the insert of Fig. 4.2%off-state eakage current is composed of two main components: punchthrough current (In)ndgate-induced drain leakage currentw. hc punchthrough current is the leakage c u m tbetween the source and the drain. The gate-induced drain leakage current is the drain-to-substrate leakage due to band-to-band tunneling between n+ and p regions. I n increases withdecreasing channel length because of the threshold voltage reduction and the increase insubthreshold swing. kIDLs, however, independent of Ld and is determined by T and thepower supply used. In Rg. 4.2, the off-state leakage currents were measured at Vw - 0.6Vfor all device dimensions and drain voltages. A gate voltage of Vm 0.6V was used to e h -


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m . 4 -81-

inate any effect caused by tbc variations m threshold voltage between different gate oxidethiciaesses. The punchduough m n t dominated regions arc indicated by open symbols; tbcGIDL current dominated regions an indicated by closed symbols. The m n t cvcl of theexperimental data is clamped at a lower bound of O.SpA/pm due t~ limits in the measurementresolution.

1.00 '

s9 0.10t,a

0.01

o To,=3.6nmA To,=5.6nmo Tox=8.6nm0 Tox=15.6nm. . . 4

EXP(-L I

0.J 0.6.3 0.4.0 0.1 0.2Effective Channel Length urn)

AVT S 0.1V

Fig. 4.l(a) Threshold vdtage rechction (AVd versus effedve chaolnel length cd Vm - 3Vfor fau oxi& thicknesses.


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Chap-4 -82-

I 0 . N

Fig. 4.l(b) 'Ihreshdd voltage reduction (AVd VQSUS effective c h a a n d length for T =8.6nm at differeat drain voltages.


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-83-

-4

-5nE -6rl.4\- 7EQ) -8LLhc)

$ -9Ea d2 -102 11QWn

-12

-13

VDS = 3v- - -Q

VGS = ov

ha

0 T0,=3.6nmA To,=5.6nmo T0,=8.6nm

. V . 1 1 40.0 0.1 0.2 0.3 0.4 0.5 0.6Effective Channel Length (pm)Eg. 2(a) 0E-stat.e leakage current versus effective channel l q t h m d t V - 3V

for four oxide thicknesses. "he off-state eakage ament has two companeats:p c h t h m g h ament and gateinduced drain leakage ament. 'Ihe showsthe diEerent paths for these two mpamts .


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-84-

-3 --4n#- 6 .

hYg -7 9&Lu' - 8 -2nE -9I- 10bD0-

- I t

-I2

= - - -

3v2v1v

0.osv

9 Tbx = 8.6nm

-1 3 4 J0.0 0.1 0.2 0.3 0.4 0.5 0.6Effective Channel Length (pm)


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Chap.4 -85-4.l3 Hot-electron reliability

Recent studies showed that digital circuits axe fairly robust to bot-elccmn effects (4.101.Therefore, the definition of device lifetime in section 35.1 (3% drain current change in thelinear region) is very tight for most applications. In this chapter, a more relaxed definition.1096 drain current reduction in the linearregion, s used for device lifetime. Fig. 4.3 displaysthe extrapolated maximum allowable power supply voltage to ensun a 10-yeardevice lifetime(4.11 as a function of channel length for four oxide thicknesses. For a given substrate currmt,thinner oxide devices exhibit less degradation than those with thicker oxides (4.121.However,for a given drain bias, thinner gate oxide devices also exhibit greater peak substrate currentthan those with thicker oxides (see Fig. 3.18). These two counteracting trends explain why8 . 6 ~ate oxide devices show a slightly smaller minimum channel length than those of 5.6nmand 15.6nm gate oxides devices at a power supply of 3V. According to Fig. 4.3,at a powersupply of 3.3V and with effective channel length larger than 0 . 5 p , LDDmay not be needed.4.1.4 Breakdown voltage

Fig. 4.4 shows breakdown voltage versus effective channel length for different oxidethicknesses. The breakdown voltage is defined as the minimum voltage of the c-shaped break-down curve shown in the insert. Comparing Fig. 4.3 and Hg. .4, t is found that the break-down voltage is about 1V to 2V higher than themaximum allowable power supply set by hot-electron requirements. Although under normal operations the breakdown w i l l not be a limitingmechanism in MOS scaling, it sets an upper bound to the burn-in voltage.4.1.5 Tim-dependent dielectric breakdown

Based on a defect-density model, a technique to predict oxide breakdown statistics hasbeen developed [4.9]. Plotted in Fig. 4.5 is the maximum allowable supply voltage to ensure10-year lifetime at 12?C versus oxide thickness for two defea densities. Because oxide qual-ity is a sensitive function of the device fabrication process, the oxide reliability results used inthis study should be viewed as a rough approximationonly. Other fabrication technologk~ an


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Clbap.4 -86-

2.6 -2.4 -

yield a higher quality oxide with a lower defmdcnsity than is observed in this study (1.0an-2). Listed in Table 1 is the oxide niiabii criterion used in Fig. 4.9411.

Fig. 4 3 Maximum allowable power supply to CDSUIC lo-year device lifetime &e tohrrt-$ectron &e& vefsus &edive Cbannd length for severat oxidebrichesses.Ihe device ifetime is &fined as 10% fornard drain aurent dtgra-dation in the linear region. 'The dashed line indicates the criterion used to&tainedthedesignawes.


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390aBreakdown Voltage (V)

cUmcWU ..,

40

O O D O


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-88-

6 -5 -4 -

3 -

2 -I,

.mm

..m

mm

m.

1O y e a r l i

Defe ct density:

Y v .5cmo21 ' t t I I t 8 I I I t t I 8 . I 8 t0 5 10 15 20Oxide Thickness (nm)Fig. 4 5 Ibhimum allowable power supply to ensure lO-year &vice lifetime due tot i m e d e p h t die ledc hreak&wn vezsus oxide thickness for two Meetdep

sitits.


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m . 4

4.2 Performance constraints-89-

43.1 Currentdriving capability:Fig. 4.6 shows drain saturation m n t ~ Tersus effective channel length. 'ihe drain

saturation current is measured at V a = 3V and V = 3V as shown in tbe insat Asexpected, the currentdriving capability for a given gate oxide increases as the channcl lcaglhdecreases. However, because of mobility degradation due to high vertical fields, tfie cuTrcIlt-driving capability tends to saturate at very thin gate oxides unless the channel length is verysmall such that all carriers in the channel arc moving with the saturation velocity. The highchannel doping concentration required to achieve the required threshold voltage for thin oxidedevices also degrades camer mobility. The sharp increase in I ~ A Tt very shortchannellengths is mainly caused by the threshold voltage reduction due to short-channeleffects.43.2 Voltage gain

In Fig. 4.7, the peak voltage gain (solid lines) measured near V m = OV and the gain(alternated lines) measured at V a VT = 0.3V,where most analog circuits arc biased, arc plot-ted for various device dimensions. The voltage gain is defined as &&, when g, is themeasured transconductance and is the output resistance. Since both g, nd& re higherfor thinner gate oxide devices, the voltage gain increases as oxide thickness decreases. Thesharp decrease of the gain at very short channel lengths is caused by bulk punchthrough whichsignificantly reducesL.4 3 3 Switching speed

Because no CMOS circuits were available, the switching speed studies were achievedthrough simulations on CMOS ring oscillator delay time. To ensure high confidence, a MOS-FET model accurate down to quarter-micron channel length was used in the simulation. Thismodel is described in chapter 5. ng. .8 shows SPICE simulated delay time of an ll-stageCMOS ring oscillator with a 0.lpF load capacitor on each stage for different oxide thicknesses,


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chaps4 -90-channel lengths, and power supplies. The channelwidm is 1 5 p fop n-channeland 3Opn forpchannel devices. The overlap between the gate and mt sourct (drain) is 0 . 0 5 ~ . s oxidethickness decreases, the gate capacitance eventually becomes larger than the load capacitance.However, because IDSATtends to saturate at thincr gate oxide (see Fig. 4.6), tfie capacit;lllcecharging rate does not increase as rapidly as the gatc capacitance These two mechanismsexplain why the delay time dots not continue to decrc;rsc with diminishingoxide thiclrness mFig. 4.8a Because the drain current saturates at larger gate voltage, the delay time alsosaturatesat larger power supply.

o To,=3.6nmA To,=5.6nrn VGS = 3v

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Effective Channel Length urn)

v*s = 3v

t

Fig. 4 6 Drain saturation ament versus effective c h d a@ for f a n oxidet h i c k n ~ . he nsert shows the bias conditions wben the m e a t w8s me8scd


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o TOx=3.6nmA TOx=5.6nm

ir'= ov

0.0 0.2 0.4 0.6 0.8 1.0 1 3 1.4 1.6Effective Channel Length ( pm)

Fig. 4.7 Single stage voltage gain (8- versus &&e channel leqth far fouroxide thiclmesses. The solid lines indiW the maximum availde gain and thealternated lined are the gain meamred ab v,-v* = 03v.


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00

- - - - - - - - -T -

. . iS 10 1sOxide Thickness (nm) 20

Fig. 4.8(a) !PICE imulated ring osciUatm dclgr time opereded at a pawct supplyaf 3V versus oxide thickness for s e v d c h d engths. 'Ihe load Capacitanceis 0.lpFonway


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0.5

nQ)2 .4c)-sE172 0.2B

Ea 0.3.W

-0.1

0.0

Fig. 4S@) SPICE simulated (Tules ring oscillator delay time versus &ective channellength forTa - 86nm operaded at Mereat supply voltages.

VDS = 4v1 I 1 1 1 . I . d


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Chap.4

4 3 Design guidelines-94-

Based on thc experimental results presented in SectiOIls 4.1 and 4 .2 various design curveswere developed. As mentioned befon, ince oxide thickness, channel length, and supply vol-tage axe the key design parameters in this study, three types of design curves axe provided formaximum flexibility (Fig. 4.94.1 1). Each type of m e ixes one parameter while varying theother two. The intersection of these performance and reliability curyes (shaded area) indicatcsthe region of allowable device dimensions and/or power supply for both digital and analogapplications under some design specifications. Table 4.1summarizes he meanings of the sym-bols in Fig. 4.94.11 and lists the performance and reliability criteria used in developing t h edesign curves.

IABLEI

Time D c p d c n t Dielecdc Breakdown S 1%

Table 4.1 Design aitcriafor design c w c s .


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Chaps4 -95-

43.1 Oxide thickness versus channel lengthFig. 4.9 shows design c w c s whem the optimal oxide thickness for this technology is

plotted v e m channel length for a power supply of 3V. All the curves corresponding to thcconstant contours of different design considerations use the criteria listed in Table 4.1. Forexample, the m e arked by AV,,,was obtained from Rg. 4.1. The gate oxide and effectivechannel length combinations along this m e i l l give 0.1V threshold voltage shift Thearrows indicate the acceptable regions. Deviceswith T and Itf! n the acceptable region haveless threshold voltage shift than 0.1V. But tk channel-lengthcan not be too long due to I ~ Tand switching speed requirements, which set upper limits to device dimensions. The intersec-tion of all acceptable regions forms design windows (shaded regions). Because of differentdesign requirements for analog and digital circuits, different bounds (different windows) areused for these two applications. The breakdown curve is not included in Fig. 4.9-4.11 becauseit is not a limiting mechanism under normal device operation.

According to the design windows, the minimum gate oxide thickness at this supply vol-tage is limited to 5.6nm by the gate-induced drain leakage current, and may be limited by thetime-dependent dielectric breakdown for technologieswith less robust oxide. For digital appli-cations, depending upon the oxide thickness, the minimum channel length is determined byeither the threshold voltage shift or by the hot-electron reliability criterion; the minimum allow-able channel length is found to be 0 . 2 6 ~t Ta = 7.8nm. The largest channel length is about0.45p.m limited by the switching speed requirement. For analog applications, the minimumchannel length is about 0 . 3 1 ~t T = 6.3nm limited by the voltage gain requirement. Itshould be kept in mind that the minimum (maximum) device dimensions mentioned here referto the "worst case" conditions. For example, if the channel length variation for a given processis fo . lpm, then a minimum channel of 0 . 2 6 ~mplies a nominal channel length of 0.36~.The same argument also applies to the oxide thickness. Another advantage of these designcurves is that the relative importance of each mechanism can be identified for any devicedimensions which makes design trade-offs very clear and provides a direction for future tech-


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Qlap.4

nology devdopmcnL

AVT Digital

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Effective Channel Length (pm)

-96-

ApplicationApplication

Eg. 9 ~ g ne s for a power s u d y of 3 ~ .iBFerent &es c to theconstant contour of each design d & r a t i o n with the criteIia listed in Table4.1. 'zbe shaded areas indicate the allowable regions.


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Qtap.4 -97-

43.2 Power supply versus channel lengthFig. 4.10 shows design curves where the suitable power supply for this technology is

ploncd against channel length for T= = 8.6mn. Again, each curve cormponds to the constantcontour of a design criterion listed in Table 4.1 and shaded regions are the allowable designwindows. At this oxide thickness, the maximum power supply voltage is limited by the hot-electron reliability while the minimum power supply voltage is limited by the switching speedrequirement. The minimum allowable channel lengths is about 0.28pm for digital applicationslimited by the threshold voltage shift, and is about 0 . 3 6 ~or analog applications limited bythe voltage gain. These values are roughly independent of the power supply voltage becausethe peak voltage gain is independent of power supply and short-channel effect is much moresensitive to the channel length than to the power supply. The maximum channel length isabout 0.48pn. At a power supply of 3.3V,hot-electron reliability does not pose a problem todevices with channel length longer than 0.4 pm implying that LDD may not be needed, butwith the bum-in consideration, longer channel length or LDDmay s t i l l be necessary.433 Power supply versus oxide thickness

The last type of a w e s is the design curves for Lg = 0 . 3 ~ . ig. 4.11 shows powersupply versus oxide thickness of each design consideration for Ld = 0 . 3 ~ . t this channellength, he maximum power supply is Limited to about 3V due to hot-electron reliability, nomatter what oxide thickness is used. The minimum power supply is determined by the speedrequirement, about 2V at TQ = 4.0~1. The maximum TQ s about 9nm for digital applica-tions and 6 . 5 ~ 1or analog applications due to voltage gain requirement43.4 Junction depth

Although the junction depth has been fixed at 0.18pm in this study, with slightmodifications, the design curves in Fig. 4.94.11 can be extended to other junction depths. Forexample, if the junction depth is decreased, short-channel and DIBL effects and punchthroughcurrents would diminish. However, hot-elemn reliability would degrade due to the increase


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chap3in the peak channel electric field.

5 1

Wh 3 .nnI A I

-98-

+G

00.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Effective Channel Length (pm)

Fig. 4.10 Design a w e s for T - 8 6 m Diffezeat a w e s comspd to the cuastmtcontouf of each design consideration with the critcxia listed inTaMe 4.1. 'Iheshaded lI#Ls indicate the 8lIlcnVablt regions.


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m . 4

5

4

Design Curves for Leff = 0.3- -- .-___--__

0 5 IO IS 20Oxide Thickness (nm)


Fig. 4.11 Design curves for & - 03pm.mereat curves cOneSpOnd to the camtzmtcontou~f each design Consideaation with the criteria listed inTde .1. ?beshaded areas indicate the allowableregions.


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-100-435 ther power supply and device dimensiau

M g n c w e s for other pow= sq#yYT,, d h alues am be obtaincdwith thc s m capprod~Similar design curves as those in Fig. 4 9 far a v e r supply of33V arc shown inFig. 4.12. Since the &vice lifetime is more sensitive to the powex supply than other mdumisms (see Fq. . 1 4 4 , this fact is dected by &e large shift OII the zm cureve in Fig. 4 2COmpEned to that in Eg. 9. 'Ihe design windows arc d e r nd shift oward longer chrondand thicker oxide directions as43.6 Other technologies

'be same methodology used to derive design curves shown in Figs. 494.11 can also beextended to any technology, ncluding p-channd aad LDD devices. For example, with LDDdevices, short channel, DIBL, and GIDL ffects would be less s c v m and the hotelectron lifetime would be longer. However, currentdriving capbility and gab would decrease due to theincrease in s d d r a i n resistance. 'Iherefore, the design windaws in Fig. 4 9 will movetoward the lower left, i.e., shorter channel length a d hinner oxide as expecbd The LDDeffects on Fig. 4.10 and 4.11 can also be a~lalogizcd,


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-101-

I I I I I I I I I 40.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Effective Channel Length (pm)


Fig. 4J.2 Design curves far a power supply d 33V.


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w - 4 -102-4.4 References

(4.1) H. Masuda, M Nakai, and M.Kubo, "Characteristics and Limitation of Scaled-DownMOSFFT's Due to Two-Dimensional Field Effect," IEEE Tran onElecmn Devices,VOL ED-26, pp.980-986, J u n ~ , 979.

[4.2] J.R. Brews, W. ichtner, E.H.Nicollian, and S.M. Sze, "Generalized Guide for MOS-FET Miniatuxization," IEEE Electron Device Latten, voL EDLl , no. 1, Jan., 1980.H. Shichijo, "A Recxamination of Practical Performance Limits of Scaled n-Umncland pChannel MOS Devicts for -1," Solid-state Electronics, vol. 26, no. 10,

(4.3)

pp.969-986, 1983.[4.4] T.Y. Chan, J. Chen. P.K.KO, and C. Hu, "The Impact of Gate-Induced Drain Leakage

Current on MOSFET Scaling," IEDM Tech. Digs., p.718, 1987.[4.5] C. Chang and J. Lien, "Comer-Field Induced Drain Leakage in Thin Oxide MOS-

F I ~ s , "EDM Tech Digs., p.714, 1987.H. Sasaki, M. Saitoh, and K. Hashimoto, "Hot-Carrier Induced Drain Leakage Cumntin N-Channel MOSFET," IEDMTech.Digs., p.726, 1987.

[4.6]

[4.7] M.H. Woods and B.L.Euzent, "Reliability in MOS Integrated Circuits," IEDM Tech.Digs., p.50, 1984.

[4.8] J. Lee, I.C. men, and C. Hu, Modeling and Characterization of Gate Oxide Reliabil-ity," IEEETran. on Electron Devices, 1989.

[4.9] R. MoaUami, J. Lee, I.C.Chen, and C. Hu, Projecting the Minimum AcceptableOxide Thickness fir Tie-Dependent Dielectric Breakdown," EDM Tech. Digs.,p.710, 1988.

[4.10] P.M. Let,UM. Kuo, K. seki, P.K. KO,and C. Hu, "Circuit Aging Simulator (CAS),"IEDM Tech Digs.,pp.134-137, 1988.


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Cbap.4 -103-(4.111 C. Hu,S. Tam, F.-C. Hsu, P K O,T.Y. Qlan, and KtW. Tenill, "Hot-Electron-

Induced MOSFET Degradation - Model, Monitor, and Impmvemau." IEEE Tran. onElectron Devices,voL ED-32, p.375, Feb.1985.

I4.121 M. oshida, IEDM Tech. Digs.,p.254, 1985.


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-104-Chapter 5

A DEEP-SUBMICROMETER MOSFETMODEL FORANALOGDIGITAL CIRCUIT SIMULATIONSIn a t i o n to high m a t rive, mother +or advantage of scaleddown devices is

reduced device areawhich a l l ows high= integration levds. With the dwnatic increase inthethe

number of transistors per chip, the circuit complexity and the fabricationcost also incnxse ~ a r pportionally. In order to speed up the VLSVULSI system design and to reduce costs, it hasbecome necessary to s ta r t the circuit design in the early stages of technology developmeat andto predict circuit behavior before the circuit is ~lctudy abricated, both of which require inteesive use of circuit simulato~~. ince the device charactdstics of small-geomeby devices arehighly sensitive to parameter variations, optimal circuit designs become even more difficult tocreate than before. Therefore, an ~ ~ c ( w ~ t end a m p u ~ o o a U y fficient drain aurent LllDddfor deepsubnicnxneter MOSFEI's becomes extremely crucial and indispeasabie in developingfuture system designs.

deep sub micron modelling

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