ddca_ch5 - class11

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5

5

.

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5

5 ::

•

• •

•

•

•

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5

•

•

Decimal Binary

23042x 01010111

5 x 7 = 35

460920+9660

01010101

0101

0000

x

+0100011

230 x 42 = 9660

multipliermultiplicand

partialproducts

result

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5

4 4

x B3

B2

B1

B0

A3B0A2B0A1B0A0B0

A3

A2

A1

A0

A3B1A2B1A1B1A0B1

A3B2 A2B2 A1B2 A0B2A3B3A2B3A1B3A0B3+

P7

P6

P5

P4

P3

P2

P1

P0

0

P2

0

0

0

P1

P0

P5

P4

P3

P7

P6

A3

A2

A1

A0

B0

B1

B2

B3

x

A B

P

44

8

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Q

CLK

Reset

N

+N

1

CLK

Reset

N

N

Q N

r

Symbol Implementation

• Increments on each clock edge

• Used to cycle through numbers. For example,

– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…

• Example uses:

– Digital clock displays

– Program counter: keeps track of current instruction executing

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()

B

()

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NQ

Sin

Sout

CLK

Sin

Sout

Q0

Q1

QN-1

Q2

• Shift a new bit in on each clock edge

• Shift a bit out on each clock edge

• Serial-to-parallel converter : converts serial input (S in) toparallel output (Q0: N -1)

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Clk0

1

0

1

0

1

0

1

D0 D1 DN-1D2

Q0

Q1

QN-1

Q2

Sin

Sout

Load

• When Load = 1, acts as a normal N -bit register

• When Load = 0, acts as a shift register

• Now can act as a serial-to-parallel converter (Sin to Q0: N -1) ora parallel-to-serial converter ( D0: N -1 to S out)

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Address

Data

ArrayN

M

Address Data

11

1001

00

depth

0 1 0

1 0 01 1 0

0 1 1

width

Address

Data

Array2

3

• 2-dimensional array of bit cells

• Each bit cell stores one bit

• N address bits and M data bits:– 2 N rows and M columns

– Depth: number of rows (number of words)

– Width: number of columns (size of word)

– Array size: depth × width = 2 N × M

A

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5

Address Data

11

10

01

00

depth

0 1 0

1 0 0

1 1 0

0 1 1

width

Address

Data

Array2

3

• 22 × 3-bit array

• Number of words: 4

• Word size: 3-bits• For example, the 3-bit word stored at address 10 is 100

A

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Address

Data

1024-word x

32-bitArray

10

32

A

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A B

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wordline311

10

2:4Decoder

Address

01

00

storedbit = 0

wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

bitline2

bitline1

bitline0

Data2 Data1 Data0

2

• Wordline:– like an enable

– single row in memory array read/written

– corresponds to unique address

– only one wordline HIGH at once

A

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5

• Random access memory (RAM): volatile

• Read only memory (ROM): nonvolatile

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5

• Nonvolatile: retains data when power off

• Read quickly, but writing is impossible orslow

• Flash memory in cameras, thumb drives, and

digital cameras are all ROMs

Historically called read only memory because ROMs

were written at manufacturing time or by burning fuses.Once ROM was configured, it could not be written again.

This is no longer the case for Flash memory and other

types of ROMs.

:

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• DRAM (Dynamic random access memory)

• SRAM (Static random access memory)

• Differ in how they store data:

– DRAM uses a capacitor

– SRAM uses cross-coupled inverters

A

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• Invented DRAM in

1966 at IBM

• Others were skeptical

that the idea would

work • By the mid-1970’s

DRAM in virtually all

computers

, 1932

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wordline

bitline

storedbit

• Data bits stored on capacitor

• Dynamic because the value needs to be refreshed

(rewritten) periodically and after read:

– Charge leakage from the capacitor degrades the value

– Reading destroys the stored value

A

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wordline

bitline

wordline

bitline

+ +storedbit = 1

storedbit = 0

A

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wordline

bitline bitline

A

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wordline311

10

2:4Decoder

Address

01

00

storedbit = 0

wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

bitline2

bitline1

bitline0

Data2

Data1

Data0

2

wordline

bitline bitline

wordline

bitline

A

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wordline

bitline

wordline

bitline

bit cellcontaining 0

bit cellcontaining 1

:

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5

• , 19711994

•

1970

•

• ;

1988• $25

, 1944

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Address Data11

10

01

00

depth

0 1 0

1 0 0

1 1 0

0 1 1

width

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2 = 1⊕ 0

1 = 1 + 0

0 = 1 0

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11

10

2:4

Decoder

A, B

Z Y X

01

00

2

Implement the following logic functions using a 22 × 3-bit

ROM:

– X = AB– Y = A + B

– Z = A B

:

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11

10

2:4Decoder

A, B

Z Y X

01

00

2


ROM:

– X = AB– Y = A + B

– Z = A B

:

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wordline311

10

2:4Decoder

Address

01

00

storedbit = 0

wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

bitline2

bitline1

bitline0

Data2

Data1

Data0

2

2 = 1⊕ 0

1 = 1 + 0

0 = 1 0

A A

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memory array:

– X = AB

– Y = A + B

– Z = A B

A

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wordline311

10

2:4

Decoder

A, B

01

00

storedbit = 1

wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 0 storedbit = 1 storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 0

storedbit = 0

bitline2

bitline1

bitline0

X Y Z

2


memory array:

– X = AB

– Y = A + B

– Z = A B

A

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storedbit = 1

storedbit = 0

00

01

2:4Decoder

A

storedbit = 0

bitline

storedbit = 0

Y

B

10

11

4-word x 1-bit Array

A B Y0 0

0 1

1 0

1 1

0

0

0

1

Truth

Table

A1

A0

Called lookup tables (LUTs): look up output at each input

combination (address)

A

ddca_ch5 - class11

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