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Davinci-DM644xEvaluation Module

2006 DSP Development Systems

ReferenceTechnical

DaVinci-DM644x Evaluation Module Technical Reference

508165-0001 Rev. C October 2006

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2006 Spectrum Digital, Inc.

Contents

1 Introduction to the DM644x Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the DM644x Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-72 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the DM644x Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.3 ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.4 Compact Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.5 Memory Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.6 VLYNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.7 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.8 EMIF Buffer/Decoder Control CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.1 On Chip Video Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.2 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1 I/O Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4.2 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5 SPDIF Analog, and Optical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.7 DM644x Core CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.8 USB Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.9 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the DM644x Evaluation Module and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1 J1, Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.2 J2, MSP430 JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.3 J3, SD/MMC/MS Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.4 J4, CS2 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.5 J5, SD/MMC/MS Termination Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.6 J6, External RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.7 J7, USB Host/Client Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.8 J8, Dual RCA Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.9 J9, Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.10 J10, USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.11 J11, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.12 J12, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.13 J13, SPDIF Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.14 J14, +5V Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.15 J15, SM/xD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.16 J16, Mini PCI VLYNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.17 J17, FPGA Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.3 Peripheral Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.3.1 P1, Compact Flash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.3.2 P2, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.3.3 P3, Line In/Mic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.3.4 P4, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3.5 P5, Dual Output RCA Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.3.6 P6, UART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.4 JP1, ATA Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.5 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.6 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.6.1 S1, EMU0/1 Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.6.2 S2, TRSTn Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.6.3 S3, Processor Configuration/Boot Load Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.6.4 S4, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.6.5 SW1, Power On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.7 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.7.1 DC1, EMIF Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.7.2 DC2, GIOV33/Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

3.7.3 DC3, SPI, McBSP, I2C Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3.7.4 DC4, Video Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.7.5 DC5, Video Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.7.6 DC6, SD Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.7.7 DC7, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.8 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the DM644x Evaluation ModuleB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the DM644x Evaluation Module

About This Manual

This document describes the board level operations of the DM644x Evaluation Module(EVM). The EVM is based on the Texas Instruments DM644x Processor.

The DM644x Evaluation Module is a table top card that allows engineers and softwaredevelopers to evaluate certain characteristics of the DM644x processor to determine ifthe processor meets the designers application requirements. Evaluators can createsoftware to execute on board or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The DM644x Evaluation Module will sometimes be referred to as the DM644x EVM orEVM.

Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents, Application Notes and User Guides

Information regarding DaVinciTM technology can be found at the following TexasInstruments website:

http://www.ti.com/corp/docs/landing/davinci/index.html

Table 1: Manual History

Revision History

A Production Release

B Corrected I2C address of TVP5146

C Corrected Pin 70, Table 30, DC1 connector

Table 2: Board History

Revision History

C Production Release

1-1

Chapter 1

Introduction to the DM644x EVM

Chapter One provides a description of the DM644x EVM along with the keyfeatures and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-7

Spectrum Digital, Inc

1-2 DM644x EVM Technical Reference

1.1 Key Features

The DM644x EVM is a standalone development platform that enables users toevaluate and develop applications for the TI DaVinci processor family. Schematics,logic equations and application notes are available to ease hardware development andreduce time to market.

The EVM comes with a full complement of on board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments DM644x processor with an ARM processor operating up to 300 Mhz. and a C64xx DSP operating up to 600 Mhz.

• 1 video input port, supports composite or S video

• 4 video DAC outputs - component, RGB, composite

• 256 Mbytes of DDR2 DRAM

• UART, Media Card interface (SD card, xD card, SM card, MS card, MMC)

• 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 4 Mbytes SRAM

• AIC33 stereo codec

Figure 1-1, Block Diagram DM644x EVM

SM/xD

CompactFlash

IR PWRSW

S3

Con

fig

DC3 DC2

3VBAT

DC1 (EMIF)

SD/MMC/

MS

TI JTAG MSP430 JTAGS

VH

SIN

US

B

VID

EO

IN

AU

DIO

IN

HP

OU

T

AU

DIO

OU

T

S/P

DIF

Opt

ical

S/P

DIF

Ana

log

UART

+5V

MSP430

User LEDs

DC7

DC6

S1 S2

NANDFlash

1.2V DSP Core Voltage

1.8V I/O Voltage

3.3V Board Supply Voltage

AIC33

J5

I2CGPIO

I2CGPIO

I2C

GP

IOI2

CE

EP

RO

M

D A V I N C IEVALUATION MODULE

A TEXAS INSTRUMENTS TECHNOLOGY

NORFlash

DC4 (VIDEO IN)

TVP5146

S/PDIFDrivers

SV

HS

OU

TDAC OUT

DC5 (VIDEO OUT)

EMIF

Video Ports

AT

A H

ard

Dis

kDDR

I2CCPLD

Serial Media

DaVinci

ENETPHY

EMAC

AlteraJTAG

DDR

DDR

10/100ENET


1-3

• USB2 Interface

• 10/100 MBS Ethernet Interface

• IR Remote Interface, real time clock, via MSP430

• Configurable boot load options

• JTAG emulation interface

• 8 user LEDs

• Single voltage power supply (+5V)

• Expansion connectors for daughter card use

• ATA Interface, Vlynq Interface

• SPDIF Interface, analog, and optical

1.2 Functional Overview of the DM644x EVM

The DM644x on the DaVinci EVM interfaces to on-board peripherals through the16-bit wide EMIF peripheral interface pins. The DDR2 memory is connected to its owndedicated 32 bit wide bus. The EMIF bus is also connected to the Flash, SRAM,NAND, and daughter card expansion connectors which are used for add-in boards.

On board video decoder and on chip encoders interface video streams to the DM644xprocessor. One decoder and 4 on chip DAC channels are standard on the EVM. Onscreen display functions are implemented in software on the DM644x processor.

An on-board AIC33 codec allows the DSP to transmit and receive analog audio

signals. The I2C bus is used for the codec control interface, while the McBSP controlsthe audio stream. Signal interfacing is done through 3.5mm audio jacks that correspondto microphone input, line input, and line output. The codec can select the line input asthe active input.

The EVM includes 8 LEDs, IR interface, and Real time clock which can be used toprovide the user with interactive feedback. These interfaces are implemented via

software on a MSP430 and are accessed by reading and writing to the I2C registers.

Media cards, ATA interface, VLYNQ, and ethernet MAC interfaces are integratedperipheral on the DM644x processor exploiting its system on a chip architecture.

An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and+1.8V memory and DM644x I/O. The board is held in reset until these supplies arewithin operating specifications.



Code Composer communicates with the EVM through an external emulator via the20 pin external JTAG connector.

1.3 Basic Operation

The EVM is designed to work with TI’s Code Composer Studio development, orstandard GDB tool environments. Code Composer communicates with the boardthrough an external JTAG emulator. To start, follow the instructions in the Quick StartGuide to install Code Composer. This process will install all of the necessarydevelopment tools, documentation and drivers.

Detailed information about the EVM including examples and reference material isavailable on the EVM’s CD-ROM.


1-5

1.4 Memory Map

The DaVinci family of processors have a large byte addressable address space, somelimitations to byte addressing are determined by peripheral interconnection to theDavinci device. Program code and data can be placed anywhere in the unified addressspace. Addresses are multiple sizes depending on hardware implementation. Refer tothe appropriate device data sheets for more details.

The memory map shows the address space of a generic DaVinci processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.

The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces tothe DDR2 memory. The other EMIF has 4 separate addressable regions called chipenable spaces (CS2-CS5). The Flash, NAND Flash, or SRAM are mapped into CE2space and selectable via J4. Daughter cards use CE2 and CE3. When CE2 is used fordaughter card interfacing J4 must be set appropriately. CS4 and CS5 are reserved forthe VLYNQ interface on the EVM.

ARM Instruction RAM

DM644x EVMGeneric DaVinciAddress SpaceAddress

0x00000000

0x00040000

0x02000000

0x06000000

0x08000000

0x80000000

AEMIF CS3

AEMIF CS4

AEMIF CS5

DDR

Figure 1-2, Memory Map, DM644x EVM

ARM Instruction RAM

ARM Data RAM ARM Data RAM

AEMIF CS2 Flash/NAND/SRAM/DC

0x04000000DC

VLNQ

VLNQ

DDR



1.5 Configuration Switch Settings

The EVM has a single 10 position configuration switch that allow users to control theoperational state of the processor when it is released from reset. The configurationswitch is labeled S3 on the EVM board.

Switch S3 configures the boot mode that will be used when the DSP starts executing.By default the switches are configured to EMIF boot (out of 8-bit Flash) in little endianmode. The table below shows the settings for switch S3.

Table 1: Configuration Switch S3 Settings

Position Name Function Boot Mode

1 COUT0 Boot Mode 0 00 - Boot from ROM NAND01 - Boot from AEMIF10 - Boot from ROM HPI11 - Boot from ROM UART

2 COUT1 Boot Mode 1

3 COUT2 Bus width: 0=8 bit, 1=16 bit

4 COUT3 0=ARM boots DSP,1=C64xx self boots

5 YOUT4

6 YOUT3

7 YOUT2

8 YOUT1

9 YOUT0

10 USER For Demos


1-7

1.6 Power Supply

The EVM operates from a single +5V external power supply connected to the mainpower input (J14), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into+1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The +1.2Vsupply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffersand other chips on the board. The +1.8 volt supply is used for DM644x I/O, low voltagememory, and peripherals, and DDR2 memory.

There are four power test points on the EVM; TP14, TP25, TP26, and TP43. These testpoints provide a convenient mechanism to check the EVM’s multiple power supplies.The table below shows the voltages for each test point and what the supply is used for.

Table 2: Power Test Points

Test Point Voltage Voltage Use

TP43 +1.2 V DM644x Core

TP25 +1.2 V DM644x Core/Power Down

TP26 +1.8 V DDR2 Memory, DSP I/O, and logic

TP14 +3.3V DSP I/O and logic

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe DM644x EVM.

Topic Page

2.1 EMIF Interfaces 2-22.1.1 DDR2 Memory Interface 2-22.1.2 Flash, NAND Flash, SRAM Memory Interface 2-22.1.3 ATA Interface 2-22.1.4 Compact Flash Interface 2-32.1.5 Memory Card Interface 2-32.1.6 VLYNQ Interface 2-32.1.7 UART Interface 2-32.1.8 EMIF Buffer/Decoder Control CPLD 2-32.2 Input Video Port Interfaces 2-42.2.1 On Chip Video Output DACs 2-42.2.2 AIC33 Interface 2-52.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator 2-62.3 Ethernet Interface 2-72.4 I2C Interface 2-72.4.1 I/O Expanders 2-82.4.2 MSP430 2-92.5 SPDIF Analog, and Optical Interfaces 2-92.6 Daughter Card Interface 2-102.7 DM644x Core CPU Clock 2-102.8 USB Clock 2-102.9 Battery 2-11



2.1 EMIF Interfaces

A separate 16 bit EMIF with four chip enables divide up the address space and allowfor asynchronous accesses on the EVM. CE4 and CE5 are reserved for VLYNQ useallowing the EVM two dedicated chip enables. CE2 is used for Flash, NAND Flash,SRAM, and xD and SM Media cards. Both CE2 and/or CE3 can be routed to thedaughter card interface connectors.

2.1.1 DDR2 Memory Interface

The DM644x device incorporates a dedicated 32 bit wide DDR2 memory bus. The EVMuses two gigabit 16 bit wide memories on this bus, for a total of 256 megabytes ofmemory for program, data, and video storage. The internal DDR controller uses aPLL to control the DDR memory timing. The interface supports rates up to 166 Mhz.,and is clocked on differential edges for optimal performance. Memory refresh for DDR2is handled automatically by the DM644x internal DDR controller.

2.1.2 Flash, NAND Flash, SRAM Memory Interface

The DM644x has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or4 megabytes of SRAM memory mapped into the CE2 space. This NOR Flash memory,and NAND Flash memory are used primarily for boot loading. SRAM is used fordebugging application code. The CE2 space is configured as 16 bits wide on theDM644x EVM for NOR Flash and SRAM usage, and 8 bit wide for NAND flash usage.

2.1.3 ATA Interface

The DM644x integrates a standard ATA interface on chip. This interface is multiplexedwith the EMIF interface at +1.8 volt levels. The EVM incorporates a standard Lap driveHard Disk Drive connector, JP1. Level translators are used to translate the data to +3.3 volt interface levels and a CPLD is used to translate the control interface to

+3.3V levels. Buffer control is implemented via the CPLD. The drive is selected via I2CI/O expander U35 bit P6. When the hard drive is in use other peripherals such as thecompact Flash interface and the xD/SM media cards on the EM bus are not accessible

without reconfiguring the EMIF or I2C select lines.

Table 1: EMIF Interfaces

Chip Select Function

CE2NOR Flash, NAND Flash, SRAM

(see JP4 definition)

CE2Daughter Card Interface

(see JP4 definition)

CE3 Daughter Card Interface


2-3

2.1.4 Compact Flash Interface

The EVM incorporates a PIO type Compact Flash interface. The Compact Flash is

selected via I2C expander U35 bit P5. The interface is multiplexed on the EMIFinterface. When the Compact Flash interface is in use other interfaces such as the ATAor xD/SM card on the EMIF cannot be used without reconfiguring the EMIF or interfaceselects.

2.1.5 Memory Card Interface

The EVM supports a number of media card interfaces. On the EMIF the EVM supports

xD/SM interfaces. These are selected via U35 I2C I/O expander. On the peripheralinterface the EVM supports MMC/MS/MSPro/SD.

When the xD/SM interface is used other interfaces such as the ATA or CF interface onthe EMIF cannot be used without reconfiguring the EMIF or interface selects.

2.1.6 VLYNQ Interface

The DM644x brings its internal VLYNQ interface out to a mini PCI connector J16. TheVLYNQ interface is multiplexed on the EM bus and this bus must be reconfigured afterboot up to support VLYNQ. A multiplexer is used to minimize board layout stubs andallow as direct as possible interface for the VLYNQ signals.

2.1.7 UART Interface

The internal UART0 on the DM644x device is driven to connector J6. The UART’sinterface is level shifted and routed to the RS-232 line drivers prior to being broughtout to a DB-9 connector, J6.

2.1.8 EMIF Buffer/Decoder Control CPLD

The EMIF buffer and decode functions are implemented with a CPLD. The EVM boardincorporates an Altera MAX II EPM240TCG100 device. The device has 2 banks ofI/O. One bank is used for +1.8 volt signals. The other bank is for+3.3 volt signals. This allows the device to do level shifting.

The CPLD incorporates the ATA control interface, CF control interface, xD/SM controlinterface along with a divide by 8 counter for video synchronization. The CPLD alsoincorporates various logic functions for buffer control and glue logic.



2.2 Input Video Port Interfaces

The DM644x EVM supports video capture via the devices internal video ports. A TexasInstruments TVP5146 is used to decode composite video or S-video inputs into thedevice after being level shifted. J11 is used for the S-video inputs and J12 for thecomposite inputs on the EVM.

User inputs can be driven via daughter card connector DC4 when the on board leveltranslator is tristate via driving control Capture Enable signal high on DC4.

2.2.1 On Chip Video Output DACs

The DM644x incorporates 4 output DACs to interface to various output standards. TheDACs are buffered via opamps and driven to a quad RCA jack, J8. The outputs of theDACs are programmable to support composite video, component video, or RGB.

Figure 2-1, DM644x CPLD Block Diagram

SM/xD

CompactFlash

IR PWRSW

S3

Con

fig

DC3 DC2

3VBAT

DC1 (EMIF)

SD/MMC/

MS

TI JTAG MSP430 JTAG

SV

HS

IN

US

B

VID

EO

IN

AU

DIO

IN

HP

OU

T

AU

DIO

OU

T

S/P

DIF

Opt

ical

S/P

DIF

Ana

log

UART

+5V

MSP430

User LEDs

DC7

DC6

S1 S2

NANDFlash

1.2V DSP Core Voltage

1.8V I/O Voltage

3.3V Board Supply Voltage

AIC33

J5

I2CGPIO

I2CGPIO

I2C

GP

IOI2

CE

EP

RO

M

D A V I N C IEVALUATION MODULE

A TEXAS INSTRUMENTS TECHNOLOGY

NORFlash

DC4 (VIDEO IN)

TVP5146

S/PDIFDrivers

SV

HS

OU

TDAC OUT

DC5 (VIDEO OUT)

EMIF

Video Ports

AT

A H

ard

Dis

k

DDR

I2CCPLD

Serial Media

DaVinci

ENETPHY

EMAC

AlteraJTAG

DDR

DDR

10/100ENET


2-5

2.2.2 AIC33 Interface

The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output ofaudio signals. The codec samples analog signals on the microphone or line inputs andconverts them into digital data so it can be processed by the DSP. When the DSP isfinished with the data it uses the codec to convert the samples back into analog signalson the line output so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internal

configuration registers and one to send and receive digital audio samples. The I2C busis used as the unidirectional control channel. The control channel is generally only usedwhen configuring the codec, it is typically idle when audio data is being transmitted,

The McBSP is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The EVM examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side.

The codec has a programmable clock from a PLL1705 PLL device. The default systemclock is 18.432 Mhz. The internal sample rate generate subdivides the 18.432 MHzclock to generate common frequencies such as 48KHz and 8KHz. The sample rate isset by a codec register. The figure below shows the codec interface on the DM644xEVM.

Figure 2-2, DM644x EVM CODEC INTERFACE

DOUTDIN

BCLKWCLK

MIC IN

LINE IN

LINE OUT

HP OUT

McBSP

I2S Format

AIC33 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT

SCLSDA

I2CControlSCL

SDAI2C Format

DRDXCLKRCLKXFSRFSX

Control Registers

ADC

DAC



2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator

The DM644x EVM implements a multiple PLL clock generator for creating the Audioclocks for the board.

In streaming video applications the audio and video sequences can losesynchronization. The DM644x uses a VCXO interpolation circuit to incrementally speedup or slow down the STCLK input to allow for this synchronization to remain locked.

The PWM0 and timer inputs on DM644x are used to control this feature. The PWM0 pindrives a PICX100-27W Voltage Controlled Oscillator which is divided by 8 in the CPLDand fed back into the timer input pin.

The STCLK is also a source clock for the PLL1705 programmable PLL device. Thisdevice creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.

The PLL1705 is programmable via an I2C and Expander U18. Software sequencing onthe I/O expander is required to interface correctly to the PLL1708’s programmableinputs.

The diagram below is a simplified diagram of this clocking scheme.

DM644x

VCXOCircuit UsingPICX100-27

PLL1705

SCK03SCK02

MCK02MCK01

XT1

PWM0 IN

PLLMS

PLLMC

PLLMD

To I/O Expander

Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator

STCLKTIMER

AUDIO_CLKSCK01SCK00

CPLD /8Counter

VID_CLK


2-7

2.3 Ethernet Interface

The DM644x integrates an ethernet MAC on chip. This interface is routed to the PHYvia CBT switches. The EVM uses an Intel LXT971 PHY. The 10/100 Mbit interface isisolated and brought out to a RJ-45 standard ethernet connector, P2. The PHY directly

interfaces to the DM644x. The ethernet address is stored in the I2C serial ROM duringmanufacturing.

The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellowand indicate the status of the ethernet link. The green LED, when on, indicates link andwhen blinking indicates link activity. The yellow LED, when illuminated, indicates fullduplex mode.

When configuring the PHY use the high drive option in the PHY register 26 tocompensate for the routing length and extra capacitance of the CBT switches.

2.4 I2C Interface

The I2C bus on the DM644x is ideal for interfacing to the control registers of many

devices. On the DM644x EVM the I2C bus is used to configure the video decoder,

stereo Codec, I/O expanders, and communicate with the MSP430. An I2C ROM is alsointerfaced via the serial bus. The format of the bus is shown in the figure below.

The addresses of the on board peripherals are shown in the table below.

Table 2: I2C Memory Map

Device Address R/W Function

TVP5146 0x5D R/W Capture 1 Decoder

PCF 8574A 0x38 R/W LEDs

PCF 8574A 0x39 R/W PLL/User Switch

PCF 8574A 0x3A R/W Peripheral Selects

TLV320AIC33 0x1B R/W CODEC

24WC256 0x50 R/W I2C EEPROM

MSP430 0x23 R/W LEDs, IR, RTC

Figure 2-4, I2C Bus Format

Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop

Write Sequence

Start Slave Address R Data STOP

Read Sequence



2.4.1 I/O Expanders

The DM644x EVM uses three I2C expanders to handle various bit I/O functions. Eachof these is an bit I/O expander, a PCF8574A. At Power Up Reset the expanders areinitialized to 0xFF, all ones. The functions for each of the I/O expanders are shown inthe tables below.

* - useful as input only High Input - Switch in “ON” Position Low Input - Switch in “OFF” Position

Table 3: U2 I/O Expander

Pin Number Function States

P0 User LED DS8 0 = Turns LED On, 1 = Turns LED Off









Pin Number Function

P0 PLL Program Interface, PLL CSEL Pin

P1 PLL Program Interface, PLL SR Pin

P2 PLL Program Interface, PLL FS1 Pin

P3 PLL Program Interface, PLL FS2 Pin

P4 Spare IO1

P5 Spare IO2

P6 Spare IO3

P7 User DIP Switch *


2-9

* Only one interface, ATA or CF, can be enabled at a time

2.4.2 MSP430

The DM644x EVM incorporates infrared remote, real time clock, and some bit I/O in a

MSP430 microcontroller. The I2C interface is used on the DM644x processor to

communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus.

2.5 SPDIF Analog, and Optical Interfaces

The McBSP’s DX pin on the DM644x can be configured to operate as a SPDIFtransmitter. The DM644x EVM supports a single SPDIF output with both analog andoptical interfaces. The analog SPDIF output pin is routed to a level translator then to adriver and filter circuit before being output on J13. The same level translator is used foranother driver which then drives the optical transmitter U65. When the SPDIF interfaceis enabled the TLV320AIC33 codec is disabled.


Pin Number Function State

P0 USB Bus Drive 0 = Enable USB Bus Drive

P1 VDD IMX Enable 0 = Disables VDDIMX supply

P2 VLYNQ 0 = Turns on VLYNQ Mux U11

P3 Compact Flash Reset Drives Reset Low to CF Adapter

P4 Not Used

P5 WLAN Reset 0 = Removes Reset from WLAN

P6 ATA Select * 0 = Enables ATA Interface

P7 Compact Flash Select * 0 = Enables CF Interface



2.6 Daughter Card Interfaces

The EVM provides expansion connectors that can be used to accept plug-in daughtercards. The daughter card allows users to build on their EVM platform to extend itscapabilities and provide customer and application specific I/O. The expansionconnectors are for all major interfaces including memory, peripherals, and videoexpansion.

The pin outs for this interface are documented in Section 3.

The memory connector provides access to the DSP’s EMIF signals to interface withmemories and memory mapped devices.

The video capture port is brought out to the daughter card interface. Four signals areused to disable the on board video peripherals so that they can be used by theexpansion connector. The table below indicates the operation of these signals.

Other than the buffering, most daughter card signals are not modified on the board.

2.7 DM644x Core CPU Clock

The DM644x EVM uses a 27 Megahertz crystal to generate the input clock. TheDM644x has an internal PLL which can multiply the input clock to generate the internalclock. The PLL multiplier is set via software on the DM644x device.

2.8 USB Clock

The DM644x EVM uses a 24 Mhz crystal for the USB II clock generator. The USBcontroller is completely integrated in the DM644x device.

Table 6: Daughter Card Video Enable

SignalState To Enable Daughter Card

Use

DM644x Signals Enables

CAPTURE_EN 1DC4 YI0-YI7 PCLK,VD,HD

McBSP_EN 1 DC3 McBSP

ENET_ENABLE 1 DC2 GIOV33 pins


2-11

2.9 Battery

The DM644x EVM incorporates a battery holder to provide backup power to theMSP430’s real time clock when the power is not applied to the board. The optionalbattery should be +3 volt 20 millimeter coin type Lithium single cell.

Some common part numbers for batteries which should operate in the EVM are shownin the table below.

These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo,Sony, Sieko, Toshiba, Varta, and other battery manufacturers.

Table 7: Battery Part Numbers

Part Numbers

CR2032

DL2032

BR2032

CR2025

BR2025

CR2016

BR2016

DL2016

3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the DM644x EVM and itsinterfaces.

Topic Page

3.1 Board Layout 3-33.2 Connectors 3-53.2.1 J1, Emulation Header 3-63.2.2 J2, MSP430 JTAG Header 3-63.2.3 J3, SD/MMC/MS Connector 3-73.2.4 J4, CS2 Select 3-83.2.5 J5, SD/MMC/MS Termination Select 3-83.2.6 J6, External RESET Interface 3-93.2.7 J7, USB Host/Client Termination 3-93.2.8 J8, Dual RCA Jack 3-103.2.9 J9, Video Out 3-103.2.10 J10, USB Connector 3-113.2.11 J11, Video In 3-123.2.12 J12, Video In 3-123.2.13 J13, SPDIF Out 3-133.2.14 J14, +5V Input 3-133.2.15 J15, SM/xD Interface 3-143.2.16 J16, Mini PCI VLYNQ Interface 3-153.2.17 J17, FPGA Programming Header 3-163.3 Peripheral Connectors 3-163.3.1 P1, Compact Flash Connector 3-173.3.2 P2, Ethernet Interface 3-183.3.3 P3, Line In/Mic Interface 3-183.3.4 P4, Headphone Out 3-19



Topic Page

3.3.5 P5, Dual Output RCA Jack 3-203.3.6 P6, UART0 3-213.4 JP1, ATA Interface Connector 3-223.5 LEDs 3-233.6 Switches 3-233.6.1 S1, EMU0/1 Select Switch 3-243.6.2 S2, TRSTn Select Switch 3-253.6.3 S3, Processor Configuration/Boot Load Options 3-263.6.4 S4, RESET 3-273.6.5 SW1, Power On/Off 3-273.7 Daughter Card Connectors 3-273.7.1 DC1, EMIF Expansion Connector 3-283.7.2 DC2, GIOV33/Ethernet Connector 3-293.7.3 DC3, SPI, McBSP, I2C Connector 3-303.7.4 DC4, Video Input Connector 3-313.7.5 DC5, Video Output Connector 3-323.7.6 DC6, SD Interface Connector 3-333.7.7 DC7, Power Connector 3-333.8 Test Points 3-34


3-3

3.1 Board Layout

The DM644x EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuitboard which is powered by an external +5 volt only power supply. Figure 3-1 shows thelayout of the DM644x EVM.

Figure 3-1, DM644x EVM, Interfaces Top Side

SW1

J5

J7

J8

J9

J12

J11

J13

J10DC1

J17

J14

J4

P1

J2

S4

DC6

DC2

DC3

DC4

DC5

P3

P4

P5

P2

P6

BHT1

S1

J1

S2

DS10

DC7

S3

DS9

J3

DS1-DS8

J6



Figure 3-2, DM644x EVM, Interfaces, Bottom Side

JP1J15

J16


3-5

3.2 Connectors

The EVM has seventeen (17) connectors providing interfaces to various peripherals.These connectors are described in the following sections.

Table 1: Connectors

Connector Size Function Board Side

J1 20 Emulation Header Top

J2 2x7 MSP430 JTAG Top

J3 24 SD/MMC/MS Top

J4 8 CS2 Select Top

J5 3 SD/MMC/DC Termination Select

Top

J6 2 External RESET Interface

Top

J7 2 USB Host/Client Termination

Top

J8 8 DAC Connector Top

J9 4 Video Out Top

J10 2 USB Top

J11 4 Video In Top

J12 2 Video In Top

J13 2 SPDIF Out Top

J14 2 +5V In Top

J15 46 SM/xD Bottom

J16 2x62 Mini PCI for VLYNQ Bottom

J17 2x5 CPLD ProgrammingHeader (Factory Use)

Top



3.2.1 J1, Emulation Header

The J1 Emulation Header is located on the top side of the board and is used to providean interface to JTAG emulators. The connections for this connector is shown on page33 of the schematics in appendix A. The pinout for the J1 connector is shown in thetable below.

3.2.2 J2, MSP430 JTAG Header

The J2 MSP430 JTAG Header is located on the top side of the board and is used toprovide a programming interface to the MSP430 microcontroller. The connections forthis connector are shown on page 28 of the schematics in appendix A. The pinout forthe J2 connector is shown in the table below.

Table 2: J1, Emulation Header

Pin # Signal Pin # Signal

1 DSP_TMS 2 TRSTn

3 DSP_TDI 4 TDIS

5 VCC_1.8V 6 Key-clipped

7 DSP_TDO 8 GND

9 DSP_RTCK 10 GND

11 CTI_TCK 12 GND

13 CTI_EMU0 14 CTI_EMU1

15 EMULATOR_RSTn 16 GND

17 NC 18 NC

19 NC 20 GND

Table 3: J21, MSP430 JTAG Header


1 430_TDO 2 NC

3 430_TDI 4 MSP430_3V3

5 430_TMS 6 NC

7 430_TCK 8 430_TEST/VPP

9 GND 10

11 NC 12 NC

13 NC 14 NC


3-7

3.2.3 J3, SD/MMC/MS Connector

The J3 SD/MMC/MS connector is located on the top side of the board and is used toprovide an interface to a SD/MMC/MD card. The connections for this connector isshown on page 16 of the schematics in appendix A. The pinout for the J3 connector isshown in the table below.

Table 4: J3, SD/MMC/MS Connector


1 SD_DATA3 2 SD_CMD

3 GND 4 VCC_3.3V

5 SD_CLK 6 GND

7 SD_DATA0 8 SD_DATA1

9 SD_DATA2 10 GND

11 MS.CMD.BS 12 MS.DATA1

13 MS.DATA0 14 MS.DATA2

15 MS.INS/VCC_3.3V

16 MS.DATA3

17 MS.CLK 18 VCC_3.3V

19 GND 20 VCC_3.3V

21 SD/MMC.INS/VCC_3.3V

22 GND

23 GND 24



3.2.4 J4, CS2 Select

The J4 connector is actually a 8 position jumper located on the top side of the boardand is used to select the type of memory that the CS2 signal is routed to. The CS2 canbe routed to the four signals shown in the figure below. Only one (1) device can beselected at a time. To reconfigure this signal, power down the EVM, change the jumper,and then power the board back up. Do NOT change this jumper with the power on. Theconnections for this connector is shown on page 10 of the schematics in appendix A.

3.2.5 J5, SD/MMC/MS Termination Select

The J5 connector is a 3 position jumper located on the top side of the board and is usedto select the termination (ground or VCC_3.3V)for the SD/MMC/MS connector (J3).Either the +3.3V (1-2 position) or Ground (2-3 position) must be selected. Toreconfigure this termination, power down the EVM, change the jumper, and then powerthe board back up. Do NOT change this jumper with the power on. The connections forthis connector are shown on page 16 of the schematics in appendix A.

Table 5: J5, SD/MMC/MS Termination Select

Media Type Position

SD 1-2

MMC 1-2

MS 1-2

MS PRO 2-3

Route EM_CS2 to FLASH_CEz

Route EM_CS2 to SRAM_CEz

Route EM_CS2 to NAND_CEz

Route EM_CS2 to DC_EM_CS2

1

FLASH

SRAM

NAND

DC

J4

Figure 3-3, J4, CS2 Select 1

J5

Figure 3-4, J5, SD/MMC/MS Termination Select

2 31

GN

D

+3.3V


3-9

3.2.6 J6, External RESET Interface

The J6 connector is a 2 position jumper located on the top side of the board and is usedto externally reset the board. This connector is unpopulated as shipped from thefactory. This circuitry parallels the RESET switch, S4. The connections for thisconnector are shown on page 34 of the schematics in appendix A.

3.2.7 J7, USB Host/Client Termination

The J7 connector is a 3 position jumper located on the top side of the board and is usedto select the termination for the USB host/client configuration on USB connector J10. Either the +3.3V (1-2 position) or Ground (2-3 position) must be selected. This signalmust be terminated. To reconfigure this termination, power down the EVM, change thejumper, and then power the board back up. Do NOT change this jumper with the poweron. The connections for this connector are shown on page 21 of the schematics inappendix A.

1

J6

Figure 3-5, J6, External RESET Interface 2

GN

D

PB

SW

_RS

Tz

J7

Figure 3-6, J7, USB Host/Client Termination

2 3

1

GN

D

+3.

3V

US

B_I

D



3.2.8 J8, Dual RCA Jack

The J8 connector is a dual RCA jack providing 4 DAC outputs. Do NOT plug into theseconnectors with the power on. The figure below shows this connector as viewed fromthe card edge. The position of each DAC output is identified. The connections for thisconnector are shown on page 25 of the schematics in appendix A.

3.2.9 J9, Video Out

Connector J9 is a four pin mini din connector which interfaces to an output displaydevice. This connector brings out the DAC B (DAC B-TOP from J8) and DAC C(DAC C-TOP from J8). Do NOT plug into this connector with the power on. The figurebelow shows this connector as viewed from the card edge. The connections for thisconnector are shown on page 25 of the schematics in appendix A.

Table 6: J9, Video Out, Mini Din Connector

Pin # Signal Name

1 Ground

2 Ground

3 DAC_IOUTB

4 DAC_IOUTC

Figure 3-7, J8, Dual RCA Jack

DAC A-BOTTOM

DAC B-TOPDAC C-TOP

DAC D-BOTTOM

Pin 1 Pin 2Pin 3 Pin 4

Figure 3-8, J9, Front View, Mini Din Connector


3-11

3.2.10 J10, USB Connector

Connector J10 is a USB connector. Three different connectors can be mounted atlocation J10. The default connector is USB host. The three tables below show thesignals on each possible connector. The connections for this connector are shown onpage 21 of the schematics in appendix A.

Table 7: J10B, USB Peripheral Connector

Pins Signal

1A USB_VBUS

2B USB_DM

3B USB_DP

4B GND

1,2 USB_SHIELD

Table 8: J10B, Mini A-B USB On The Go Connector

Pins Signal

1AB USB_VBUS

2AB USB_DM

3AB USB_DP

4AB USB_ID

5AB GND

5,6,7,8 USB_SHIELD

Table 9: J10C, USB Host Connector

Pins Signal

1A USB_VBUS

2A USB_DM

3A USB_DP

4A GND

3,4 USB_SHIELD



3.2.11 J11, Video In

Connector J11 is a four pin mini din connector which interfaces to the TVP5146encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146. Do NOT plug into this connector with the power on. The figure below shows thisconnector as viewed from the card edge. The connections for this connector are shownon page 24 of the schematics in appendix A.

3.2.12 J12, Video In

J12 is an RCA jack used as a video input to the TVP5146 encoder. This connectorbrings in a video signal to pin 8 on the TVP5146. Do NOT plug into this connector withthe power on. The figure below shows this connector as viewed from the card edge.The connections for this connector are shown on page 24 of the schematics inappendix A.

Table 10: J11, Video In, Mini Din Connector

Pin # Signal Name

1 GND

2 GND

3 LUMA

4 Chroma

Table 11: J12, Video In, RCA Jack

Pin # Signal Name

1 Pin 8, TVP5146

2 GND

Pin 1 Pin 2Pin 3 Pin 4

Figure 3-9, J11,Front View, Mini Din Connector

Figure 3-10, J12, Video In RCA Jack

Pin 2, Shield (ground)

Pin 1, Signal Input


3-13

3.2.13 J13, SPDIF Out

J12 is an RCA jack used as an output from the DX signal on the DM644x. Thisconnector brings out the SPDIF signal. Do NOT plug into this connector with the poweron. The figure below shows this connector as viewed from the card edge. Theconnections for this connector are shown on page 27 of the schematics in appendix A.

3.2.14 J14, +5V Input

Connector J14 is the input power connector. This connector bring in +5 volts to theEVM. This is 2.5mm. jack. Inside of the jack is tied to On/Off power switch SW1. The other side is tied to ground and LED DS9. The figure below shows this connectoras viewed from the card edge. The connections for this connector are shown on page34 of the schematics in appendix A.

Table 12: J13, SPDIF, RCA Jack

Pin # Signal Name

1 SPDIF Analog output

2 GND

Figure 3-11, J13, SPDIF Out, RCA Jack

Pin 2, Shield (ground)

Pin 1, Signal Output

PC Board

J14+5V

Ground

Front ViewFigure 3-12, J14, +5 Volt Input Connector



3.2.15 J15, SM/xD Interface

Connector J14 provides an interface to SM/xD memory cards. This connector is locatedon the bottom side of the board. Do NOT plug into this connector with the power on.The table below shows the signals on this connector. The connections for thisconnector are shown on page 34 of the schematics in appendix A.

Table 13: J15, SM/xD Interface

ConnectorPin Name

EVMSignal

ConnectorPin Name

EVMSignal

SM.I/01 3V3.EM.D0 SM.LVD NC

SM.I/02 3V3.EM.D1 SM.VCC1 VCC_3.3V

SM.I/03 3V3.EM.D2 SM.VCC2 VCC_3.3V

SM.I/04 3V3.EM.D3 SM.VSS1 GND

SM.I/05 3V3.EM.D4 SM.VSS2 GND

SM.I/06 3V3.EM.D5 xD.VSS2 GND

SM.I/07 3V3.EM.D6 xD.CD xD.CD/VCC_3.3V

SM.I/08 3V3.EM.D7 xD.R/B 3V3.WAIT/BUSY

SM.CLE 3V3.CLE_EM_A2 xD.RE 3V3.READ_OE

SM.ALE 3V3.ALE_EM_A1 xD.CE 3V3.SM_CEz

SM.WE 3V3.WRITE_WE xD.CLE 3V3.CLE_EM_A2

SM.WP GND xD.ALE 3V3.ALE_EM_A1

SM.R/B 3V3.WAIT/BUSY xD.WE 3V3.WRITE_WE

SM.RE 3V3.READ.OE xD.WP SM.Xd.wp

SM.CE 3V3.SM_CEz xD.VSS1 GND

SM.CD SM.CD/VCC_3.3V

xD.I/O0 3V3.EM_D0

SM.OPTION GND xD.I/O1 3V3.EM_D1

SM.26 GND xD.I/O2 3V3.EM_D2

SM.25 GND xD.I/O3 3V3.EM_D3

SM.SENS.1 GND xD.I/O4 3V3.EM_D4

SM.SENS.2 GND xD.I/O5 3V3.EM_D5

xD.VCC1 VCC_3.3V xD.I/O6 3V3.EM_D6

xD.VCC2 VCC_3.3V xD.I/O7 3V3.EM_D7


3-15

3.2.16 J16, Mini PCI VLYNQ Interface

Connector J16 provides an interface to TI supported VNLYNQ cards. This mini-PCIconnector is located on the bottom side of the board. Do NOT plug into this connectorwith the power on. The table below shows the signals on this connector. Theconnections for this connector are shown on page 32 of the schematics in appendix A.

Table 14: J16, VLYNQ Card Interface

Pin # Signal

1,2,7-9,11-14,17,18,EMC1,EMC2,

EMC3,EMC4,93,98,100,112,121,104-110,113,

115-120,122-124

NC

15,20,23,25,26,2732,33,34,35,37,41,

42,45-49,50-62,64-69,71-87,90-92,94-96,

99,101,102,114

GND

10,111 VCC_1.8V

19,28,31,40,63,70, 88,89,97,103

VCC_3.3V

3 SLP_CLK_EN

4 SLP_REG/WAKEUP

5 PM_EN

6 WLAN_INTR

16 SD_CLK/VLYNQ_CLK

21 SD_CMD/VLYNQ_RXD0

22 SD_DATA3/VLYQ_RXD1

24 VLYNQ_SCRUN/SD_DATA0

26 1V8.WLAN_RESET

29 VLYNQ_RXD2

30 VLYNQ_RXD3

36 SD_DATA2/VLYNQ_TXD0

38 VLYNQ_TXD2

39 VLYNQ_TXD3

43 SD_DATA1/VLYNQ_TXD1



3.2.17 J17, FPGA Programming Header

Connector J17 is a 10 pin header that provides a programming interface to theFPGA, U14. This connector is located on the top side of the board. Do NOT plug intothis connector with the power on. The table below shows the signals on this connector.This connector is for factory use only. Reprogramming this CPLD affects thefunctionality of your EVM.

3.3 Peripheral Connectors

Table 15: J17, FPGA Programming Header


1 ISR_TCK 2 GND

3 ISR_TDO 4 VCC_1.8V

5 ISR_TMS 6 NC

7 NC 8 NC

9 ISR_TDI 10 GND

Table 16: Peripheral Connectors

Connector Pins Signal Board Side

P1 50 Compact Flash Top

P2 8 Ethernet Top

P3 4 Line In/Mic Top

P4 2 HP Out Top

P5 4 Line Out Top

P6 8 UART0 Top


3-17

3.3.1 P1, Compact Flash Connector

The P1 connector is located on the top side of the board and is used to provide aninterface to a Compact Flash memory card. This is a 2 x 25 pin male connector. Theconnections for this connector is shown on page 19 of the schematics in appendix A.The pinout for the P1 connector is shown in the table below.

Table 17: P1, Compact Flash Connector


1 GND 2 3V3.EM_D3

3 3V3.EM_D4 4 3V3.EM_D5

5 3V3.EM_D6 6 3V3.EM_D7

7 3V3.CF.ATA_CS0 8 GND

9 GND 10 GND

11 GND 12 GND

13 Pin 3, U10 14 GND

15 GND 16 GND

17 GND 18 3V3.CF.ATA2_EM_A0

19 3V3.CF.ATA1_EM_BA1 20 3V3.CF.ATA0_EM_BA0

21 3V3.EM_D0 22 3V3.EM_D1

23 3V3.EM_D2 24

25 VCC_3.V/3V3.CF_CD2 26 VCC_3.V/3V3.CF_CD1

27 3V3.EM_D11 28 3V3.EM_D12

29 3V3.EM_D13 30 3V3.EM_D14

31 3V3.EM_D15 32 3V3.CF.ATA_CS1

33 NC 34 3V3.CF.READ_OE

35 3V3.CF.WRITE_WE 36 VCC_3.3V

37 3V3.CF.INTRQ_EM_RNW 38 Pin 3, U10

39 GND 40 NC

41 3V3.CF_RESETz 42 3V3.CF.WAIT/BUSY

43 NC 44 VCC_3.3V

45 NC 46 NC

47 3V3.EM_D8 48 3V3.EM_D9

49 3V3.EM_D10 50 GND



3.3.2 P2, Ethernet Interface

The P2 connector is located on the top side of the board and is used to provide anEthernet interface. This is a standard RJ-45 connector. The connections for thisconnector is shown on page 22 of the schematics in appendix A. The pinout for the P2connector is shown in the table below.

3.3.3 P3, Line In/Mic Interface

The P2 connector is provides a stereo input (lower) and microphone input (upper) tothe TVL320AIC33 on the EVM. This connector is located on the top side of the board. A view of the connector from the card edge is shown in the figure below. The signalspresent on this connector are defined in the following table. The connections for thisconnector is shown on page 26 of the schematics in appendix A.

Table 18: P2, Ethernet Interface


1 LXT_TDP 2 LXT_TDM

3 LXT_RDP 4 LXT_TDCT

5 NC 6 LXT_RDM

7 NC 8 GND

9 VCC_3.3V 10 LED1-

11 VCC_3.3V 12 LINKLED-

Table 19: P3, Line In/Mic Interface

Pin # Signal Input

1 Isolated Ground Mic

2 MIC3L/MIC3R Mic

3 MIC3L/MIC3R Mic

4 Isolated Ground Line In

5 LINE1R+/LINE2R+ Line In

6 LINE1L+/LINE2L+ Line In

Figure 3-13, P3, Line In/Mic Interface

MIC

Stereo Line In

(upper)

(lower)


3-19

3.3.4 P4, Headphone Out

The P4 connector is a stereo headphone output from the TVL320AIC33 on the EVM.This connector is located on the top side of the board. A view of the connector from thecard edge is shown in the figure below. The signals present on this connector aredefined in the following table. The connections for this connector is shown on page 26of the schematics in appendix A.

Table 20: P4, Headphone Out Interface

Pin # Signal

1 Isolated Ground

2 HPLOUT

3 HPROUT

4 NC

Figure 3-14, P4, Headphone Out Interface

Stereo Line Out



3.3.5 P5, Dual Output RCA Jack

The P5 connector is a dual output RCA jack bringing audio from the TVL320AIC33 onthe EVM. This connector is located on the top side of the board. A view of theconnector from the card edge is shown in the figure below. The signals present on thisconnector are defined in the following table. The connections for this connector isshown on page 26 of the schematics in appendix A.

Table 21: P5, Dual Output RCA Jack

Pin # Signal

1 Isolated Ground

2 LEFT_LO+

3 RIGHT_LO+

Figure 3-15, P5, Dual Output RCA Jack

WHITE

RED


3-21

3.3.6 P6, UART0

The P6 connector is a 9 pin make D-connector which provides a UART interface to theEVM. This connector interfaces to the MAX 3221 RS-232 line driver (U64) and islocated on the top side of the board. A view of the connector from the card edge isshown in the figure below. The signals present on this connector are defined in thefollowing table. The connections for this connector is shown on page 20 of theschematics in appendix A.

The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a standard dual row to DB-9 connector interface used on personalcomputers.

Table 22: P6, UART0 Pinout

Pin # Signal Name Direction

1 NC N/A

2 S_A_RXD In

3 S_A_TXD Out

4 NC N/A

5 GND N/A

6 NC N/A

7 S_A_TXD Out

8 S_A_TXD Out

9 NC N/A

10,11 Earth Ground N/A

9

5 4 3 2 1

8 7 6

Figure 3-16, P6, DB9 Male Connector



3.4 JP1, ATA Interface Connector

The JP1 connector is located on the bottom side of the board and is used to provide anATA interface to a hard disk drive. This is a 2 x 22 pin male connector. The connectionsfor this connector is shown on page 18 of the schematics in appendix A. The pinout forthe JP1 connector is shown in the table below.

Table 23: JP1, ATA Interface


1 ATA RESETn 2 GND

3 ATA.DD7 4 ATA.DD8

5 ATA.DD6 6 ATA.DD9

7 ATA.DD5 8 ATA.DD10






19 GND 20 NC

21 ATA.DMARQ 22 GND

23 ATA.DIOW 24 GND

25 ATA.DIOR 26 GND

27 ATA.IORDY 28 ATA_CSEL, TP34

29 ATA.DMACK 30 GND

31 ATA.INTRQ 32 GND

33 ATA.DA1 34 TP33

35 ATA.DA0 36 ATA.DA2

37 ATA.CS0 38 ATA.CS1

39 ATA.DASPn 40 GND

41 VCC_5V 42 VCC_5V

43 GND 44 NC


3-23

3.5 LEDs

The EVM has ten (10) LEDs which are located on the top side of the board. Eight of

these LEDs (DS1-8) are under user control and addressed over the I2C bus. One LED(DS9) indicates the presence of +5 volts on the board. The remaining LED (DS10)indicates a hard disk drive is plugged into the EVM. Additional information regardingthe LEDs are shown in the table below.

3.6 Switches

The EVM has five (5) switches. The function of these switches are shown in the tablebelow.

Table 24: LEDs

LED # Use ColorSchematic

Page

DS1 User Defined Green 27








DS9 +5V Green 34

DS10 +3.3V Red 18

Table 25: Switches

Switch Function TypeBoard Side

SchematicPage

S1 EMU0/1 Selection DIP Top 33

S2 TRSTn Select DIP Top 33

S3Boot

Configuration Options

DIPTop 10

S4 RESET Push button Top 34

SW1 Power On/Off Toggle Top 34



3.6.1 S1, EMU0/1 Select Switch

S1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0 andEMU1 pins on the processor. The connections for this switch are shown on page 33of the schematics in appendix A. A view of the switch is shown in the figure below. Theselection options with this switch are in the table below.

* is the factory shipped configuration

Table 26: S1, EMU0/1 Select

State at ResetEMU0 EMU1

Function

L L Emulation Debug ARM JTAG Enabled

L H Not Defined

H L Not Defined

H H Emulation Debug *Both ARM & DSP JTAG Enabled

Figure 3-17, S1, EMU0/1 Select Switch EMU0

EMU1

H

H

L

L

S1


3-25

3.6.2 S2, TRSTn Select Switch

S2 is a 2 position DIP switch providing 4 options in selecting the state of the TRSTsignal for JTAG emulation. The connections for this switch are shown on page 33of the schematics in appendix A. A view of the switch is shown in the figure below. Theselection options with this switch are in the table below.

* is the factory shipped configuration

Table 27: S2, TRST Select

Switch Position Function

A Right TRST Pull up

A Left TRST Pull down *

B Right TRST low on power up Reset

B Left Delay via capacitor(capacitor not populated) *

Figure 3-18, S2, TRST Select TRSTn

TRSTn

S2A

B



3.6.3 S3, Processor Configuration/Boot Load Options

S2 is a 10 position DIP switch providing 9 options in selecting the processorconfiguration and boot load modes. when a switch is in the “ON” position the specificfunction is selected. The connections for this switch are shown on page 10 of theschematics in appendix A. A view of the switch is shown in the figure below. Theselection options with this switch are in the table below.

Table 28: S3, Processor Configuration/Boot Load Options

Position Name Function

1 COUT0 Bootmode 0

2 COUT1 Bootmode 1

3 COUT2 Bus width: 0=8 bit, 1=16 bit

4 COUT3 0=ARM boots DSP,1=C64xx self boots

5 YOUT4

6 YOUT3

7 YOUT2

8 YOUT1

9 YOUT0

10 USER For Demos

Figure 3-19, S3, Processor Configuration/

COUT0S3

ON1

23

45

67

89

10

COUT1

COUT2

COUT3

YOUT4

YOUT3

YOUT2

YOUT1

YOUT0

SPARE

Boot Load Options


3-27

3.6.4 S4, RESET

Switch S4 is a push button rest switch that will RESET the processor. This switch is inparallel with J6. The connections for this switch are shown on page 34 of theschematics in appendix A.

3.6.5 SW1, Power On/Off

Switch S1 is a toggle switch that provides power to the EVM. The connections for thisswitch are shown on page 34 of the schematics in appendix A.

3.7 Daughter Card Connectors

The EVM has seven connectors that are available for daughter card connections.These connectors make many of the signals on the EVM available to be used byexternal logic. The signals on each of the connectors are described in the followingtables. The table below lists the connectors.

Table 29: Daughter Card Connectors

Connector Size FunctionBoard Side

SchematicPage

DC1 2x35 EMIF Top 29

DC2 2x20 GIOV33/Ethernet Top 31

DC3 2x15 SPI, McBSP, I2C Top 31

DC4 2x20 Video In Top 30

DC5 2x25 Video Out Top 30

DC6 2x5 SD Interface Top 31

DC7 2x5 Power Top 35



3.7.1 DC1, EMIF Expansion Connector

Table 30: DC1, EMIF Expansion Connector


1 B.EM_A21 2 B.EM_A20

3 B.EM_A19 4 B.EM_A18

5 B.EM_A17 6 B.EM_A16

7 B.EM_A15 8 B.EM_A14

9 GND 10 GND

11 B.EM_A13 12 B.EM_A12

13 B.EM_A11 14 B.EM_A10

15 B.EM_A9 16 B.EM_A8

17 B.EM_A7 18 B.EM_A6

19 GND 20 GND

21 B.EM_A5 22 B.EM_A4

23 B.EM_A3 24 CLE_EM_A4

25 B.EM_A1 26 ATA2_EM_A0

27 GND 28 GND

29 ATA_CS1 30 ATA_CS0

31 ATA1_EM_BA1 32 ATA0_EM_BA0

33 WRITE_WE 34 READ_OE

35 WAIT/BUSY 36 INTRQ_EM_RNW

37 GND 38 GND

39 EM_D15 40 EM_D14

41 EM_D13 42 EM_D12

43 EM_D11 44 EM_D10

45 GND 46 GND

47 EM_D9 48 EM_D8

49 EM_D7 50 EM_D6

51 EM_D5 52 EM_D4

53 GND 54 GND

55 EM_D3 56 EM_D2

57 EM_D1 58 EM_D0

59 EM_CS3 60 DC_EM_CS2

61 1.8V.SYS_RESETz 62 CLKOUT0

63 GND 64 GND

65 VCC_3.3V 66 VCC_3.3V

67 GND 68 GND

69 VCC_5V 70 VCC_1.8V


3-29

3.7.2 DC2, GIOV33/Ethernet Connector

Table 31: DC2, GIOV33/Ethernet Connector


1 GND 2 GND

3 GIOV33_0 4 GIOV33_1

5 GIOV33_2 6 GIOV33_3

7 GIOV33_4 8 GIOV33_5

9 GND 10 GND

11 GIOV33_6 12 GIOV33_7

13 GIOV33_8 14 GIOV33_9

15 GIOV33_10 16 GIOV33_11

17 GND 18 GND

19 GIOV33_12 20 GIOV33_13

21 GIOV33_14 22 GIOV33_15

23 GIOV33_16 24 GND

25 GND 26 3V3.SYS_RESETz

27 ENET_ENABLEz 28 GND

29 VCC_1.8V 30 3V3.UART_RXD1

31 VCC_1.8V 32 3V3.UART_TXD1

33 GND 34 GND

35 VCC_3.3V 36 VCC_3.3V

37 VCC_5V 38 VCC_5V

39 GND 40 GND



3.7.3 DC3, SPI, McBSP, I2C Connector

Table 32: DC3, SPI, McBSP, I2C Connector


1 SPI_EN1 2 SPI_EN0

3 SPI_DI 4 SPI_DO

5 SPI_CLK 6 TIMER_IN_DC3

7 GND 8 GND

9 DR 10 DX

11 CLKR 12 CLKX

13 FSR 14 FSX

15 GND 16 GND

17 1.8V.SYS_RESETz 18 1.8V.I2C_CLK

19 McBSP_EN 20 1.8V.I2C_DATA

21 AUDIO_CLK 22 GND

23 GND 24 1.8V_DC3_PCLK

25 VCC_3.3V 26 VCC_3.3V

27 GND 28 GND

29 VCC_5V 30 VCC_1.8V


3-31

3.7.4 DC4, Video Input Connector

Table 33: DC4, Video Input Connector


1 1.8V.SYS_RESETz 2 CAPTURE_EN

3 GND 4 GND

5 GIO1 6 GIO4

7 GND 8 GND

9 PWM1 10 PWM2

11 GND 12 GND

13 Y10 14 Y11

15 Y12 16 Y13

17 Y14 18 Y15

19 Y16 20 Y15

21 GND 22 GND

23 GND 24 HD

25 PCLK/1V8.DC_PCLK 26 VD

27 GND 28 GND

29 CI0 30 CI1

31 CI2 32 CI3

33 CI4 34 CI5

35 CI6 36 CI7

37 GND 38 GND

39 1V8.I2C_CLK 40 1V8.I2C_DATA

41 VCC_1.8V 42 VCC_1.8V

43 GND 44 GND

45 VCC_3.3V 46 VCC_3.3V

47 GND 48 GND

49 VCC_5V 50 VCC_5V



3.7.5 DC5, Video Output Connector

Table 34: DC5, Video Output Connector


1 GIO0 2 GIO2

3 GIO3 4 GIO5

5 GIO6 6 GIO38

7 GND 8 GND

9 COUT0 10 COUT1

11 COUT2 12 COUT3

13 COUT4 14 COUT5

15 COUT6 16 COUT7

17 GND 18 GND

19 VPBECLK/VID_CLK 20 HSYNC

21 GND 22 GND

23 VCLK 24 VSYNC

25 GND 26 GND

27 YOUT0 28 YOUT1

29 YOUT2 30 YOUT3

31 YOUT4 32 YOUT5

33 YOUT6 34 YOUT7

35 GND 36 GND

37 1.8V.I2C_CLK 38 1.8V.SYS_RESETz

39 1.8V.I2C_DATA 40 GND

41 VCC_1.8V 42 VCC_1.8V

43 GND 44 GND

45 VCC_3.3V 46 VCC_3.3V

47 GND 48 GND

49 VCC_5V 50 VCC_5V


3-33

3.7.6 DC6, SD Interface Connector

3.7.7 DC7, Power Connector

Table 35: DC6, SD Interface Connector


1 SD_CLK 2 SD_CMD

3 GND 4 GND



9 GND 10 GND

Table 36: DC7, Power Connector


1 VDDIMX_EN 2 GND

3 DSP_CORE_SUPPLY 4 DSP_CORE_SUPPLY

5 GND 6 GND

7 VCC_1.8V 8 VCC_1.8V

9 GND 10 GND



3.8 Test Points

The EVM has 63 test points. All test points appear on the top of the board. Thefollowing figure identifies the position of each test point. the next table list each testpoint and the signal appearing on that test point.

Figure 3-20, DM644x EVM, Test Points

TP1

TP9

TP8

TP7

TP6

TP3

TP5

TP2

TP4

TP10

TP11

TP19

TP20

TP21

TP22

TP14

TP25

TP15

TP16

TP17

TP26

TP18

TP27

TP28

TP29

TP31

TP30

TP33

TP35

TP37

TP32

TP34

TP42

TP36

TP40 TP38TP39

TP41

TP43

TP46

TP49

TP44

TP45TP47

TP48

TP53

TP54

TP55

TP56

TP57

TP60

TP63

TP58

TP59

TP61

TP62

TP65

TP66

TP69

TP64

TP67

TP68

TP70


3-35

Table 37: DM644x EVM Test Points

Test Point #

SignalSchematic

PageTest Point

#Signal

SchematicPage

TP1 GND 4,34 TP36

TP2 GND 34 TP37 U27,U38,PIN 4,VCC_3.3V 35

TP3 GND 34 TP38 GND 4

TP4 U4,P24,P1.3/TA2 28 TP39 U28A,DDR_VSS.DLLVCC_1.8V

4

TP5 VCC_5V 34 TP40 VCC_1.8V 4

TP6 GND 4 TP41 DSP_CORE_VDD 9

TP7 U28A,DDR_AMUX.DLL TP42 U28D,VDD.10DSP_CORE_VDD

9

TP8 U28E,PLLPWR18VCC_1.8V

8 TP43 DSP_CORE_VDD 35

TP9 GND 8 TP44

TP10 U28E,AMUX 8 TP45 GND

TP11 U28D,VDDS1.14VCC_1.8V

9 TP46 U28H,USB_VDDA1P8PHY

VCC_1.8V

7

TP14 +3.3V 34 TP47 VCC_1.8V 7

TP15 TP48 VCC_3.3V 7

TP16 3V3_PWR_OK 34 TP49 U28H,USB_VDDA3P3PHY

VCC_3.3V

7

TP17 GND 4 TP53 VCC_1.8V 5

TP18 U28E,APLLREFVDSP_CORE_VDD

8 TP54 U28G,VDDA18VVCC_1.8V

5

TP19 VCC_1.8V 8 TP55 U28G,VDDA11DSP_CORE_VDD

5

TP20 DSP_CORE_VDD 8 TP56 U51,Pin 36 24

TP21 VCC_1.8V 9 TP57 U51,Pin 37 24

TP22 U28D,VDDSHV.4VCC_3.3V

9 TP58 U58,PIN 64,MDINT 22

TP25 DSP_CORE_VDDIMX 35 TP59

TP26 VCC_1.8V 35 TP60

TP27 GND 34 TP61 DSP_CORE_VDD 5

TP28 JP1,Pin 28, ATA_CSEL 18 TP62 U51,Pin 30 24

TP29 TP63 U52,A8,MPF2 26

TP30 U28D,VDDIMX.11DSP_CORE_VDDIMX

9 TP64 U52,A9,MPF3 26

TP31 DSP_CORE_VDDIMX 9 TP65 U52,C8,SCL 26

TP32 VCC_3.3V 9 TP66 U28I,GIO45/PWM0VCC_1.8V

5

TP33 JP1, Pin 34 18 TP67 VIN, U54,PIN 3 5

TP34 TP68 GND 34

TP35 TP69 U52,J9,GPIO1 26

TP70 GND 34

A-1

Appendix A

Schematics

This appendix contains the schematics for the DaVinci EVM.


A-2 DM644x EVM Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

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OR

evi

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Sh

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of

Titl

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Pa

ge

Co

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nts

:

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SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

Mo

nda

y, M

arc

h 0

6,

200

61

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

Titl

e B

lock

SCHEMATIC

CONTENTS

01 DAVINCI EVM TITLE SHEET

02 DAVINCI EVM BLOCK DIAGRAM

03 DAVINCI EMIF INTERFACE

04 DAVINCI DDR INTERFACE

05 DAVINCI VIDEO INTERFACE

06 DAVINCI I/O INTERFACE

07 DAVINCI USB & SD/MMC/MS CONTROLLER

08 DAVINCI EMULATION & CLOCKS

09 DAVINCI POWER PINS

10 DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS

11 DDR2 MEMORY

12 SRAM/NAND FLASH

13 NOR FLASH

14 EMIF LEVEL SHIFTER

15 EMIF CPLD MULTIPLEXER

16 SD/MMC/MS CONNECTOR

17 SM/xD CONNECTOR

18 ATA INTERFACE

19 COMPACT FLASH CONNECTOR

20 RS232 INTERFACE

21 USB 2.0 INTERFACE

22 ETHERNET INTERFACE

23 TVP5146 LEVEL SHIFTER

24 TVP5416 VIDEO DECODER

25 VIDEO OUT

26 AIC33 AUDIO INTERFACE

27 SPDIF OUTPUTS & USER LEDS

28 MSP430 & IR INTERFACE

29 EMIF EXPANSION CONNECTOR

30 VIDEO INPUT/OUTPUT CONNECTORS

31 EMAC/GIO & McBSP/SPI & SD CONNECTORS

32 VLYNQ CONNECTOR

33 DAVINCI EMULATION HEADER

34 POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC

35 POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONNECTOR

REV

ENGR

2REVISION STATUS OF SHEETS

111

SH

DATE

14

12

13

DATE

ENGR-MGR

MFG

7

DWN

DATE

8

DATE

10

SH

DATE

CHK

RLSE

APPLICATION

REV

35

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

4

15

AA

AB

BA

A

BD

AA

A

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

02/17/2005

02/17/2005

16

17

18

19

20

21

22

23

24

25

02/17/2005

02/17/2005

03/01/2004

02/17/2005

02/17/2005

REV

SH

BB

AA

A

BB

B

DB

B

AA

AA

A

AA

DA

26

27

28

29

30

AA

31

32

33

34

AInitial schematic ready

for layout - Alpha Release

DESCRIPTION

REV

APPROVED

DATE

02/17/05

RRP

4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS

OTHERWISE NOTED. THEY ARE SHOWN

ON THE PAGE WITH THE INTEGRATED

CIRCUITS THEY SHOULD BE PLACED NEAR.

NOTES, UNLESS OTHERWISE SPECIFIED:

1. RESISTANCE VALUES IN OHMS.

2. CAPACTITANCE VALUES IN MICROFARADS.

3. REFERENCE DESIGNATORS USED:

5. OBSERVE THE FOLLOWING LAYOUT NOTES:

1. TOP - SIGNAL ROUTING

2. GROUND PLANE

3. INNER1 - SIGNAL ROUTING

4. VCC3 PLANE (3.3V BOARD)



7. VCC PLANE 2


9. GROUND PLANE

10. BOTTOM - SIGNAL ROUTING

6.

BOARD

PROPERTIES

B1. General layers 50 +/- 5 OHM MATCHED IMPEDANCE

C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING

D. INNER LAYERS 1.0 OZ CU

E. FR4 BOARD MATERIAL

F. MINIMUM TRACE WIDTH/SPACING 4 MILS

G. MINIMUM VIA SIZE 10/19 MIL

H. LAYER STACKUP:

A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE

B2. USB layer

90 ohm differential

35

D

BBeta Release

RRP

09/27/05

I2CADDRESS TABLE

IO EXPANDER 0

IO EXPANDER 1

IO EXPANDER 2

I2C ROM

AIC33

TVP5146

MSP430

0x50

BASE

0x1B

0x5D

0x23

0x38

(LED)

0x39

(PLL/USER_SW)

0x3A

(USB/CD_RESET)

SHEET

26

24

28

28

28

28

6

CGamma

Release

RRP

10/28/05

DProduction Release

02/18/06

RRP


A-3

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

52

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

BL

OC

K D

IAG

RA

M

DaVinci

SH:3-9

DDR2 IF

SH:4

SH:12

NAND Flash (64MB)

SH:13

NOR Flash (16MB)

SH:12

SRAM (4MB)

SH:14

Switch

SH:32

VLYNQ Connector S

H:16

SD/MMC/MS Connector

SH:25

(4) DAC Video Outputs

SH:30

DC #5 Connector

SH:31

DC #3 Connector S

H:27

SPDIF Outputs

SH:7

Switch

SH:26

Stereo Codec

(AIC33)

SH:31

DC #3 Connector

SH:30

DC #4 Connector

SH:5

VCXO/PLL

(Audio & Video

Clock Generation)

SH:17

SMC/xD Connector

SH:19

Compact Flash Connector

SH:14,15

1.8V to 3.3V

Level Shifters

SH:18

ATA Connector

SH:33

Emulator Header

SH:29

DC #1 Connector

SH:11

DDR2 SDRAM (256MB)

SH:21

USB 2.0 IF

SH:22

Ethernet IF

SH:30

DC #4 Connector

SH:31

DC #2 Connector

SH:22

Switch

SH:6

EEPROM

SH:27

(8) LEDs

SH:23

Level Shifter

& Switch

SH:20

UART

(Debug Term)

SH:24

Video Decoder

(TVP5146)

SH:28

MSP430

IR/RTC/SC

Emulator

SH:8

USB 2.0

SH:7

Image In

SH:5

UART1

SH:3

I2C SH:6

SH:28

Resistor

Pop Option

SH:6

EMAC/

GPIOs

UART0

SH:6

SH:31

DC #6 Connector

Config Control &

EM_CS2 Select

SH:10

Power Supply (3.3V)

& System Reset Logic

SH:34

Power Supply (1.8V & DSP Core)

& DC #7 Connector

SH:35

EMIF/VLYNQ

SH:3

SD/MMC/MS

SH:7

(4) DACs

SH:5

Video Out

SH:5

PWM0

SH:5

Timer In

SH:8

PWM [2:1]

SH:5

SPI SH:6

McBSP

SH:7

Power Pins

SH:9

SH:8

Crystal/Osc

SH:8

PLLs



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_D

15

EM

_D

11

EM

_D

13

EM

_D

9

EM

_D

5

EM

_D

7

EM

_D

3

EM

_D

1

EM

_A21

EM

_A16

EM

_A18

EM

_A20

EM

_A14

EM

_A8

EM

_A6

EM

_A10

EM

_A4

EM

_A12

EM

_A19

EM

_A17

EM

_A15

EM

_A13

EM

_A11

EM

_A9

EM

_A7

EM

_A5

EM

_A3

EM

_D

14

EM

_D

12

EM

_D

8

EM

_D

4

EM

_D

6

EM

_D

2

EM

_D

0

EM

_D

10

CP

U.V

LY

NQ

_C

LK

VL

YN

Q_

SC

RU

N

VL

YN

Q_

CL

K

CP

U.V

LY

NQ

_C

LK

VC

C_

1.8

V

VC

C_

1.8

V

EM

_D

[0:1

5]1

2,1

3,1

4,29

EM

_A

[3:2

1]1

2,1

3,1

4,2

9

CLE

_EM

_A2

12

,13,

15,2

9A

LE_E

M_

A1

12

,13

,15

,29

AT

A2_

EM

_A0

12

,13

,15,

29A

TA

1_E

M_B

A1

12,

13

,15

,29

AT

A_C

S0

15,2

9A

TA

_CS

115

,29

RE

AD

_O

E12

,13

,15,

29

WR

ITE

_WE

12

,13

,15,

29

EM

_C

S2

10,1

5E

M_

CS

329

AT

A0_

EM

_BA

01

5,29

INT

RQ

_E

M_R

NW

15

,29

UA

RT

_T

XD

1/D

MA

CK

15

VL

YN

Q_

CL

K32

VL

YN

Q_

SC

RU

N32

WA

IT/B

US

Y1

5,2

9

INT

RQ

_E

M_

RN

W1

5,2

9

UA

RT

_RX

D1/

DM

AR

Q15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

53

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

EM

IF I

NT

ER

FA

CE

R18

022

R16

822

U2

8B

DA

VIN

CI-

BG

A_

24

EM

_D14

/HD

14H

5E

M_D

13/H

D13

F2

EM

_D12

/HD

12D

1E

M_D

11/H

D11

G4

EM

_D10

/HD

10G

5E

M_D

09/H

D09

E2

EM

_D15

/HD

15E

1

EM

_D08

/HD

08F

3

EM

_D07

/HD

07C

1E

M_D

06/H

D06

F4

EM

_D05

/HD

05D

2E

M_D

04/H

D04

E4

EM

_D03

/HD

03E

3E

M_D

02/H

D02

F5

EM

_D01

/HD

01D

3E

M_D

00/H

D00

E5

INT

RQ

_EM

_RN

W/H

RN

WG

3

WA

IT_B

US

YN

/HR

DY

NF

1

RE

AD

_OE

/HD

S1N

H4

WR

ITE

_WE

/HD

S2N

G2

UA

RT

_TX

D1/

DM

AC

KH

3U

AR

T_R

XD

1/D

MA

RQ

G1

GIO

8/V

LYN

Q_C

LK/E

M_C

S5

T1

EM

_CS

2/H

CS

NC

2E

M_C

S3/

HA

SN

B1

GIO

9/V

LYN

Q_S

CR

UN

/EM

_CS

4T

2

EM

_BA

1/A

TA

1_B

A1/

GIO

52H

2

CLE

_EM

_A2/

HC

NT

LAJ1

GIO

28/E

M_A

3K

2G

IO27

/EM

_A4

K4

GIO

26/E

M_A

5K

3

GIO

25/E

M_A

6N

1G

IO24

/EM

_A7

N2

GIO

23/E

M_A

8N

3G

IO22

/EM

_A9

M4

GIO

21/E

M_A

10P

1G

IO20

/EM

_A11

P2

GIO

/19E

M_A

12R

1G

IO18

/EM

_A13

N4

GIO

17/V

LYN

Q_R

XD

3/E

M_A

14P

4G

IO16

/VLY

NQ

_TX

D3/

EM

_A15

P3

GIO

15/V

LYN

Q_R

XD

2/E

M_A

16R

5G

IO14

/VLY

NQ

_TX

D2/

EM

_A17

R2

GIO

13/V

LYN

Q_R

XD

1/E

M_A

18P

5G

IO12

/VLY

NQ

_TX

D1/

EM

_A19

R4

GIO

11/V

LYN

Q_R

XD

0/E

M_A

20R

3

EM

_BA

0/A

TA

0_B

A0/

HIN

TN

J3

AT

A_C

S0/

GIO

50J5

AT

A_C

S1/

GIO

51H

1

GIO

10/V

LYN

Q_T

XD

0/E

M_A

21T

3

ALE

_EM

_A1/

HH

WIL

J2

EM

_A0/

AT

A2_

EM

_A0/

GIO

53/H

CN

TLB

J4

RN

8R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

R17

322

R17

022

R1

71

243

C1

70

NO

-PO

P

R17

222

R17

422

R16

722

RN

7R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

R20

322

RN

3R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

RN

2R

PA

CK

8-1

01 2 3 4 5 6 7 8

910111213141516

R16

922

R1

611

K

C1

71

NO

-PO

P

R17

922

R3

94N

O-P

OP

R17

522

RN

9R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516


A-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

D8

DD

R_

D1

2

DD

R_

D1

4

DD

R_

D6

DD

R_

D2

5

DD

R_

D1

6

DD

R_

D2

6

DD

R_

D1

9

DD

R_

D2

1D

DR

_D

20

DD

R_

D2

2D

DR

_D

23

DD

R_

D2

8

DD

R_

D3

1

DD

R_

D2

7

DD

R_

D1

7

DD

R_

D2

9

DD

R_

D0

DD

R_

D1

DD

R_

D2

DD

R_

D3

DD

R_

D4

DD

R_

D5

DD

R_

D7

DD

R_

D9

DD

R_

D1

0D

DR

_D

11

DD

R_

D1

3

DD

R_

D1

5

DD

R_

D1

8

DD

R_

D2

4

DD

R_

D3

0

DD

R_

A0

DD

R_

A1

DD

R_

A2

DD

R_

A3

DD

R_

A4

DD

R_

A5

DD

R_

A6

DD

R_

A7

DD

R_

A8

DD

R_

A9

DD

R_

A1

0D

DR

_A

11

DD

R_

A1

2D

DR

_B

S0

0D

DR

_B

S0

1D

DR

_B

S0

2 DD

R_

CS

DD

R_

CL

KD

DR

_C

LK

_N

DD

R_

DQ

S0

DD

R_

DQ

M0

DD

R_

DQ

S1

DD

R_

DQ

S2

DD

R_

DQ

S3

DD

R_

DQ

M3

BD

DR

_A

0

BD

DR

_A

3B

DD

R_

A4

BD

DR

_A

5B

DD

R_

A6

BD

DR

_A

7

BD

DR

_B

S0

2B

DD

R_

BS

01

BD

DR

_B

S0

0

BD

DR

_A

8B

DD

R_

A9

BD

DR

_A

10

BD

DR

_A

11

BD

DR

_A

12

BD

DR

_D

QS

0B

DD

R_

DQ

S1

BD

DR

_D

QS

2B

DD

R_

DQ

S3

BD

DR

_D

QM

0B

DD

R_

DQ

M1

BD

DR

_D

QM

2B

DD

R_

DQ

M3

BD

DR

_C

S

BD

DR

_C

LK

BD

DR

_C

LK

_N

BD

DR

_C

KE

DD

R_

DQ

M2

DD

R_

DQ

M1

VR

EF

_S

TL

BD

DR

_A

1B

DD

R_

A2

DD

R_

RA

S

DD

R_

CK

ED

DR

_W

E

DD

R_

CA

S

BD

DR

_W

E

BD

DR

_R

AS

BD

DR

_C

AS

VC

C_

1.8

V

DD

R_

D[0

:31

]11

DD

R_

A[0

:12

]1

1

DD

R_

DQ

M0

11

DD

R_

DQ

S2

11

DD

R_

CA

S11

DD

R_

CL

K11

DD

R_

CS

11

DD

R_

CL

K_

N11

DD

R_W

E1

1D

DR

_R

AS

11

DD

R_

CK

E11

DD

R_

DQ

S3

11

DD

R_

DQ

S1

11D

DR

_D

QS

011

DD

R_

DQ

M3

11

DD

R_

BS

02

11D

DR

_B

S0

111

DD

R_

BS

00

11

DD

R_

DQ

M1

11

DD

R_

DQ

M2

11

VR

EF

_ST

L11

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

54

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

DD

R I

NT

ER

FA

CE

SURFACE MOUNT TEST POINT PADS

USED FOR VERIFYING DDR TIMINGS

ROUTE CLOCK DIFFERENTIAL WITH 15 MIL SPACING BETWEEN

PLACE RESISTOR BY DATA TERMINATOR PINS

BALANCE

LINE LENGTHS WITH DATA BYTES LENGTHS

RN

17

RP

AC

K4

-47

12345 6 7 8

R5

14

7

R53

0.22

R2

064

7

R3

34

7

TP

71

R1

824

7

C1

890

.1u

F

TP

171

RN

13R

PA

CK

4-4

7

12345 6 7 8

R1

814

7

R2

18

0

TP

381

C1

901

uF

L10

BLM

21P

G2

21S

N1D

12

R2

214

7

TP

451

C21

60

.22

uF

RN

12

RP

AC

K4

-47

12345 6 7 8

RN

10

RP

AC

K4

-47

12345 6 7 8

R2

19

200

TP

40 1

U2

8A

DA

VIN

CI-

BG

A_

24

DD

R_A

00W

13

DD

R_A

01U

13

DD

R_A

02V

13

DD

R_A

03U

12

DD

R_A

04V

12

DD

R_A

05W

12

DD

R_A

06W

11

DD

R_A

07V

11

DD

R_A

08V

10

DD

R_A

09U

11

DD

R_A

10U

10

DD

R_A

11W

10

DD

R_A

12W

9

DD

R_B

S00

U8

DD

R_C

ST

9

DD

R_C

LK_N

W8

DD

R_W

ET

8

DD

R_C

LKW

7

DD

R_C

KE

V8

DD

R_Z

PT

13

DD

R_Z

NT

12

DD

R_V

SS

.DLL

T11

DD

R_V

DD

.DLL

T10

DD

R_C

AS

T7

DD

R_R

AS

U7

DD

R_D

00U

1

DD

R_D

01U

2

DD

R_D

02V

1

DD

R_D

03V

2

DD

R_D

04W

2

DD

R_D

05U

3

DD

R_D

06V

3

DD

R_D

07W

3

DD

R_D

08V

4

DD

R_D

09W

4

DD

R_D

010

U5

DD

R_D

11V

5

DD

R_D

12W

5

DD

R_D

13V

6

DD

R_D

14W

6

DD

R_D

15V

7

DD

R_D

16W

14

DD

R_D

17V

14

DD

R_D

18W

15

DD

R_D

19V

15

DD

R_D

20U

15

DD

R_D

21W

16

DD

R_D

22V

16

DD

R_D

23T

17

DD

R_D

24V

17

DD

R_D

25U

17

DD

R_D

26U

18

DD

R_D

27W

17

DD

R_D

28V

18

DD

R_D

29W

18

DD

R_D

30V

19

DD

R_D

31U

19

DD

R_B

S01

V9

DD

R_B

S02

U9

DD

R_A

MU

X.D

LLR

8

DD

R_D

QS

0U

4

DD

R_D

QS

1U

6

DD

R_D

QM

0T

4

DD

R_D

QM

1T

6

DD

R_D

QS

3U

16D

DR

_DQ

S2

U14

DD

R_D

QM

2T

14

DD

R_D

QM

3T

16

VR

EF

ST

LT

15

TP

39 1

TP

61

R2

054

7

RN

11

RP

AC

K4

-47

12345 6 7 8

R5

24

7

R3

24

7

R4

14

7

R2

204

7

R2

04

200



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VR

EF

_0

.5V

VR

EF

_1

.24

V

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

1.8

V

DS

P_

CO

RE

_V

DD

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3.3

V

VC

C_

3.3

V

CO

UT

01

0,3

0

CO

UT

21

0,3

0

CO

UT

430

YO

UT

01

0,3

0

YO

UT

21

0,3

0

VS

YN

C30

CO

UT

11

0,3

0

CO

UT

31

0,3

0

HS

YN

C30

YO

UT

11

0,3

0

YO

UT

31

0,3

0

CO

UT

630

CO

UT

730

CO

UT

530

YO

UT

530

YO

UT

41

0,3

0

YO

UT

630

YO

UT

730

VP

BE

CLK

30

VC

LK

30

PW

M1

30

PW

M2

30

HD

23

,30

VD

23

,30

CI5

30

CI7

30

CI4

30

CI6

30

CI3

30C

I230

CI1

30C

I030

YI4

23

,30

YI6

23

,30

YI3

23

,30

YI5

23

,30

YI2

23

,30

YI1

23

,30

YI0

23

,30

PC

LK

23

,30

YI7

23

,30

DA

C_

IOU

TA

25

DA

C_

IOU

TB

25

DA

C_

IOU

TC

25

DA

C_

IOU

TD

25

AU

DIO

_CL

K2

6,3

1

VID

_C

LK

30

3V

3.D

C_

PC

LK

27

PL

L.F

S2

28P

LL.

FS

128

PL

L.S

R28

PLL

.CS

EL

28

CP

LD

_T

IME

R_

IN15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

C

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

We

dn

esd

ay,

No

vem

be

r 1

6,

200

55

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

VID

EO

IN

TE

RF

AC

E

VREF =1.24 VOLTS

R2

3622

TP

67

1

R2

94N

O-P

OP

R2

3322

R2

430

R3

0310

0K

C31

0N

O-P

OP

R2

9133

Q1

2N39

04

U2

8G

DA

VIN

CI-

BG

A_

24

DA

C_I

OU

TA

P19

DA

C_I

OU

TB

P18

DA

C_I

OU

TC

R19

DA

C_I

OU

TD

T19

VS

SA

11T

18

VS

SA

18P

17

DA

C_V

RE

FR

17

VD

DA

18V

R18

DA

C_R

BIA

SR

16

VD

DA

11P

16

R3

653

3

TP

66

1

C2

31.0

01

uF

C2

71N

O-P

OP

U2

8I

DA

VIN

CI-

BG

A_

24

CI7

/CC

D15

/UA

RT

_RX

D2

N19

CI6

/CC

D14

/UA

RT

_TX

D2

N18

CI5

/CC

D13

/UA

RT

_CT

S2

N17

CI4

/CC

D12

/UA

RT

_RT

S2

N16

CI3

/CC

D11

N15

CI2

/CC

D10

M17

CI1

/CC

D09

M16

CI0

/CC

D08

M15

YI7

/CC

D07

L18

YI6

/CC

D06

L17

YI5

/CC

D05

L16

YI4

/CC

D04

L15

YI3

/CC

D03

K19

YI2

/CC

D02

K18

YI1

/CC

D01

K17

YI0

/CC

D00

K16

PC

LKM

19

HD

M18

VD

L19

GIO

47/P

WM

2/B

2A

15

GIO

46/P

WM

1/R

2B

15

YO

UT

7E

18

YO

UT

6E

17

YO

UT

5E

16

YO

UT

4/A

EA

W4

E15

YO

UT

3/A

EA

W3

D18

YO

UT

2/A

EA

W2

D17

YO

UT

1/A

EA

W1

D16

YO

UT

0/A

EA

W0

D15

CO

UT

7C

16

CO

UT

6B

19

CO

UT

5B

18

CO

UT

4A

18

CO

UT

3/D

SP

_BT

B17

CO

UT

2/8_

16A

17

CO

UT

1/B

TS

EL1

B16

CO

UT

0/B

T_S

EL0

A16

VC

LKD

19

VS

YN

CC

18

HS

YN

CC

17

VB

EC

LKC

19

GIO

45/P

WM

0C

15

TP53 1

C2

30.1

uF

R2

923

3

TP

61 1

R30

20

R2

97

33

RN

21

RP

AC

K8-

33

123456789 10 11 12 13 14 15 16

C2

32.1

uF

R2

417

.5K

U5

7S

N7

4A

UC

1G12

5

3

4

5

2

1

R2

3222

R2

93N

O-P

OP

R3

0010

K

C23

51

uF

C2

33.0

01

uF

RN

18

RP

AC

K8-

33

123456789 10 11 12 13 14 15 16

TP55 1

C31

21

0p

F

R2

981

0K

C26

7

0.1

uF

U5

5

PLL

1705

VD

D1

1V

DD

213

XT

110

XT

211

VD

D3

20

VC

C8

DG

ND

14

DG

ND

216

SR

7

FS

26

FS

15

SC

KO

119

AG

ND

9

DG

ND

317

SC

KO

33

SC

KO

018

SC

KO

22

MC

KO

215

MC

KO

114

CS

EL

12

+C

66

10u

F

R2

95N

O-P

OP

R2

1622

C2

70

0.1

uF

+C

65

10u

F

L22

BLM

21P

G2

21S

N1D

1 2

C2

69

0.1

uFR

29

910

K

U5

6S

N7

4A

UC

1G

12

5

3

4

5

2

1

R6

30.

22

R6

20.

22

TP

54 1

R2

404

.99

K

C2

72

0.1

uF

R3

042.

2K

R2

90

33

R2

3422

R3

01

NO

-PO

P

C2

73

10

0pF

R1

9422

L21

BLM

21P

G2

21S

N1D

1 2

R2

44N

O-P

OP

+C

71

10

uF

R3

6633

C26

8

0.1

uF

R2

9610

K

R3

071K

R2

39

4.0

2K

Y5

27M

Hz U

39

TL

V43

1AD

BV

53

4

R24

21K

C23

4.1

uF

R3

052

2.1

K 1

%

U5

4

PI6

CX

100

-27W

X1

1X

28

GN

D4

VIN

3V

DD

6

CLK

OU

T5

NC

12

NC

27

C3

110

.1u

F

C2

66

0.1

uF

C2

65

0.1

uF


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

I2C

_C

LK

I2C

_D

AT

A

UA

RT

_RX

D0

UA

RT

_TX

D0

3V

3.I

2C

_C

LK

3V

3.I

2C_

DA

TA

1V8

.MS

P43

0_I

NT

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3

.3V

VC

C_

1.8

V

VC

C_

1.8

V

1V

8.I2

C_

CL

K2

6,3

0,3

1

GIO

330

GIO

630

GIO

030

GIO

230

GIO

530

GIO

38

30

GIO

430

GIO

130

GIO

V3

3_0

22

,31

GIO

V3

3_2

22

,31

GIO

V3

3_4

22

,31

GIO

V3

3_6

22

,31

GIO

V33

_8

22,3

1

GIO

V33

_10

22

,31

GIO

V33

_12

22

,31

GIO

V33

_14

22

,31

GIO

V33

_16

22

,31

GIO

V3

3_1

22

,31

GIO

V3

3_3

22

,31

GIO

V3

3_5

22

,31

GIO

V3

3_7

22

,31

GIO

V3

3_9

22

,31

GIO

V33

_11

22

,31

GIO

V33

_13

22

,31

GIO

V33

_15

22

,31 SP

I_E

N1

31

SP

I_E

N0

31

SP

I_C

LK

31

SP

I_D

I31

SP

I_D

O31

3V

3.I

2C

_C

LK

24

,27,

28

3V

3.I

2C

_DA

TA

24,2

7,2

8

UA

RT

_R

XD

020

UA

RT

_TX

D0

20

1V

8.I

2C

_D

AT

A2

6,3

0,31

1V8.

MS

P4

30_I

NT

15

AT

A_

DIR

15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

56

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

I/O

IN

TE

RF

AC

E

EEPROM ( 32KBytes )

R4

24

10K

U3

4 24W

C2

56

A0

1V

CC

8

VS

S4

NC

3S

CL

6

SD

A5

A1

2W

P7

U2

8C

DA

VIN

CI-

BG

A_

24

GIO

V33

.1/T

XC

LKA

13

GIO

V33

.2/C

OL

A12

GIO

V33

.3/T

XD

0B

12

GIO

V33

.13/

RX

ER

D10

GIO

V33

.4/T

XD

1D

12

GIO

V33

.5/T

XD

2A

11

GIO

V33

.6/T

XD

3C

12

GIO

V33

.7/R

XD

0E

12

GIO

V33

.14/

CR

SC

10

GIO

V33

.8/R

XD

1C

11

GIO

V33

.9/R

XD

2B

11

GIO

V33

.10/

RX

D3

E11

GIO

V33

.11/

RX

CLK

A10

GIO

V33

.15/

MD

IOE

10

GIO

V33

.12/

RX

DV

D11

GIO

V33

.0/T

XE

NB

13

GIO

0/LC

D_O

EC

13

GIO

1/C

_WE

NE

13

GIO

2/G

0D

13

GIO

3/LC

D_F

IELD

/B0

C14

GIO

4/C

_FIE

LD/R

0B

14

GIO

5/G

1E

14

GIO

6/B

1A

14

GIO

44/I2

C_D

AT

AB

4

GIO

38/R

1D

14

GIO

43/I2

C_C

LKC

4

GIO

36/U

AR

T_T

XD

0C

5G

IO35

/UA

RT

_RX

D0

D5

GIO

41/S

PI_

DO

A2

GIO

37/S

PI_

EN

0A

4

GIO

42/S

PI_

EN

1/A

TA

DIR

B2

GIO

39/S

PI_

CLK

A3

GIO

7C

3

GIO

V33

.16/

MD

CB

10

GIO

40/S

PI_

DI

B3

R2

12

2.2

K

R2

0122

C1

620

.1u

F

C1

940

.1u

F

R2

112

.2K

R2

152.

2K

R1

9722

C1

950

.1u

F

R1

9822

R2

142

.2K

R2

1310

0K

VREF

2

GN

D

VR

EF1

ENAB

LE

SC

L1

SDA1

SC

L2

SDA2

U33

PC

A9

306

7 6

2

8

3 1

54

RN

14

RP

AC

K4

-22

1 2 3 45678

R4

1010

K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_3

.3V

VC

C_

1.8

V

VC

C_

3.3

V

SD

_C

LK1

6,3

1,32

SD

_DA

TA

01

6,3

1,32

SD

_C

MD

16

,31,

32

SD

_DA

TA

11

6,3

1,3

2

SD

_DA

TA

31

6,3

1,3

2S

D_D

AT

A2

16

,31,

32

CL

KR

31

FS

R31

DR

31D

X2

7,31

FS

X31

CLK

X31

US

B_

ID21

US

B_V

BU

S2

1

B_C

LK

R26

B_

FS

R26

B_

DR

26B

_DX

26

B_F

SX

26

B_C

LKX

26

McB

SP

_E

N31

US

B_

DM

21

US

B_

DP

21

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

We

dn

esd

ay,

No

vem

be

r 1

6,

200

57

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

US

B &

SD

/MM

C/M

MC

CO

NT

RO

LL

ER

Place C206 as close to device as possible, between 2 to 5 millimeters

U53 is a switch used for DC3 to allow the McBSP

to be disconnected from on-board circuitry.

Signal levels are at 1.8 Volt logic levels on both

sides of switch

Place R217 as close to device as possible

C27

4

0.1

uF

R6

00

.22

R3

08

10K

RN

15

RP

AC

K4-

22

1 2 3 45678

RN

16

RP

AC

K4-

22

12345 6 7 8

C2

09

0.1

uF

R3

0936

0

R1

9922

TP

48 1

TP

49 1

C2

11

0.0

1u

F

U2

8H

DA

VIN

CI-

BG

A_

24

US

B_V

DD

A3P

3PH

YJ1

9

US

B_V

SS

A3P

3PH

YJ1

8

US

B_V

DD

A1P

8PH

YH

17

US

B_V

SS

A1P

8PH

YH

16

US

B_D

PG

19

US

B_I

DJ1

6

US

B_V

BU

SJ1

7

US

B_V

DD

A1P

2LD

OP

HY

G18

US

B_V

SS

_RE

F_P

HY

G16

US

B_D

MH

19

US

B_R

1H

18

R1

962

2

R2

0022

U53

74C

BT

LV32

45

A1

2B

118

A2

3B

217

A3

4B

316

A4

5B

415

A5

6B

514

A6

7B

613

A7

8B

712

A8

9B

811

G19

NC

1V

CC

20

GN

D10

U2

8F

DA

VIN

CI-

BG

A_

24

GIO

31/F

SX

C8

GIO

32/F

SR

C7

GIO

29/C

LKX

B8

GIO

30/C

LKR

A8

GIO

33/D

XB

7

GIO

34/D

RA

7

SD

_DA

TA

1/M

S_D

AT

A1

E9

SD

_DA

TA

0/M

S_D

AT

A0

D8

SD

_DA

TA

2/M

S_D

AT

A2

D9

SD

_DA

TA

3/M

S_D

AT

A3

C9

SD

_CM

D/M

S_B

SB

9

SD

_CLK

/MS

_CLK

A9

R2

1710

K

C2

06

1u

F

TP

47 1

L15

BLM

21

PG

22

1SN

1D1

2

L13

BL

M2

1PG

221S

N1D

12

R1

952

2

TP

46 1

C2

12

0.1

uF

+C

59

10

uF

+C

60

10

uF

C2

07

0.0

1u

F

R6

10

.22


A-9

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1

.8V

VC

C_1

.8V

VC

C_1

.8V

DS

P_

CO

RE

_V

DD

DS

P_

EM

U0

33

DS

P_

EM

U1

33

DS

P_T

RS

T#

33

DS

P_

TD

O33

DS

P_

TD

I33

DS

P_

TM

S33

DS

P_

RT

CK

33

DS

P_T

CK

33

TIM

ER

_IN

15

1.8

V.S

YS

_R

ES

ET

z1

3,1

5,2

6,2

9,3

0,3

1,3

4

CLK

OU

T0

29

Siz

e:

Da

te:

DW

G N

OR

ev

isio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

508

162-

0001

We

dn

esd

ay,

No

vem

be

r 1

6,

20

05

835

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

EM

UL

AT

ION

& C

LO

CK

S

OPTIONAL OSCILLATOR POPULATION

CRYSTAL AND CAPS REMOVED WHEN

OSCILLATOR IS USED

R2

35

NO

-PO

P

TP

8 1

R1

78N

O-P

OPC

22

7.1

uF

EIA

0402 C1

41

.1u

F

EIA

040

2

R1

77

0

C1

44

18

pF

TP

20 1

R2

37

0

C1

40

10

00pF

C2

29

18

pF

R2

38N

O-P

OP

R1

76N

O-P

OP

C1

47

1u

F

C1

48

1u

F

TP

18 1

TP

19 1

C1

39

18

pF

U1

2

NO

-PO

P/2

7 M

Hz

VC

C4

OU

T3

GN

D2

EN

1

TP

10

1

Y3 24

MH

z

L5

BL

M2

1PG

221S

N1D

12

L2

BLM

21P

G2

21S

N1D

12

Y2 27

MH

z

U2

8E

DA

VIN

CI-

BG

A_

24

TC

KA

6

TM

SE

6

TR

ST

D7

TD

IA

5

TD

OB

5

EM

U1

C6

EM

U0

D6

RE

SE

TL4

M24

X0

F19

M24

GN

DF

17

M24

XI

F18

GIO

49/C

LKO

UT

1/T

IM_I

NE

19

GIO

48/C

LKO

UT

0K

1

RT

CK

B6

MX

0M

1

MX

IL1

MX

GN

DL2

AP

LLR

EF

VM

3

AM

UX

L3

PLL

PW

R18

M2

R3

50

.22

U4

0

NO

-PO

P/2

4 M

Hz

VC

C4

OU

T3

GN

D2

EN

1

C1

420

.1uF

C1

380

.1uF

TP

9

1

L6

BL

M2

1PG

221

SN

1D1

2

R3

40

.22

C2

28

18

pF

C1

37

10

00pF

L14

BL

M2

1PG

221S

N1D

12



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CP

U_

DS

P_

CO

RE

_V

DD

IMX

CP

U_

VC

C_

3.3

V

CP

U_

DS

P_C

OR

E_

VD

D

CP

U_

VC

C_

1.8

V

CP

U_

VC

C_1

.8V

CP

U_

VC

C_

1.8

V

CP

U_

VC

C_

1.8

V

CP

U_

VC

C_

1.8

V

CP

U_

DS

P_C

OR

E_

VD

DIM

X

CP

U_

VC

C_

3.3

V

CP

U_

DS

P_

CO

RE

_V

DD

VC

C_

3.3

V

VC

C_

1.8

V

DS

P_

CO

RE

_V

DD

DS

P_

CO

RE

_VD

DIM

X

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

59

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

PO

WE

R P

INS

R42

0.02

5

C20

5

0.1

uF

C1

83

0.1

uF

R54

0.0

25

+C

30

22

uF

C1

85

0.1

uF

C2

14

0.1

uF

C1

79

0.1

uF

TP

21

1

C1

99

0.1

uF

C2

10

0.1

uF

C1

46

0.1

uF

C20

2

0.1

uF

C1

88

0.1

uF

+C

40

22u

F

+C

312

2u

F

+C

47

22u

F

C1

78

0.1

uF

C13

6

0.1

uF

+C

272

2u

F

C1

84

0.1

uF

R36

0.0

25

C1

77

0.1

uF

C1

75

0.1

uF

C1

76

0.1

uF

TP

31 1

C1

80

0.1

uF

+C

582

2u

F

C1

11

0.1

uF

C1

86

0.1

uF

+

C1

25N

O-P

OP

C2

03

0.1

uF

TP

22 1

C1

43

0.1

uF

C1

34

0.1

uF

C2

15

0.1

uF

+C

48

22

uF

C1

45

0.1

uF

C1

35

0.1

uF

C1

13

0.1

uF

+

C1

30

NO

-PO

P

C1

67

0.1

uF

C1

81

0.1

uF

TP

42 1

C1

74

0.1

uF

TP

11 1

C1

87

0.1

uF

U2

8D

DA

VIN

CI-

BG

A_

24

VD

DS

.1E

7V

DD

S.2

F6

VD

DS

.3F

8V

DD

S.4

F14

VD

DS

.5F

16V

DD

S.6

G7

VD

DS

.7G

9V

DD

S.8

G15

VD

DS

.9H

6V

DD

S.1

0H

14V

DD

S.1

1J7

VD

DS

.12

J15

VD

DS

.13

K6

VD

DS

.14

K14

VD

DS

.15

L5V

DD

S.1

6L7

VD

DS

.17

L13

VD

DS

.18

M6

VD

DS

.19

M14

VD

DIM

X.1

H8

VD

DIM

X.2

H10

VD

DIM

X.3

H11

VD

DIM

X.4

H12

VD

DIM

X.5

J9V

DD

IMX

.6J1

0V

DD

IMX

.7J1

1V

DD

IMX

.8J1

3V

DD

IMX

.9K

8V

DD

IMX

.10

K9

VD

DIM

X.1

1K

11

VD

D.1

F15

VD

D.2

K10

VD

D.3

K12

VD

D.4

L8V

DD

.5L9

VD

D.6

L10

VD

D.7

L11

NC

.3A

19

PO

RD

ISD

4

VS

S.2

0K

5V

SS

.21

K7

VS

S.2

2K

13V

SS

.23

K15

VS

S.2

4L6

VS

S.2

5L1

2V

SS

.26

L14

VS

S.2

7M

5V

SS

.28

M7

VS

S.2

9M

9V

SS

.30

M11

VS

S.3

1M

13V

SS

.32

N6

VS

S.3

3N

8V

SS

.34

N10

VS

S.3

5N

12V

SS

.36

N14

VS

S.3

7P

7V

SS

.38

P9

VS

S.3

9P

11V

SS

.40

P13

VS

S.4

1P

15V

SS

.42

R6

VS

S.4

3R

7V

SS

.44

R10

VS

S.4

5R

12

VS

S.1

4H

13V

SS

.15

H15

VS

S.1

6J6

VS

S.1

7J8

VS

S.1

8J1

2V

SS

.19

J14

VS

S.1

E8

VS

S.2

F7

VS

S.3

F9

VS

S.7

G11

VS

S.9

G13

VS

S.4

G6

VS

S.8

G12

VS

S.1

0G

14V

SS

.11

G17

VS

S.1

2H

7V

SS

.13

H9

VD

DS

1.1

N7

VD

DS

1.2

N9

VD

DS

1.3

N11

VD

DS

1.4

N13

VD

DS

1.5

P6

VD

DS

1.6

P8

VD

DS

1.7

P10

VD

DS

1.8

P12

VD

DS

1.9

P14

VD

DS

1.10

R9

VD

DS

1.11

R11

VD

DS

1.12

R13

VD

DS

1.13

R15

VD

D.8

M8

VD

D.9

M10

VD

D.1

0M

12

VD

DS

HV

.1F

10V

DD

SH

V.2

F11

VD

DS

HV

.3F

12V

DD

SH

V.4

F13

VS

S.5

G8

VS

S.6

G10

VD

DS

.20

N5

VS

S.4

6R

14

NC

.4W

19

VD

DS

1.14

T5

NC

.1A

1N

C.2

W1

TP

41 1

R3

70

.02

5

+C

28

22u

F

+

C1

32

NO

-PO

P

C20

0

0.1

uF

C2

04

0.1

uF

C16

8

0.1

uF

C2

01

0.1

uF

C1

15

0.1

uF

C2

08

0.1

uF

+C

49

22u

F

C2

13

0.1

uF

C1

82

0.1

uF

R2

02

0

TP

30 1

TP

32 1 +C

12

7N

O-P

OP

C1

69

0.1

uF

+C

29

22

uF


A-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

1.8

V

YO

UT

05

,30

YO

UT

15

,30

YO

UT

25

,30

YO

UT

35

,30

YO

UT

45

,30

EM

_CS

23

,15

NA

ND

_C

Ez

12S

RA

M_C

Ez

12F

LA

SH

_CE

z13

DC

_E

M_C

S2

29

CO

UT

35

,30

CO

UT

25

,30

CO

UT

15

,30

CO

UT

05

,30

US

ER

_S

W28

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

We

dn

esd

ay,

No

vem

be

r 1

6,

200

510

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

CO

NF

IGU

RA

TIO

N C

ON

TR

OL

/BO

OT

OP

TIO

NS

BOOT CONFIGURATION SWITCH

ONLY ONE DEVICE CAN BE SELECTED

AT A TIME AT POWER UP.

TO RECONFIGURE BOARD

POWER DOWN EVM,

CHANGE JUMPER TO DESIRED DEVICE.

11 = Boot from ROM (UART)

1 = GEM Self-Boots

PINS

FUNCTION

SWITCH S1

Selects ARM Boot Mode

BTSEL[1:0]

00 = Boot from ROM (NAND)

01 = Boot from AEM IF

10 = Boot from ROM (HPI)

Non-secure device

COUT[1:0]

MODE

Selects AEM IF CS2 Bus Width

8_16

COUT2

0 = 8-bit

1 = 16-bit

S1-2=XXX S1-1=XXX

S1-3=XXX

S1-3=XXX

S1-2=XXX S1-1=XXX

S1-2=XXX S1-1=XXX

S1-2=XXX S1-1=XXX

COUT3

DSP_BT

0 = ARM boots GEM

S1-4=XXX

S1-4=XXX

YOUT[4:0]

AEAW [4:0]

Address Bus Width

DSP BOOT

S1-5=XXX

S1-6=XXX

S1-7=XXX

S1-8=XXX

ALL

ADDRESS LINES GPIO

S1-9=XXX

SPARE SWITCH

R2

30

1K

R2

2710

K

R2

29

1K

1 2 3 4 5 6 7 8 9 10S3

DIP

_S

WIT

CH

-10

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

RN

29R

PA

CK

8-1

K

1 2 3 4 5 6 7 8910111213141516

R22

8N

O-P

OP

RN

28

RP

AC

K8

-NO

-PO

P

123456789

10111213141516

J4

CO

NN

4x2

2 4 6 8

1 3 5 7



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

A1

0

DD

R_

A8

DD

R_

A7

DD

R_

A1

DD

R_

A9

DD

R_

A5

DD

R_

A0

DD

R_

A6

DD

R_

A2

DD

R_

A1

1D

DR

_A

12

DD

R_

A3

DD

R_

A4

DD

R_

A4

DD

R_

A3

DD

R_

A1

2D

DR

_A

11

DD

R_

A2

DD

R_

A6

DD

R_

A0

DD

R_

A5

DD

R_

A9

DD

R_

A1

DD

R_

A7

DD

R_

A8

DD

R_

A1

0

DD

R_B

S0

0D

DR

_BS

01

DD

R_B

S0

2D

DR

_B

S02

DD

R_

BS

01D

DR

_B

S00

DD

R_

CL

K_

ND

DR

_C

LK

DD

R_

CS

DD

R_

CL

KD

DR

_C

LK_

N

DD

R_C

AS

DD

R_C

KE

DD

R_R

AS

DD

R_

WE

DD

R_

DQ

S0

DD

R_

DQ

M0

DD

R_

DQ

S1

DD

R_

DQ

S2

DD

R_

DQ

M1

DD

R_

DQ

M2

DD

R_

DQ

M3

DD

R_

CS

DD

R_

RA

S

DD

R_

CK

E

DD

R_

CA

S

DD

R_

WE

DD

R_

DQ

S3

VR

EF

_ST

L

VR

EF

_S

TL

DD

R_

D1

2D

DR

_D

14

BD

DR

_D

15

BD

DR

_D

14

BD

DR

_D

13

BD

DR

_D

12

BD

DR

_D

11

BD

DR

_D

10

BD

DR

_D

9B

DD

R_

D8

BD

DR

_D

7B

DD

R_

D6

BD

DR

_D

5B

DD

R_

D4

BD

DR

_D

3B

DD

R_

D2

BD

DR

_D

1

BD

DR

_D

14

BD

DR

_D

12

DD

R_

D2

8

DD

R_

D2

9

DD

R_

D3

0

BD

DR

_D

31

BD

DR

_D

30

BD

DR

_D

29

BD

DR

_D

27

BD

DR

_D

28

BD

DR

_D

26

BD

DR

_D

25

BD

DR

_D

24

BD

DR

_D

23

BD

DR

_D

22

BD

DR

_D

21

BD

DR

_D

20

BD

DR

_D

19

BD

DR

_D

18

BD

DR

_D

17

BD

DR

_D

16

BD

DR

_D

29

BD

DR

_D

30

BD

DR

_D

28

DD

R_

D2

DD

R_

D0

BD

DR

_D

2

BD

DR

_D

0

BD

DR

_D

0

DD

R_

D9

DD

R_

D1

1B

DD

R_

D1

1B

DD

R_

D9

DD

R_

D3

1D

DR

_D

24

BD

DR

_D

31

BD

DR

_D

24

BD

DR

_D

13

DD

R_

D1

5D

DR

_D

13

BD

DR

_D

15

DD

R_

D1

0D

DR

_D

8B

DD

R_

D1

0B

DD

R_

D8

DD

R_

D6

DD

R_

D4

BD

DR

_D

6B

DD

R_

D4

DD

R_

D1

DD

R_

D3

BD

DR

_D

1B

DD

R_

D3

BD

DR

_D

17

BD

DR

_D

19

BD

DR

_D

20

BD

DR

_D

22

BD

DR

_D

27

BD

DR

_D

25

DD

R_

D2

7D

DR

_D

25

BD

DR

_D

16

BD

DR

_D

18

DD

R_

D1

6D

DR

_D

18

BD

DR

_D

23

BD

DR

_D

21

DD

R_

D2

3

DD

R_

D2

1

BD

DR

_D

5B

DD

R_

D7

DD

R_

D7

DD

R_

D5

BD

DR

_D

26

DD

R_

D2

6

DD

R_

D1

7D

DR

_D

19

DD

R_

D2

2D

DR

_D

20

BD

DR

_D

[0:1

5]

BD

DR

_D

[16

:31

]

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1

.8V

DD

R_D

[0:3

1]

4

DD

R_

A[0

:12

]4

DD

R_

BS

02

4D

DR

_B

S0

14

DD

R_

BS

00

4

DD

R_W

E4

DD

R_

CK

E4

DD

R_

CL

K4

DD

R_

RA

S4 D

DR

_C

LK

_N

4

DD

R_

CA

S4

DD

R_

CS

4

DD

R_

DQ

M2

4D

DR

_D

QM

34

DD

R_

DQ

S2

4

DD

R_

DQ

S1

4

DD

R_

DQ

S0

4 DD

R_

DQ

M1

4D

DR

_D

QM

04

VR

EF

_ST

L4

DD

R_

DQ

S3

4

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

511

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DD

R2

ME

MO

RY

128 MEGABYTES

128 MEGABYTES

RN

31

RP

AC

K4

-47

1 2 3 45678

U2

0

MT

47H

64M

16B

T

A12

V2

A11

U7

A10

R2

A9

U3

A8

U8

A7

U2

A6

T7

A5

T3

A4

T8

A3

T2

A2

R7

A1

R3

A0

R8

BA

2P

1

BA

1P

3

BA

0P

2

NC

.1A

A9

NC

.2A

A8

NC

.3A

A2

NC

.4A

A1

NC

.5D

2

NC

.6V

8

NC

.7A

9

NC

.8A

8

NC

.9A

2

NC

.10

A1

NC

.11

H2

RF

U.1

V3

RF

U.2

V7

OD

TN

9

CS

#P

8

CA

S#

P7

RA

S#

N7

WE

#N

3

CK

EN

2

CK

M8

CK

#N

8

UD

QS

#/N

UD

8

UD

QS

E7

LDQ

S#/

NU

H8

LDQ

SJ7

UD

ME

3

LDM

J3

VD

D.1

M9

VD

D.2

H1

VD

D.3

R9

VD

D.4

D1

VD

D.5

V1

VD

DQ

.1F

3

VD

DQ

.2F

7

VD

DQ

.3K

1

VD

DQ

.4K

3

VD

DQ

.5K

7

VD

DQ

.6K

9

VD

DQ

.7D

9

VD

DQ

.8F

1

VD

DQ

.9F

9

VD

DQ

.10

H9

VD

DL

M1

VR

EF

M2

DQ

15E

9

DQ

14E

1

DQ

13G

9

DQ

12G

1

DQ

11G

3

DQ

10G

7

DQ

9F

2

DQ

8F

8

DQ

7J9

DQ

6J1

DQ

5L9

DQ

4L1

DQ

3L3

DQ

2L7

DQ

1K

2

DQ

0K

8

VS

S.1

U9

VS

S.2

T1

VS

S.3

H3

VS

S.4

D3

VS

S.5

M3

VS

SQ

.1G

8

VS

SQ

.2J8

VS

SQ

.3D

7

VS

SQ

.4J2

VS

SQ

.5E

2

VS

SQ

.6L8

VS

SQ

.7L2

VS

SQ

.8E

8

VS

SQ

.9H

7

VS

SQ

.10

G2

VS

SD

LM

7

RN

26

RP

AC

K4-

47

1 2 3 45678

U3

2

MT

47H

64M

16B

T

A12

V2

A11

U7

A10

R2

A9

U3

A8

U8

A7

U2

A6

T7

A5

T3

A4

T8

A3

T2

A2

R7

A1

R3

A0

R8

BA

2P

1

BA

1P

3

BA

0P

2

NC

.1A

A9

NC

.2A

A8

NC

.3A

A2

NC

.4A

A1

NC

.5D

2

NC

.6V

8

NC

.7A

9

NC

.8A

8

NC

.9A

2

NC

.10

A1

NC

.11

H2

RF

U.1

V3

RF

U.2

V7

OD

TN

9

CS

#P

8

CA

S#

P7

RA

S#

N7

WE

#N

3

CK

EN

2

CK

M8

CK

#N

8

UD

QS

#/N

UD

8

UD

QS

E7

LDQ

S#/

NU

H8

LDQ

SJ7

UD

ME

3

LDM

J3

VD

D.1

M9

VD

D.2

H1

VD

D.3

R9

VD

D.4

D1

VD

D.5

V1

VD

DQ

.1F

3

VD

DQ

.2F

7

VD

DQ

.3K

1

VD

DQ

.4K

3

VD

DQ

.5K

7

VD

DQ

.6K

9

VD

DQ

.7D

9

VD

DQ

.8F

1

VD

DQ

.9F

9

VD

DQ

.10

H9

VD

DL

M1

VR

EF

M2

DQ

15E

9

DQ

14E

1

DQ

13G

9

DQ

12G

1

DQ

11G

3

DQ

10G

7

DQ

9F

2

DQ

8F

8

DQ

7J9

DQ

6J1

DQ

5L9

DQ

4L1

DQ

3L3

DQ

2L7

DQ

1K

2

DQ

0K

8

VS

S.1

U9

VS

S.2

T1

VS

S.3

H3

VS

S.4

D3

VS

S.5

M3

VS

SQ

.1G

8

VS

SQ

.2J8

VS

SQ

.3D

7

VS

SQ

.4J2

VS

SQ

.5E

2

VS

SQ

.6L8

VS

SQ

.7L2

VS

SQ

.8E

8

VS

SQ

.9H

7

VS

SQ

.10

G2

VS

SD

LM

7

C2

24

0.1

uF

+C

57

22

uF

C1

54

0.1

uF

C2

17

0.1

uF

C22

20

.1u

F

C2

200

.1u

F

C1

52

0.1

uF

C2

180

.1u

F

RN

27

RP

AC

K4-

47

1 2 3 45678

R2

081

K 1

%

+C

18

22

uF

+C

102

NO

-PO

P

RN

19

RP

AC

K4

-47

1 2 3 45678

RN

6R

PA

CK

4-4

71 2 3 4

5678

RN

20

RP

AC

K4

-47

1 2 3 45678

C1

51

0.1

uF

C2

21

0.1

uF

C1

57

0.1

uF

C1

49

0.1

uF

C1

56

0.1

uF

RN

5R

PA

CK

4-4

7

1 2 3 45678

R2

071

K 1

%

C2

25

0.1

uF

RN

30

RP

AC

K4

-47

1 2 3 45678

C1

50

0.1

uF

C22

30

.1u

F

C1

55

0.1

uF

C2

19

0.1

uF

C1

53

0.1

uF


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_A7

EM

_A6

EM

_A9

EM

_A4

B.E

M_A

11B

.EM

_A10

EM

_A5

EM

_A8

EM

_A3

B.E

M_A

16B

.EM

_A15

B.E

M_A

13B

.EM

_A12

B.E

M_A

17

B.E

M_A

14

B.E

M_A

19B

.EM

_A18

AT

A2_

EM

_A0

AT

A1_

EM

_BA

1

SR

AM

_C

E2

EM

_D

2

EM

_D

8

EM

_D

5 EM

_D

0

EM

_D

2E

M_

D3

EM

_D

4

EM

_D

4

EM

_D

14

EM

_D

15

EM

_D

5

EM

_D

3

EM

_D

7

EM

_D

12

EM

_D

1

EM

_D

6

EM

_D

13

EM

_D

6

EM

_D

0

EM

_D

11

EM

_D

10

EM

_D

9 EM

_D

7

EM

_D

1

CL

E_

EM

_A2

CL

E_

EM

_A

2

ALE

_EM

_A1

AL

E_

EM

_A1

WR

ITE

_WE

RE

AD

_O

E

RE

AD

_O

EW

RIT

E_

WE

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

1.8

V

EM

_A

[3:2

1]3

,13

,14

,29

AT

A2_

EM

_A0

3,1

3,1

5,2

9A

LE

_E

M_A

13

,13

,15,

29

WR

ITE

_WE

3,1

3,1

5,29

CLE

_E

M_A

23

,13

,15

,29

SR

AM

_C

Ez

10AT

A1_

EM

_BA

13

,13

,15

,29

RE

AD

_O

E3

,13

,15

,29 N

AN

D_

CE

z1

0

EM

_D

[0:1

5]

3,1

3,1

4,2

9

NA

ND

_BU

SY

15

B.E

M_

A[1

0:2

1]

13

,14,

29

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

512

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

SR

AM

/NA

ND

FLA

SH

SRAM ( 4MBytes )

NAND FLASH ( 64MBytes )

K9K1G08 supports 128 MEGABYTES

R1

37

10K

R1

41

10K

C9

00

.1u

F

R1

351

0K

U7

SA

MS

UN

G->

K1S

321

6B

CD

DQ

16G

1

DQ

1B

6

DQ

2C

5

DQ

3C

6

DQ

4D

5

DQ

5E

5

DQ

6F

5

DQ

7F

6

DQ

8G

6

DQ

9B

1

DQ

10C

1

DQ

11C

2

DQ

12D

2

DQ

13E

2

DQ

14F

2

DQ

15F

1

A0

A3

A1

A4

A2

A5

A3

B3

A4

B4

A5

C3

A6

C4

A7

D4

A8

H2

A9

H3

A10

H4

A11

H5

VSS.1 D1

VSS.2 E6

CS

1B

5

WE

G5

OE

A2

UB

B2

LBA

1

A12

G3

A13

G4

A14

F3

A15

F4

A16

E4

A17

D3

A18

H1

A19

G2

VCC.2E1VCC.1D6

NC

.1E

3

CS

2A

6

A20

H6

SA

MS

UN

G K

9K

120

8/Q

/D/U

/0C

U6

NC.1 B1

NC.2 B4

NC.3 B5

NC.4 B6

NC.5 C1

NC.6 C2

R/B

A6

RE

B2

CE

A4

NC.7 C3

NC.8 C4

VC

C.1

F6

VS

S.1

A3

NC.20 E4

NC.21 E5

CLE

B3

ALE

A2

WE

A5

WP

A1

NC.19 E3NC.18 E2NC.17 E1NC.16 D6NC.15 D5

VS

S.2

H1

I/O00

F2

NC.9 C5

I/O01

G2

NC.10 C6

I/O02

H2

NC.11 D1

I/O03

H3

NC.12 D2

NC.14 D4

NC.22 F1

NC.13 D3

VC

C.2

G4

LOC

KP

RE

E6

NC.23 F3

I/O04

H4

NC.25 F5

I/O05

G5

NC.24 F4

I/O06

H5

I/O07

G6

VS

S.3

H6

NC.26 G1

NC.27 G3

C9

2.1

uF

R1

39N

O-P

OP

R13

810

K

R13

60

R1

13

NO

-PO

P

R1

340

C9

10

.1u

F

C9

3.1

uF

R1

4010

K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_D3

EM

_D8

EM

_D6

EM

_D5

EM

_D7

EM

_D0

EM

_D1

EM

_D2

EM

_D4

EM

_D9

EM

_D10

EM

_D11

EM

_D13

EM

_D12

EM

_D14

EM

_D15

AT

A1

_EM

_BA

1A

TA

2_E

M_A

0A

LE_E

M_A

1C

LE

_EM

_A2

B.E

M_A

21

B.E

M_A

18

EM

_A8

EM

_A9

EM

_A7

B.E

M_A

19

EM

_A6

EM

_A4

B.E

M_A

15

B.E

M_A

12B

.EM

_A11

B.E

M_A

17

EM

_A3

B.E

M_A

13

B.E

M_A

10

B.E

M_A

16

B.E

M_A

14

EM

_A5

B.E

M_A

20

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

1.8

V

EM

_D

[0:1

5]

3,1

2,14

,29

FL

AS

H_

CE

z10

AT

A1_

EM

_BA

13

,12

,15

,29

EM

_A

[3:2

1]3

,12

,14

,29

AT

A2_

EM

_A0

3,1

2,1

5,2

9A

LE_E

M_A

13

,12

,15

,29

CL

E_E

M_A

23,

12

,15

,29

WR

ITE

_W

E3

,12

,15

,29

RE

AD

_O

E3

,12,

15,2

9

1.8

V.S

YS

_R

ES

ET

z8

,15

,26

,29,

30

,31

,34

B.E

M_

A[1

0:2

1]1

2,1

4,29

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

We

dn

esd

ay,

No

vem

be

r 1

6,

200

513

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

NO

R F

LA

SH

16 MBytes

U1

3A

M29

LV25

6M

A0

31

A1

26

A2

25

A3

24

A4

23

A5

22

A6

21

A7

20

A8

10

A9

9

A10

8

A11

7

A12

6

A13

5

A14

4

A15

3

A16

54

BY

TE

53

CE

32

OE

34

RE

SE

T14

WE

13

VC

C43

VS

S1

33V

SS

252

RY

/BY

17

DQ

15/A

-151

DQ

035

DQ

137

DQ

239

DQ

341

DQ

444

DQ

546

DQ

648

DQ

750

DQ

836

DQ

938

DQ

1040

DQ

1142

DQ

1245

DQ

1347

DQ

1449

A17

19

A18

18

A19

11

A20

12

A21

15

A22

2

A23

1

NC

127

NC

228

NC

330

NC

455

NC

556

WP

/AC

C16

VIO

29

C1

20.1

uF

R1

1410

K

R1

42

10K

R1

16N

O-P

OP

R1

151

0K

R14

310

K

C9

4.1

uF


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VLY

NQ

_R

XD

3V

LYN

Q_

RX

D2

EM

_A

12

EM

_A

10

EM

_A

11

B.E

M_

A16

B.E

M_

A20

B.E

M_

A15

B.E

M_

A17

B.E

M_

A18

B.E

M_

A19

B.E

M_

A21

B.E

M_

A14

EM

_A

18

EM

_A

21

EM

_A

17

EM

_A

19

EM

_A

15

EM

_A

16

EM

_A

14

EM

_A

20

B.V

LNQ

_TX

D0

B.V

LNQ

_TX

D1

B.V

LNQ

_TX

D2

B.V

LNQ

_TX

D3

VL

YN

Q_T

XD

1V

LY

NQ

_TX

D2

VL

YN

Q_T

XD

0

VL

YN

Q_T

XD

3

EM

_A

13

B.E

M_

A10

B.E

M_

A13

B.E

M_

A11

B.E

M_

A12

VLY

NQ

_R

XD

0V

LYN

Q_

RX

D1

3V

3.E

M_

D15

3V

3.E

M_

D14

3V

3.E

M_

D13

3V

3.E

M_

D12

3V

3.E

M_

D11

3V

3.E

M_

D10

3V

3.E

M_

D9

3V

3.E

M_

D8

3V

3.E

M_

D7

3V

3.E

M_

D6

3V

3.E

M_

D5

3V

3.E

M_

D4

3V

3.E

M_

D3

3V

3.E

M_

D2

3V

3.E

M_

D1

3V

3.E

M_

D0

EM

_D15

EM

_D14

EM

_D13

EM

_D12

EM

_D11

EM

_D10

EM

_D9

EM

_D8

EM

_D7

EM

_D6

EM

_D5

EM

_D4

EM

_D3

EM

_D2

EM

_D1

EM

_D0

VC

C_

3.3

V

VC

C_3

.3V

VC

C_

3.3

VV

CC

_1

.8V

VL

YN

Q_O

Nz

28E

M_

A[3

:21

]3

,12

,13

,29

VL

YN

Q_

RX

D0

32

VL

YN

Q_

RX

D1

32

VL

YN

Q_

RX

D2

32

VL

YN

Q_

RX

D3

32

SL

P_

CL

K_

EN

32E

LP

_R

EQ

/WA

KE

UP

32P

M_E

N32

WLA

N_

INT

R32

B.E

M_

A[1

0:2

1]

12

,13

,29

VLY

NQ

_T

XD

332

VLY

NQ

_T

XD

132

VLY

NQ

_T

XD

232

VLY

NQ

_T

XD

032

3V

3.E

M_D

[0:1

5]1

7,1

8,1

9

EM

_D

[0:1

5]

3,1

2,1

3,2

9 1V

8.E

M_D

AT

A_B

UF

_E

N15

1V8

.EM

_D

AT

A_

BU

F_D

IR15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

Mo

nd

ay,

Ma

rch

06

, 20

06

143

5

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

EM

IF L

EV

EL

SH

IFT

ER

U11 is a switch used to enable Vlynq functions.

Signal levels are at 1.8 Volt logic levels on both

sides of switch

L A TO B1

DIR BUS

L B->A

H B<-A

R4

13

22

R4

19

22

C1

050

.1u

F

C1

16

5.6

pF

U1

1

SN

74C

BT

LV1

629

2DG

GR

NC

.14

56GND.2 19

1A2

11A

25

1B1

54

1B2

53

GND.1 8VCC.117

GND.3 38

GND.4 49

NC

.13

55

2A4

3A6

4A9

5A11

6A13

7A15

8A18

9A21

10A

23

12A

27

NC

.13

NC

.25

NC

.37

NC

.410

NC

.512

NC

.614

NC

.716

NC

.820

S1

2B1

52

3B1

50

9B1

36

4B1

47

5B1

45

6B1

43

7B1

41

8B1

39

10B

134

2B2

51

3B2

48

4B2

46

5B2

44

6B2

42

7B2

40

8B2

37

11B

231

12B

229

NC

.922

NC

.10

24

NC

.11

26

NC

.12

28

11B

132

12B

130

9B2

35

10B

233

C1

19N

O-P

OP

R4

14

22

C1

21

0.1

uF

C1

17

5.6

pF

R1

4410

K

R4

15

22

C1

18

NO

-PO

P

R4

16

22

C3

73

560

pF

C1

060

.1u

F

R4

17

22

R3

92N

O-P

OP

C8

90

.1u

F

R4

12

22

U8

SN

74

AV

CB

1642

45V

R

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

1DIR

1

1OE

n48

2DIR

24

2OE

n25

VC

CB

7

VC

CB

18V

CC

A42

VC

CA

31

GN

D28

GN

D34

GN

D39

GN

D45

GN

D4

GN

D10

GN

D15

GN

D21

R39

3N

O-P

OP

R4

18

22

C8

80

.1u

F



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ISR

_T

CK

ISR

_T

MS

ISR

_T

DO

ISR

_T

CK

ISR

_T

DO

ISR

_TM

S

ISR

_T

DI

ISR

_T

CK

ISR

_T

DO

ISR

_T

DI

DL

OO

P1

DL

OO

P2

DL

OO

P3

DL

OO

P4

DL

OO

P5

ISR

_T

MS

VC

C_

3.3

VV

CC

_1

.8V

VC

C_

3.3

VV

CC

_3.3

V

VC

C_

3.3

V

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1

.8V

VC

C_3

.3V

VC

C_

3.3

V

3V

3.S

M_

CE

z28

CF

n_

SE

L2

8

3V

3.C

F_

PW

R_

ON

19

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AT

A_S

EL

28

1.8

V.S

YS

_R

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ET

z8

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34

1V

8.M

SP

43

0_IN

T6

INT

RQ

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M_

RN

W3

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WA

IT/B

US

Y3

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AT

A1

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13

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ALE

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3,1

2,1

3,2

9A

TA

2_E

M_

A0

3,1

2,1

3,2

9

CLE

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3,1

2,1

3,2

9

WR

ITE

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E3

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13

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RE

AD

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E3

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1V

8.E

M_D

AT

A_

BU

F_

DIR

141

V8.

EM

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TA

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F_E

N14

3V3

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A_B

UF

F_E

Nz

183

V3

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A_

BU

FF

_D

IR18

AT

A_

DIR

6

EM

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S2

3,10

AT

A_

CS

13

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AT

A_

CS

03

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UA

RT

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XD

1/D

MA

RQ

3U

AR

T_

TX

D1/

DM

AC

K3

AT

A0

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03

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3V3

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ET

n18

3V

3.A

TA

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US

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3V

3.A

TA

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AR

Q18

3V

3.A

TA

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TR

Q_

EM

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NW

18

3V

3.A

TA

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W18

3V3

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A.C

S0

18

3V

3.A

TA

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R18

3V3

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A.D

A0

183V

3.A

TA

.DA

118

3V3

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A.D

MA

CK

18

3V3

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A.C

S1

183V

3.A

TA

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218

MS

P43

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NT

283

V3

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S_

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SE

Tz

22

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3V

3.S

M.W

AIT

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SY

173V

3.S

M.S

M_C

Ez

17

3V3

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ITE

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17

3V3

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AD

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E17

3V3.

SM

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M_

A1

17

3V3.

SM

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M_

A2

17

3V3

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A0_

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A0

193V

3.C

F.A

TA

1_E

M_

BA

119

3V3

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A2_

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019

3V

3.C

F.R

EA

D_

OE

193V

3.C

F.A

TA

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S0

193V

3.C

F.A

TA

_C

S1

19

3V

3.C

F.W

RIT

E_

WE

19

3V

3.C

F.W

AIT

/BU

SY

19

3V

3.C

F.I

NT

RQ

_E

M_

RN

W19

3V3

.UA

RT

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XD

128

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3V3.

UA

RT

_TX

D1

28,

31

SP

AR

EIO

328

SP

AR

EIO

228

SP

AR

EIO

128

NA

ND

_B

US

Y12

TIM

ER

_IN

8

TIM

ER

_IN

_D

C3

31

CP

LD

_T

IME

R_

IN5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

C

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

515

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

EM

IF D

AT

A B

US

LE

VE

L S

HIF

TE

R

CPLD

REVISION 508163-0001B

C1

040

.1u

F

RN

24

RP

AC

K4

-10K

1 2 3 45678

C1

290

.1u

FC

131

0.1

uF

L62

NO

-PO

P

U1

4

EP

M24

0G

TC

100

B1.

PIN

22

B1.

PIN

33

TD

I.B1

23

B1.

PIN

44

B1.

PIN

66

B1.

PIN

77

B1.

PIN

88

B1.VCCIO1A9

GNDIO1 10

GNDINTA 11

B1.

GC

LK0

12

VCCINT113

B1.

GC

LK1

14

TM

S.B

122

B1.

PIN

1616

B1.

PIN

1717

B1.

PIN

1818

B1.

PIN

1919

B1.

PIN

2020

B1.

PIN

2121

B1.

PIN

2727

B1.

PIN

2626

B1.

PIN

2828

B1.

PIN

2929

B1.

PIN

3030

B1.VCCIO1B31

B1.

PIN

3333

B1.

PIN

3434

B1.

PIN

3535

B1.

PIN

3636

B1.

PIN

3737

B1.

PIN

3838

B1.

PIN

3939

B1.

PIN

4040

B1.

PIN

4141

B1.

PIN

4242

B1.

DE

V_O

E43

B1.

DE

V_C

LRn

44

B1.VCCIO1C45

GNDIO3 46

B1.

PIN

4747

B1.

PIN

4848

B1.

PIN

4949

B1.

PIN

5050

B1.

PIN

5151

B2.

PIN

5252

GNDIO2 32

B2.

PIN

5454

B2.

PIN

5555

B2.

PIN

5757

B2.

PIN

5858

B2.VCCIO1A59

GNDIO4 60

B2.

PIN

6161

TC

K.B

124

VCCINT263

B2.

PIN

6666

GNDINTB 65

B2.

PIN

6767

B2.

PIN

6868

B2.

PIN

6969

B2.

PIN

7070

B2.

PIN

7171

B2.

PIN

7272

TD

O.B

125

B2.

PIN

7373

B2.

PIN

7676

B2.

PIN

7777

GNDIO5 79

B2.VCCIO1B80

B2.

PIN

8181

B2.

PIN

8383

B2.

PIN

8484

B2.

PIN

8585

B2.

GC

LK3

64B

2.G

CLK

262

B2.

PIN

8686

GNDIO6 93

B2.VCCIO1C94

B2.

PIN

9696

B2.

PIN

9797

B2.

PIN

9898

B2.

PIN

9999

B2.

PIN

100

100

B1.

PIN

55

B1.

PIN

1515

B2.

PIN

5353

B2.

PIN

5656

B2.

PIN

7474

B2.

PIN

7575

B2.

PIN

7878

B2.

PIN

8282

B2.

PIN

8787

B2.

PIN

8888

B2.

PIN

8989

B2.

PIN

9090

B2.

PIN

9191

B2.

PIN

9292

B2.

PIN

9595

B2.

PIN

11

R4

0610

K

R3

68

NO

-PO

P

J17

SM

T F

EM

AL

E H

EA

DE

R 5

X2

12

34

56

78

910

C1

080

.1u

F

R4

31

0K

L63

BLM

41P

750S

PT

C10

90

.1u

F

R3

10K

R1

65

0

C1

28

0.1

uF

C1

070

.1u

F

R1

92

0

R3

693

3

R1

91

10K

C1

26

0.1

uF


A-17

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MS

.CLK

MS

.DA

TA

3

MS

.DA

TA

0

SD

_D

AT

A0

SD

_C

MD

SD

_D

AT

A1

MS

.CM

D.B

SM

S.D

AT

A1

MS

.DA

TA

1

MS

.DA

TA

0M

S.D

AT

A2

MS

.DA

TA

2

SD

_D

AT

A2

MS

.DA

TA

3M

S.C

LK

SD

_C

LK

SD

_D

AT

A3

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

SD

_D

AT

A1

7,3

1,32

SD

_DA

TA

37

,31,

32

SD

_D

AT

A2

7,3

1,32

SD

_C

LK

7,3

1,3

2SD

_C

MD

7,3

1,3

2

SD

_D

AT

A0

7,3

1,32

SD

/MM

C.I

NS

28

MS

.IN

S28

SD

/MM

C.W

P2

8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16,

20

05

163

5

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

SD

/MM

C/M

S C

ON

NE

CT

OR

SELECTS TERMINATION FOR SD/MMC/MS

WHEN USING DAT3 CARD DETECTION

PULL DOWN IS POPULATED WITH 470K OHM

RESISTOR AND PULL UP IN NOT POPULATED

J5 TERMINATION

MEMORY STICK

MEMORY STICK PRO

MMC CARD

SD CARD

1-2

1-2

1-2

2-3

R1

2351

K

J5

HE

AD

ER

3

1 2 3

R1

21

100

K

+C

10

10

uF

R1

19N

O-P

OP

R12

70

J3 SC

DB

2A

101

SD

.DA

T3

1

SD

.CM

D2

SD

.VS

S1

3

SD

.VD

D4

SD

.CLK

5

SD

.VS

S2

6

SD

.DA

T0

7

SD

.DA

T1

8

SD

.DA

T2

9

WP 20

COM 22

INS 21

GND.123

MS

.VS

S1

10M

S.B

S11

MS

.DA

TA

112

MS

.SD

IO/D

AT

A0

13M

S.D

AT

A2

14M

S.X

INS

15M

S.D

AT

A3

16M

S.S

CLK

17M

S.V

CC

18M

S.V

SS

219

R1

0851

K

R1

245

1K

C7

8

.1u

F

R1

2251

K

R9

90

R1

18N

O-P

OP

R1

26

51K

C9

5

0.1

uF

R1

2051

KR

117

51K

R7

351

K

U5

SN

74L

VC

1G

125

3

4

5

2

1

R1

25

NO

-PO

P



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3V

3.W

RIT

E_

WE

3V3.

AL

E_E

M_A

1

3V3.

SM

_C

Ez

3V

3.C

LE

_EM

_A2

3V

3.R

EA

D_O

E3

V3

.WA

IT/B

US

Y

3V

3.E

M_D

03

V3

.EM

_D1

3V

3.E

M_D

23

V3

.EM

_D3

3V

3.E

M_D

43

V3

.EM

_D5

3V

3.E

M_D

63

V3

.EM

_D7

SM

.xD

.WP

3V

3.W

RIT

E_W

E3

V3.

AL

E_

EM

_A1

3V

3.R

EA

D_O

E3

V3.

SM

_C

Ez

3V

3.W

AIT

/BU

SY

3V

3.C

LE_

EM

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2

SM

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3V

3.E

M_D

73

V3

.EM

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3V

3.E

M_D

53

V3

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_D4

3V

3.E

M_D

33

V3

.EM

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3V

3.E

M_D

13

V3

.EM

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VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3V

VC

C_

3.3

V

VC

C_

3.3V

3V

3.S

M.S

M_C

Ez

153V

3.S

M.R

EA

D_O

E15

3V

3.S

M.W

RIT

E_

WE

153

V3.

SM

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E_

EM

_A1

153

V3.

SM

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_E

M_

A2

15

3V

3.E

M_

D[0

:15]

14,

18,1

9

3V

3.S

M.W

AIT

/BU

SY

15

SM

.CD

28

xD.C

D28

SM

.xD

.WP

28

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

517

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

SM

/xD

CO

NN

EC

TO

R

Chant

Sincere SM/xD Connector

ADD INLINE RESISTORS HERE

J15

SM

/xD

_C

ON

NE

CT

OR

SM

.I/O

1S

MC

6

SM

.I/O

2S

MC

7

SM

.I/O

3S

MC

8

SM

.I/O

4S

MC

9

SM

.I/O

5S

MC

13

SM

.I/O

6S

MC

14

SM

.I/O

7S

MC

15

SM

.I/O

8S

MC

16

SM

.CLE

SM

C2

SM

.ALE

SM

C3

SM

.WE

SM

C4

SM

.WP

SM

C5

SM

.OP

TIO

NS

MC

18

SM

.R/B

SM

C19

SM

.RE

SM

C20

SM

.CE

SM

C21

xD.V

CC

2X

D20

SM.VSS1SMC1

SM.VSS2SMC10

SM.LVDSMC17

SM.VCC2SMC22

SM

.CD

SM

C11

SM.SENS.1 SMCSW1

SM.25 SMCWP1SM.26 SMCWP2

SM.SENS.2 SMCSW2

xD.C

DX

D1

xD.C

LEX

D5

xD.A

LEX

D6

xD.W

EX

D7

xD.W

PX

D8

xD.R

/BX

D2

xD.R

EX

D3

xD.C

EX

D4

xD.V

SS

1X

D9

xD.I/

O0

XD

10

xD.I/

O1

XD

11

xD.I/

O2

XD

12

xD.I/

O3

XD

13

xD.I/

O4

XD

14

xD.I/

O5

XD

15

xD.I/

O6

XD

16

xD.I/

O7

XD

17

SM.VCC1SMC12

xD.V

CC

1X

D18

xD.V

SS

2X

D19

R1

06

10K

R7

7N

O-P

OP

R1

07

10K

RN

23

100K

1234

678

5

R7

810

K

R7

610

K

RN

22

100

K

1234

678

5

+C

91

0u

F


A-19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AT

A_

DA

SP

n

AT

A_

CS

EL

AT

A.D

D0

AT

A.D

D1

AT

A.D

D2

AT

A.D

D3

AT

A.D

D4

AT

A.D

D5

AT

A.D

D6

AT

A.D

D7

AT

A.D

D8

AT

A.D

D9

AT

A.D

D1

0A

TA

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11

AT

A.D

D1

2A

TA

.DD

13

AT

A.D

D1

4A

TA

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15

3V

3.E

M_D

4

3V

3.E

M_D

63

V3.

EM

_D5

3V

3.E

M_D

23

V3.

EM

_D1

3V

3.E

M_D

0

3V

3.E

M_D

3

3V

3.E

M_D

7

3V

3.E

M_D

15

3V

3.E

M_D

93

V3.

EM

_D1

03

V3.

EM

_D1

13

V3.

EM

_D1

2

3V

3.E

M_D

8

3V

3.E

M_D

13

3V

3.E

M_D

14

AT

A.D

D0

AT

A.D

D1

AT

A.D

D2

AT

A.D

D3

AT

A.D

D4

AT

A.D

D5

AT

A.D

D6

AT

A.D

D7

AT

A.D

D8

AT

A.D

D9

AT

A.D

D10

AT

A.D

D11

AT

A.D

D12

AT

A.D

D13

AT

A.D

D14

AT

A.D

D15

AT

A.D

D[0

:15

]

AT

A.D

A0

AT

A.D

A1

AT

A.D

A2

AT

A.D

MA

CK

AT

A.C

S0

AT

A.C

S1

AT

A.D

IOR

AT

A.D

IOW

AT

A.D

MA

RQ

AT

A.I

NT

RQ

AT

A.D

MA

RQ

AT

A.I

OR

DY

AT

A.I

NT

RQ

AT

A_R

ES

ET

n

AT

A_R

ES

ET

n

AT

A.I

OR

DY

AT

A.C

S1

AT

A.C

S0

AT

A.D

IOR

AT

A.D

IOW

AT

A.D

MA

CK

AT

A.D

A0

AT

A.D

A2

AT

A.D

A1

VC

C_5

V

VC

C_

5V

VC

C_

5V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3.3

V

VC

C_

3.3

V

3V3

.AT

A.D

A2

15

3V

3.A

TA

.CS

115

3V3

.EM

_D

[0:1

5]1

4,1

7,1

9

3V

3.A

TA

.DA

015

3V

3.A

TA

.DA

115

3V

3.A

TA

.CS

015

3V

3.A

TA

.DIO

R15

3V

3.A

TA

.DIO

W15

3V

3.A

TA

.DM

AR

Q15

3V

3.A

TA

.IN

TR

Q_E

M_R

NW

15

3V

3.A

TA

.WA

IT/B

US

Y15

3V

3.A

TA

_RE

SE

Tn

15

3V

3.A

TA

_BU

FF

_DIR

15

3V

3.A

TA

_BU

FF

_E

Nz

15

3V

3.A

TA

.DM

AC

K15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

518

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

AT

A I

NT

ER

FA

CE

KEY

NC

IOCS16

DIR BUS

L B->A

H B<-A

MOUNTING HOLES TP

34T

ES

T P

OIN

T1

R1

5410

K

R40

1N

O-P

OP

R5

73

3

Z7

1

C8

6.1

uF

R5

533

R1

538

2

R1

12

10K

R4

52

2

R15

51K

R1

5633

C1

01

.1u

F

RN

4R

PA

CK

8-3

31 2 3 4 5 6 7 8

910111213141516

R1

50

82

C8

7.1

uF

R1

582

0K

DS

10

LE

D,G

RN

R1

578

2

R5

83

3

RN

1R

PA

CK

8-3

31 2 3 4 5 6 7 8

910111213141516

R2

232K

R1

485

.6K

U9

SN

74

LVT

162

45B

/SN

74C

B3

Q1

624

5

Vcc

7

Vcc

18V

cc31

Vcc

42

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1OE

48

1DIR

1

2OE

25

2DIR

24

GN

D4

GN

D10

GN

D15

GN

D21

GN

D28

GN

D34

GN

D39

GN

D45

R4

40

JP1

HE

AD

ER

22X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

R4

83

3

Z8

1C

10

3.1

uF

Z9

1

R5

633

R4

72

2

TP

33T

ES

T P

OIN

T1

R4

62

2

Z6

1



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CF

_A

2C

F_

A1

CF

_A

0

3V

3.E

M_D

15

3V

3.E

M_D

14

3V

3.E

M_D

13

3V

3.E

M_D

12

3V

3.E

M_D

11

3V

3.E

M_D

10

3V

3.E

M_D

93

V3.

EM

_D8

3V

3.E

M_D

73

V3.

EM

_D6

3V

3.E

M_D

53

V3.

EM

_D4

3V

3.E

M_D

33

V3.

EM

_D2

3V

3.E

M_D

13

V3.

EM

_D0

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_3

.3V

VC

C_

3.3

V

3V

3.C

F_

CD

128

3V

3.C

F_

CD

2283V

3.E

M_

D[0

:15]

14

,17

,18

3V

3.C

F_R

ES

ET

z283

V3

.CF

.WA

IT/B

US

Y15

3V

3.C

F.A

TA

0_E

M_

BA

015

3V

3.C

F.A

TA

1_E

M_

BA

115

3V

3.C

F.A

TA

2_E

M_A

015

3V

3.C

F_

PW

R_

ON

15,2

8

3V

3.C

F.W

RIT

E_

WE

15

3V

3.C

F.R

EA

D_

OE

15

3V3

.CF

.AT

A_

CS

015

3V3

.CF

.AT

A_

CS

115

3V

3.C

F.I

NT

RQ

_EM

_R

NW

15

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

519

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

CO

MP

AC

T F

LA

SH

CO

NN

EC

TO

R

+

C1

61

0u

FC

15

.1u

F

R2

810

0K

U1

0 FD

C6

331

L

VIN

4V

OU

T3

VO

UT

2

R1/

C1

6

ON

/OF

F5

R2

1

R2

1

20K

C1

7.1

uF

R2

21K

R2

5

10K

R2

6

20K

R1

10

2K

R2

010

0K

R2

40

R2

310

K

R2

70

R4

00

NO

-PO

P

R1

0910

0K

P1

Co

mp

act

Fla

sh C

on

nec

tor

GN

D1

D03

2

D04

3

D05

4

D06

5

D07

6

CE

17

A10

8

OE

9

A09

10A

0811

A07

12

VC

C13

A06

14A

0515

A04

16A

0317

A02

18A

0119

A00

20D

0021

D01

22

D02

23

WP

24C

D2

25C

D1

26

D11

27

D12

28

D13

29

D14

30

D15

31

CE

232

VS

133

IOR

D34

IOW

R35

WE

36

RD

Y/B

SY

37

VC

C38

CS

EL

39

VS

240

RE

SE

T41

WA

IT42

INP

AC

K#

43

RE

G44

BV

D2

45

BV

D1

46

D08

47

D09

48

D10

49

GN

D50

R1

11N

O-P

OP


A-21

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

S_A

_TX

D

S_A

_RX

DS

_A_R

XD

3V3

.UA

RT

_R

XD

0

UA

RT

_TX

D0

3V3.

UA

RT

_TX

D0

UA

RT

_RX

D0

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3V

VC

C_

1.8

V

VC

C_3

.3V

VC

C_

1.8

V

UA

RT

_TX

D0

6

UA

RT

_R

XD

06

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

520

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

RS

23

2 I

NT

ER

FA

CE

L B-->A

H A-->B

DIR FUNCTION

R3

560

L46

1u

H

+C

299

1u

F

C2

94

10

pF

+C

298

1u

F

U6

4M

AX

3221

DIN

11

INV

ALI

D10

RO

UT

9

C1+

2

C1-

4

V+

3

VCC 15

GND 14

V-

7

C2-

6

C2+

5

RIN

8

EN

AB

LE1

FO

RC

EO

FF

16

DO

UT

13

FO

RC

EO

N12

C2

43

.1u

F

R3

57

10

U43

SN

74A

VC

1T4

5

A1

3

VC

CB

6V

CC

A1

GN

D1

2

B1

4

DIR

5

R3

5410

K

L54

BL

M2

1PG

221S

N1D

12

C2

97

10p

F

+

C29

61

uF

C2

45

.1u

F

L47

1u

H

L55

BL

M2

1PG

221S

N1D

12

C3

01.1

uF

R3

5510

K

+C

302

1u

F

C3

00

10

pF

C2

95

10

pF

+C

77

47

uF

C24

6.1

uF

U42

SN

74A

VC

1T4

5

A1

3

VC

CB

6V

CC

A1

GN

D1

2

B1

4

DIR

5

C2

44

.1u

F

P6

DS

UB

9-M

ale594837261

1011



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

US

B_

DP

US

B_

SH

IEL

D

US

B_

DM

US

B_

SH

IELD

US

B_

SH

IELD

US

B_

SH

IELD

US

B_

SH

IELD

VC

C_

5V

VC

C_

5V

VC

C_

3.3

V

VC

C_

3.3

V

US

B_D

M7

US

B_

DP

7

US

B_

VB

US

7

US

B_

ID7

US

B.D

RV

VB

US

z2

8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

C

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

521

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

US

B 2

.0 I

NT

ER

FA

CE

THESE FOOTPRINTS ARE OVERLAYED

ONLY 1 OF 3 IS POPULATED AT 1 TIME

Selects Termination

for

Host/Client

configurations

STUB TO R337 AND JUMPER NEED TO BE MINIMUM

0.1 TO 0.2 INCHES MAX

MINI A-B CONNECTOR

FULL

SIZE B CONNECTOR

FULLSIZE A CONNECTOR

For host mode Capacitor Minimum Capacitance

is 100uF, this design uses 104.7uF

both

C133 and C69 installed.

For Peripheral or OTG the

Capacitancer should be 4.7 uF

so remove R132 thus C69 provides capacitanceR3

7710

0K

+

C1

331

00u

F

+

C6

94

.7u

F

C3

50.1

uF

J7 HE

AD

ER

3

1 2 3

C2

93

10

0nF

TP

591

L53

BLM

21P

G22

1SN

1D

12

TP

601

J10

B

US

B-m

iniA

B/A

/B c

onn

ect

or

AT

TA

CH

1B

D-

2B

D+

3B

GN

D4B

SH

IELD

11

SH

IELD

22

D6

NO

-PO

P

R3

79

NO

-PO

P

S D

GQ2

IRLM

L64

01

R37

810

K

L52

BLM

21P

G22

1SN

1D

12

J10

C

US

B-m

iniA

B/A

/B c

onn

ect

or

VB

US

-A1A

D-

2A

D+

3A

GN

D4A

SH

IELD

33

SH

IELD

44

R3

371

.5K

U5

9S

N7

4A

HC

1G

08

1 24

5 3

R1

330

C3

51.1

uF

R1

320

J10

A

US

B-m

iniA

B/A

/B c

on

nec

tor

VB

US

1AB

D-

2AB

D+

3AB

GN

D5A

B

SHIELD5 5

ID4A

B

SHIELD6 6

SHIELD7 7

SHIELD8 8


A-23

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LXT

_RD

M

LXT_TDCT

LXT

_TD

P

MII

_R

XD

V

MII

_C

RS

XS

PD

O_

MD

IO

MII

_RX

D3

MII

_R

CL

K

MII_

TX

CLK

RB

IAS

MII

_RD

X2

MT

XD

3LX

T_R

DP

_c

MII

_RX

D1

MT

XE

N

MT

XD

2M

TX

D1

LXT

_RD

M_c

MII

_RX

D0

MD

INT

_T

P

MT

XD

0

PW

RD

WN

SL

EE

P

MII

_C

OL

SY

S_

RS

Tz

MII

_R

XE

R

XS

PC

LK

_M

DC

LK

PA

US

ET

XS

LEW

1T

XS

LEW

0

LXT

_RD

P

MT

XD

3M

TX

EN

MT

XD

0

EN

ET

_E

NA

BLE

z

EN

ET

_E

NA

BLE

z

LIN

KL

ED

-

LED

1-

MT

XD

1M

TX

D2

LXT

_TD

M

PW

RD

WN

TX

SLE

W0

SL

EE

PP

AU

SE

TX

SLE

W1

LED

1-

LIN

KL

ED

-

AV

CC

3.3

AV

CC

3.3

AV

CC

3.3

VC

C_

3.3V

VC

C_3

.3V

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

EN

ET

_EN

AB

LEz

31

GIO

V33

_06

,31

GIO

V33

_26

,31

GIO

V33

_46

,31

GIO

V33

_66

,31

GIO

V33

_86

,31

GIO

V33

_10

6,3

1G

IOV

33_1

26

,31

GIO

V33

_14

6,3

1

GIO

V33

_16

6,3

1

GIO

V33

_16,

31

GIO

V33

_36

,31

GIO

V33

_56

,31

GIO

V33

_76

,31

GIO

V33

_96

,31

GIO

V33

_11

6,3

1

GIO

V33

_13

6,3

1

GIO

V33

_15

6,3

1

3V3

.SY

S_R

ES

ET

z1

5,2

4,2

8,31

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

522

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

ET

HE

RN

ET

IN

TE

RF

AC

E

DUPLEX

STATUS

Pla

ce te

rmin

atio

ns

clos

e to

PH

Y s

our

cepi

ns.

COLLISION/

LINK/

SPEED

ACTIVITY

Ro

ute

pair

s to

geth

er,

pair

s ar

e (3

an

d 6

) an

d(1

an

d 2)

.

R2

75

100

R3

584

9.9

R2

88

49.9

R2

2236

0

L32

BLM

41P

750S

PT R

26

222

R2

851

0k

C2

58

.1uF

R2

74

0E

IA0

402

C2

57

0.0

1uF

C2

481

0p

F

C2

26

.1u

F

R2

871

0k

C2

62

.1u

FR

27

610

0

R2

821

0k

R2

89

0

L56

BLM

21P

G2

21S

N1D

12

R27

710

0

L31

EX

C-3

BB

102

H

1 2

C30

3

.1u

FR

279

10

kR

278

10

k

C3

04

270

pF

R2

831

0k

R2

57

0E

IA0

402

R2

60N

O P

OP

L57

BLM

21P

G2

21S

N1D

12

Y6

25M

Hz

C2

59

.1u

F

R4

07

10K

C2

60 2

70p

F

TP

58M

DIN

T

RN

34

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

C2

641

0p

F

R2

80

1.5

k

R2

86N

O P

OP

C2

63

0.0

1u

F

R2

61

22

R2

81N

O P

OP

R2

58

NO

-PO

P

U5

8

LXT

971A

LE

TX

_CLK

55

TX

D0

57

TX

D1

58

TX

D2

59

TX

D3

60

TX

_EN

56

TX

_ER

54

CO

L62

CR

S63

RX

_CLK

52

RX

D0

48

RX

D1

47

RX

D2

46

RX

D3

45

RX

_DV

49

RX

_ER

53

MD

DIS

3

MD

C43

MD

IO42

MD

INT

#64

TD

I27

TD

O28

TP

FO

P19

TP

FO

N20

TP

FIP

23

TP

FIN

24

LED

/CF

G1

38

LED

/CF

G2

37

LED

/CF

G3

36

AD

DR

012

AD

DR

113

AD

DR

214

AD

DR

315

AD

DR

416

XO

2R

EF

CLK

/XI

1

PW

RD

WN

39

RB

IAS

17

TE

ST

135

RE

SE

T#

4

TE

ST

034

VC

CA

22

GN

D25

SD

/TP

#26

GND1 7

GND2 11

GND3 18

GND4 41

GND5 50

GND6 61

VCCD51

VCCIO18

VCCIO240

VCCA21

TM

S29

TC

K30

TR

ST

#31

TxS

LEW

05

TxS

LEW

16

PA

US

E33

SLE

EP

32

N/C

19

N/C

210

N/C

344

P2

RJ4

5 H

ALO

HF

J11

-245

0E

-L2

1

TX

D-C

T4

NC

17

GN

D8

TX

D+

1

TX

D-

2

RX

D+

3

RX

D-

6R

XD

-CT

5

S0 14S1 13

LED

1+9

LED

1-10

LED

2-12

LED

2+11

C2

47.1

uF

U4

1C

BT

LV

162

10D

GG

R

2OE

47

1OE

48

1A1

2

2A1

13

1B1

46

2B1

35

GND 8GND 17GND 32GND 41

VCC15

1A2

3

1A3

4

1A4

5

1A5

6

1A6

7

1A7

9

1A8

10

1A9

11

1A10

12

2A2

14

2A3

16

2A4

18

2A5

19

2A6

20

2A7

21

2A8

22

2A9

23

2A10

24

NC

1

1B2

45

1B3

44

1B4

43

1B5

42

1B6

40

1B7

39

1B8

38

1B9

37

1B10

36

2B2

34

2B3

33

2B4

31

2B5

30

2B6

29

2B7

28

2B8

27

2B9

26

2B10

25

R2

59

360

R2

842

2.1

k

C2

61

.1u

F



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TV

P51

46V

IDE

O4

TV

P51

46V

IDE

O3

TV

P51

46V

IDE

O2

TV

P51

46V

IDE

O1

TV

P51

46V

IDE

O0

TV

P51

46V

IDE

O6

TV

P51

46V

IDE

O7

TV

P51

46V

IDE

O5

YI0

YI1

YI2

YI3

YI4

YI5

YI6

YI7

B.Y

I0B

.YI1

B.Y

I2B

.YI3

B.Y

I4B

.YI5

B.Y

I6B

.YI7

VC

C_

3.3

VV

CC

_1.

8V

VC

C_

1.8

V

TV

P5

14

6VID

EO

[0:7

]24

TV

P51

46

HS

YN

C2

4T

VP

51

46

VS

YN

C2

4T

VP

5146

PC

LK24

YI3

5,3

0Y

I45

,30

YI5

5,3

0

YI7

5,3

0

YI0

5,3

0Y

I15

,30

HD

5,3

0V

D5

,30

CA

PT

UR

E_

EN

30

YI2

5,3

0

1.8

V_

DC

3_P

CL

K31

YI6

5,3

0

PC

LK

5,3

0

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

523

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

TV

P51

46

LE

VE

L S

HIF

TE

R

DIR BUS

L B->A

H B<-A

U66 is a tri-stateable logic translator used for DC4

to allow the TVP5146 to be disconnected

from on-board circuitry.Signal levels are at 1.8V logic

levels on B side and 3.3V on A sides of translator.

RN

32

RP

AC

K4

-33

12345 6 7 8

RN

33

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

R2

26

0

R2

31

0

C6

70

.1u

F

R2

64

10K

C6

20

.1u

F

R6

436

0C6

80

.1uF

U6

6

SN

74

AV

CB

164

245

VR

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

1DIR

1

1OE

n48

2DIR

24

2OE

n25

VC

CB

7

VC

CB

18V

CC

A42

VC

CA

31

GN

D28

GN

D34

GN

D39

GN

D45

GN

D4

GN

D10

GN

D15

GN

D21

C6

10

.1u

F


A-25

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LU

MA

TV

P5

146

VID

EO

4T

VP

514

6V

IDE

O3

TV

P5

146

VID

EO

1T

VP

514

6V

IDE

O0

TV

P5

146

VID

EO

6T

VP

514

6V

IDE

O7

TV

P5

146

VID

EO

5

TV

P5

146

VID

EO

2

3.3

VA

_D

DE

C3

.3V

D_

DD

EC

1.8

VD

_D

DE

C

3.3

VD

_D

DE

C

3.3

VA

_D

DE

C

3.3

VD

_D

DE

C

1.8

VA

_D

DE

C

3.3

VD

_D

DE

C

3.3

VD

_D

DE

C

1.8

VD

_D

DE

C

1.8

VA

_D

DE

C

3.3

VA

_D

DE

C

3.3

VD

_D

DE

C1

.8V

D_

DD

EC

1.8

VA

_D

DE

CV

CC

_1.

8V

VC

C_

3.3

V

VC

C_

1.8

VV

CC

_3

.3V

3V

3.S

YS

_R

ES

ET

z1

5,2

2,2

8,3

1

TV

P5

146

VID

EO

[0:7

]23

TV

P5

14

6V

SY

NC

23

TV

P5

146P

CLK

23

TV

P51

46

HS

YN

C23

3V

3.I

2C

_C

LK

6,2

7,2

83V

3.I

2C

_D

AT

A6

,27

,28

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

524

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

TV

P5

146

VID

EO

DE

CO

DE

R

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

DDEC_GND

C28

6

0.1

uF

C3

37

0.1

uF

C3

67

33

0pF

L39

2.7

uH

Y4 14

.318

18m

hz

C3

47

0.1

uFR

328

NO

PO

P

C3

446

80p

F

C3

323

30

pFC

325

68

0pF

L43

2.7

uH

C3

42

33

0pF

R2

65

4.7

K

C3

38

33

0pF

L41

2.7

uH

C3

46

0.1

uF

C2

92

33

pF

R3

360

J12

RC

A J

AC

K

1

2

C3

68

33

0pF

R3

30

2K

L38

BLM

41P

750S

PT

12

C3

43

.1u

F

C3

29

0.1

uF C

287

0.1

uF

R3

7675

R3

3522

L44

2.7

uH

R3

33

4.7

K

C2

84

0.1

uF

C3

35

0.1

uF

J11

7491

81-1

34 2

1

56

L40

2.7

uH

TP

62

1

C2

88

0.1

uF

R3

27

NO

PO

P

C3

39

.1u

F C3

33

.1uF

C2

50

0.1

uF

L42

2.7

uH

C3

31

0.1

uF

R3

34

2.2

K

C3

41

0.1

uFR

329

2K

R2

66

22

C29

0

0.1

uF

TP

561

U5

1T

VP

514

6

VI_

3_B

17

VI_

3_A

16

VI_

2_B

8

VI_

2_C

9

Y8

44Y

943

Y7

45

TH

ER

MA

L81

CH3_A18GND 15

CH4_A18GND 24

CH1_A18GND 79

DGND4 56

CH1_A33GND 3

CH3_A33GND 19CH2_A33GND 6

VI_

3_C

18

VI_

4_A

23

Y2

52Y

351

Y6

46

CH4_A33GND 22

DGND2 32

DGND3 42

IOGND1 39

IOGND2 49

IOGND3 62

PLL_A18GND 77

DGND1 27

DGND5 68

A18GND_REF 13AGND 26

CH2_A18VDD11

CH3_A18VDD14

CH4_A18VDD25

CH1_A18VDD78

CH1_A33VDD4

CH2_A33VDD5

CH3_A33VDD20

CH4_A33VDD21

A18VDD_REF12

DVDD131

DVDD241

DVDD355

DVDD467

IOVDD138

IOVDD248

IOVDD361

PLL_A18VDD76

VI_

2_A

7

VI_

1_C

2

VI_

1_B

1

VI_

1_A

80

SC

L28

SD

A29

Y5

47

Y4

50

Y1

53

Y0

54

C9

57

C8

58

C7

59

C6

60

C5

63

C4

64

C3

65

C2

66

C1

69

C0

70

XT

AL1

74

XT

AL2

75

DA

TA

CLK

40

RE

SE

TB

34

PW

RD

WN

33

INT

RE

Q30

FS

S/G

PIO

35

GLC

O/1

2CA

37

HS

/CS

/GP

IO72

VS

/VB

LK/G

PIO

73

FID

/GP

IO71

AV

ID/G

PIO

36

CH2_A18GND 10

C3

45

0.1

uF

C2

85

0.1

uF

C3

263

30pF

L28

BLM

41P

750S

PT

12

C3

40

68

0pF

C3

28

.1u

F

C3

34

0.1

uF

RN

35

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

C3

30

0.1

uF

C3

27

0.1

uF

L37

BLM

41P

750

SP

T1

2

C3

48

0.1

uF

R3

74

75

TP

571

R3

32

100

K

L23

BLM

41P

750

SP

T1

2

C2

89

.1u

F

C2

91

0.1

uF

C2

83

0.1

uF

C3

36

0.1

uF

C3

49

33p

F

R3

3122

R3

75

75



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VO

UT

_ON

VO

UT

_ON

VO

UT

_ON

3V3A

_VO

UT

VO

UT

_ON

VC

C_

3.3

VD

AC

_3V

3

DA

C_3

V3

DA

C_3

V3

DA

C_

3V

3

DA

C_

3V

3

DA

C_

3V

3

DA

C_

IOU

TA

5

DA

C_

IOU

TB

5 DA

C_

IOU

TD

5

DA

C_

IOU

TC

5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

525

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

VID

EO

OU

TP

UT

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

1812LS-273XJB

1812LS-273XJB

1812LS-273XJB

1812LS-273XJB

1812LS-273XJB

1812LS-273XJB

1812LS-273XJB

1812LS-273XJB

L12

BLM

41P

750

SP

T

C3

550

.1u

F

R3

431

130

1%

R3

481K

R3

5075

L36

1u

H

-+

U4

8

OP

A3

57A

IDB

V

3 4

526

1

C36

3

10

pF

-+

U5

0

OP

A3

57A

IDB

V

3 4

526

1

R3

45

26

7 1

%

R3

471

130

1%

J974

918

1-1

34 2

1

56

C3

61

10

pF

L27

12

uH

L35

1u

H

R3

521K

C2

52

27

pF

-+

U4

9

OP

A3

57A

IDB

V

3 4

526

1

C3

590

.1u

F

C2

53

27

pF

R33

875

L25

12

uH

C3

62

10

pF

R3

391

130

1%

R3

4675

R27

01K

L19

12

uH

R3

511

130

1%

L18

12

uH

R3

4275

C35

4

10

pF

C3

52

0.1

uF

C3

60

10p

F

C3

580

.1u

F

R3

49

26

7 1

%

R3

81

NO

-PO

P

R27

21K

L26

12

uH

C2

54

27

pF

+C

63

10

uF

C35

7

10

pF

C2

51

27

pF

C2

560

.1u

F

R2

71

1KR

269

1K

C3

53

10

pF

C3

56

10

pF

L33

1u

H

-+

U4

7

OP

A3

57A

IDB

V

3 4526

1

+C

64

220

uF

L20

12

uH

R3

401K

R3

80

10K

C25

50

.01

uF

R3

441K

R3

412

67

1%

L17

12

uH

L34

1u

H

L16

BLM

41P

750S

PT

R3

53

26

7 1

%

L24

12

uH

J8

DU

AL

RC

A J

AC

K

2

1

3

4

5 6


A-27

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

1.8

V

B_

CL

KR

7

B_

FS

R7

B_

DR

7

B_D

X7

B_F

SX

7

B_C

LKX

7

1V

8.I

2C

_DA

TA

6,3

0,3

1

1V8

.I2

C_

CL

K6,

30

,31

AU

DIO

_C

LK

5,3

1

1.8

V.S

YS

_RE

SE

Tz

8,1

3,1

5,2

9,3

0,3

1,3

4

Siz

e:

Da

te:

DW

G N

OR

ev

isio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

508

162

-000

1

We

dn

esd

ay,

Nov

em

be

r 1

6,

20

05

2635

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

AIC

33

AU

DIO

IN

TE

RF

AC

E

MIC_IN

LINE_IN

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

C2

79.1

uF

P4

He

ad

pho

ne O

ut

3421

TP

631

R3

71

330

P5

DU

AL

RC

A J

AC

K

2

1

3

U5

2

TV

L3

20A

IC33

IZQ

E

HP

LOU

TD

1

HP

LCO

ME

1

LIN

E1R

+B

7

LIN

E1R

-B

6

LIN

E2L

+A

4

LIN

E2L

-B

5

MIC

BIA

SA

2

WC

LKF

9

DO

UT

F8

MP

F2

A8

MC

LKG

8

SE

LEC

TE

8

SD

AD

8

RIG

HT

_LO

+J6

DR

VS

S.1

E2

DR

VS

S.2

F2

GP

IO2

J8

LEF

T_L

O+

J4

LEF

T_L

O-

J5

MO

NO

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5 5

4 4

3 3

2 2

1 1

DD

CC

BB

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3.3

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SP

EC

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UM

DIG

ITA

L IN

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RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

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vem

ber

16,

20

05

273

5

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

SP

DIF

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TP

UT

S &

US

ER

LE

DS

L B-->A

H A-->B

DIR FUNCTION

USER CONTROLLED LEDS

SPDIF OUT

OPTICAL SPDIF OUT

C3

06

0.1

uF

R7

133

0R

66

330

C30

9

0.1

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DS

5

LE

D

DS

1

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D

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330

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D

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D

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A J

AC

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1

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3

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74

AV

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45

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2

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CC

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GN

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4

B1

7

B2

6A

23

DIR

5

R3

61

0

R7

033

0

DS

7

LE

D

R35

91

00

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PC

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574

A

GN

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7

A0

1

A1

2

A2

3

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4

P2

6P

15

VD

D16

SD

A15

SC

L14

INT

13

P7

12

P6

11

P5

10

P4

9

C30

8.1

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3

SN

74L

VC

1G

125

3

4

5

2

1

R6

833

0

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0.1

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233

0

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VC

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GN

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IN3

MP1 4

MP2 5

DS

3

LE

D

DS

2

LE

D

R3

62

100K

R3

60

220

U6

1

SN

74L

VC

1G

125

3

4

5

2

1


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5 5

4 4

3 3

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CC

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430

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TC

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MS

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C_

3.3

V

VC

C_

3.3

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VC

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VC

C_

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VC

C_3

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C_

1.8

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VC

C_

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VC

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3V

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6,2

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3V

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2,2

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3V

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119

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219

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6,2

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73

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5,3

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SD

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P16

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16M

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16 3

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15

VL

YN

Q_

ON

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VD

DIM

X_E

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US

B.D

RV

VB

US

z21

SM

.CD

17

3V

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ON

15,1

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17

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ET

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3.I

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24

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MS

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INT

15

PL

L.F

S1

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LL

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5

PL

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3V

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ET

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0

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115

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AR

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215

SP

AR

EIO

315

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e:

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te:

DW

G N

OR

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sio

n:

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of

Titl

e:

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ge

Co

nte

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:

C

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

528

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

MS

P4

30

& I

R I

NT

ER

FA

CE

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4.1

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C1

93.1

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123

2IP

W

VCC2

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0/A

CLK

8

P2.

1/IN

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9

XIN

6

XO

UT

5

VSS 4

P1.

0/T

AC

LK21

TE

ST

1

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2/C

AO

UT

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010

RS

T/N

MI

7

P1.

1/T

A0

22

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2/T

A1

23

P1.

3/T

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24

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4/S

MC

LK/T

CK

25

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5/T

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TM

S26

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6/T

A1/

TD

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7/T

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TD

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3/C

A0/

TA

119

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4/C

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TA

220

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5/R

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C3

P3.

0/S

TE

0/A

511

P3.

1/S

IMO

012

P3.

2/S

OM

I013

P3.

3/U

CLK

014

P3.

4/U

TX

D0

15

P3.

5/U

RX

D0

16

P3.

6/A

617

P3.

7/A

718

R4

2210

K

Y1

32.7

68K

Hz

U3

0S

N7

4LV

C1G

06

3

4

5

2 1

U3

TS

OP

3484

0

23 1

C8

5

0.1

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R2

24

10K

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BA

T17

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6N

O-P

OP

R1

0510

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63

0.1

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C1

00.1

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11

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F 6

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80

R1

90N

O-P

OP

C1

64

0.1

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R7

510

0

U3

5

PC

F8

574

A

GN

D8

P3

7

A0

1

A1

2

A2

3

P0

4

P2

6P

15

VD

D16

SD

A15

SC

L14

INT

13

P7

12

P6

11

P5

10

P4

9

+C

13

10

uF

6.3

V

R7

410

K

BH

T1

BA

203

2SM

2 1

U1

8

PC

F85

74A

GN

D8

P3

7

A0

1

A1

2

A2

3

P0

4

P2

6P

15

VD

D16

SD

A15

SC

L14

INT

13

P7

12

P6

11

P5

10

P4

9

C83

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F

R10

110

K

L1

BLM

41P

750

SP

T

R1

030

R9

7N

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2N

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D3

BA

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7

RN

25

RP

AC

K4

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12345

678

J2

HE

AD

ER

7X

2

TD

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1N

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DI/V

PP

3V

CC

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TM

S5

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UT

6T

CK

7T

ES

T/V

PP

8G

ND

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CLK

10R

ST

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AC

LKE

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NC

113

TC

LKE

N14

R1

04

47K

TP

41

U15

SN

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C1G

32

1 24

5 3

R4

21N

O-P

OP

R2

73

0



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B.E

M_A

16B

.EM

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B.E

M_A

12

EM

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B.E

M_A

14

B.E

M_A

21

EM

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EM

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EM

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B.E

M_A

11

EM

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B.E

M_A

17

B.E

M_A

10

EM

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B.E

M_A

13

B.E

M_A

19

B.E

M_A

15

B.E

M_A

20

EM

_A4

EM

_D14

EM

_D10

EM

_D12

EM

_D8

EM

_D4

EM

_D6

EM

_D2

EM

_D0

EM

_D15

EM

_D11

EM

_D13

EM

_D9

EM

_D5

EM

_D7

EM

_D3

EM

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VC

C_

1.8

VV

CC

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V

VC

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3.3

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CC

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V

EM

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[3:2

1]3

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[0:1

5]

3,1

2,1

3,1

4

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5 WR

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13,1

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3,15

INT

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RN

W3

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AT

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03

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A_C

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AL

E_E

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13

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3,1

2,1

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TA

2_E

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5

DC

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M_C

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10

WA

IT/B

US

Y3

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33

CL

KO

UT

08

B.E

M_

A[1

0:21

]12

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1.8

V.S

YS

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ES

ET

z8

,13

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,26

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,31,

34

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

529

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

EM

IF E

XP

AN

SIO

N C

ON

NE

CT

OR

EMIF CONNECTOR

DC

1

HE

AD

ER

35x

2

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

4545

4747

4949

5151

5353

5555

5757

5959

6161

6363

6565

6767

6969

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

5454

5656

5858

6060

6262

6464

6666

6868

7070


A-31

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_1

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VC

C_

1.8

V

VC

C_

1.8

VV

CC

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V

VC

C_

5VV

CC

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V

VC

C_

5V

VC

C_

5V

VC

C_

3.3

VV

CC

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V

VC

C_

3.3

VV

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3V

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36

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66

CO

UT

05

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CO

UT

25

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06

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45

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26

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56

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10

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10

HS

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UT

75

CO

UT

55

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UT

15,

10

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UT

35,

10

YO

UT

55

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UT

75

YI0

5,2

3

YI6

5,2

3

CI0

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PC

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3

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5,2

3Y

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YI1

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23

YI7

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34

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YS

_R

ES

ET

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,13

,15

,26

,29

,31,

34

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

530

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

VID

EO

IN

PU

T/O

UT

PU

T C

ON

NE

CT

OR

S

VIDEO INPUT CONNECTOR

VIDEO OUTPUT CONNECTOR

R2

68N

O-P

OP

DC

4

HE

AD

ER

25X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

DC

5

HE

AD

ER

25X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

R2

25

NO

-PO

P

R2

67N

O-P

OP



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_5

V

VC

C_

3.3

V

VC

C_

5V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3

.3V

VC

C_

5V

VC

C_

1.8

V

VC

C_

1.8

V

GIO

V3

3_1

6,2

2G

IOV

33

_36

,22

GIO

V3

3_5

6,2

2

GIO

V3

3_7

6,2

2G

IOV

33

_96

,22

GIO

V3

3_11

6,2

2

GIO

V3

3_13

6,2

2G

IOV

33_

156,

22

GIO

V33

_0

6,2

2G

IOV

33_

26

,22

GIO

V33

_4

6,2

2

GIO

V33

_6

6,2

2G

IOV

33_

86

,22

GIO

V33

_10

6,2

2

GIO

V33

_12

6,2

2G

IOV

33_1

46

,22

GIO

V33

_16

6,2

2

SP

I_C

LK

6

CL

KR

7F

SR

7

DR

7

SP

I_D

O6

DX

7,2

7

FS

X7

CL

KX

7

SP

I_E

N0

6S

PI_

DI

6S

PI_

EN

16

SD

_C

LK

7,1

6,3

2 SD

_DA

TA

27

,16

,32

SD

_C

MD

7,1

6,3

2

SD

_DA

TA

17

,16

,32

SD

_DA

TA

37

,16

,32

SD

_DA

TA

07

,16

,32

1V

8.I

2C

_D

AT

A6

,26

,30

EN

ET

_EN

AB

LE

z22

AU

DIO

_C

LK

5,2

61

.8V

_D

C3

_P

CL

K23

McB

SP

_E

N7

1V

8.I

2C

_C

LK6,

26

,30

1.8

V.S

YS

_R

ES

ET

z8

,13

,15

,26

,29

,30,

34

TIM

ER

_IN

_D

C3

15

3V3

.SY

S_

RE

SE

Tz

15

,22,

24,2

8

3V3

.UA

RT

_TX

D1

15

,28

3V

3.U

AR

T_R

XD

11

5,2

8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

We

dn

esd

ay,

No

vem

be

r 1

6,

200

531

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

EM

AC

/GIO

& M

cBS

P/S

PI

& S

D C

ON

NE

CT

OR

S

DC

3

HE

AD

ER

15

X22 4 6 8 10 12 14 16 18 20 22 24 26 28 30

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

DC

2

HE

AD

ER

20X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

DC

6

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9

R2

63N

O-P

OP


A-33

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VL

YN

Q_

RX

D2

VL

YN

Q_

RX

D3

VL

YN

Q_

TX

D3

VL

YN

Q_

TX

D2

VC

C_

3.3

VV

CC

_5V

VC

C_

3.3

V

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1.8

V

SD

_C

LK

7,1

6,3

1

VL

YN

Q_

CL

K3

SD

_DA

TA

07

,16

,31

VL

YN

Q_

SC

RU

N3

SD

_C

MD

7,1

6,3

1

SD

_DA

TA

37

,16

,31

SD

_DA

TA

27

,16

,31

SD

_DA

TA

17

,16

,31

VL

YN

Q_T

XD

01

4

VL

YN

Q_

RX

D0

14

VL

YN

Q_T

XD

11

4

VL

YN

Q_

RX

D1

14

SL

P_

CL

K_E

N14

PM

_E

N14

EL

P_

RE

Q/W

AK

EU

P14

WL

AN

_IN

TR

14

VL

YN

Q_

RX

D3

14

VL

YN

Q_

RX

D2

14

VL

YN

Q_T

XD

214

VL

YN

Q_T

XD

314

1V8

.WLA

N_R

ES

ET

z28

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

532

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

VL

YN

Q I

NT

ER

FA

CE

Resistors are only populated for modules

requiring the upper VLYNQ data pairs

Resistors are only populated for modules

requiring the upper VLYNQ data pairs

+C

23

3uF

R1

2N

O-P

OP

C11

2

0.1

uF

R1

5N

O-P

OP

R1

70

R3

99

NO

-PO

P

R1

3N

O-P

OP

R39

81K

C4

0.1

uF

C1

14

0.1

uF

C1

1

0.1

uF

L59

NO

-PO

P

R7

NO

-PO

P

C6

0.1

uFC

3

0.1

uF

L58

BLM

41P

750S

PT

L60

BLM

41P

750S

PT

R1

60

R5

0

R4

09

10K

R1

9N

O-P

OP

R1

00

R9

0

R1

1N

O-P

OP

R3

90

10K

R6

NO

-PO

P

+C

110

33

uF

R4

081

0K

R4

NO

-PO

P

L61

BLM

41P

750

SP

T

R3

91

NO

-PO

P

R3

971

K

J16

mP

CI

LED

1_G

RN

P11

+3.3V.363

LED

1_G

RN

N13

SY

S_A

UD

IO_I

N11

6

+3.3V.440

INT

A20

SY

S_A

UD

IO_O

UT

.GN

D11

7

+3.3V.531

LED

2_Y

ELP

12

AU

DIO

_GN

D.1

119

LED

2_Y

ELN

14

8PM

J-3

3

RS

T26

TIP

1

GN

T30

RIN

G2

PM

E34

AD

3038

8PM

J-1

4

AD

2842

AD

2644

GND.12 37

AD

2446

IDS

EL

48

8PM

J-6

5

AD

2252

AD

2054

GND.14 27

AD

1858

AD

1660

8PM

J-4

8

FR

AM

E64

GND.11 49

TR

DY

66

GND.3 101

ST

OP

68R

ES

ER

VE

D_J

112

AC

_SY

NC

103

AU

DIO

_GN

D.3

120

RE

SE

RV

ED

_H98

PA

R56

AD

1576

RE

SE

RV

ED

_K12

1

AD

1378

AD

1180

GND.2 102

AD

984

C/B

E0

86

RE

SE

RV

ED

_I10

0

AD

690

AD

492

GND.8 62

AD

294

AD

096

RE

SE

RV

ED

_F43

CLK

RU

N65

EM

C1

EM

C1

RE

SE

RV

ED

_A16

+5V.218

M66

EN

104

GND.13 32

SY

S_A

UD

IO_O

UT

115

+3.3V.870

+3.3V.189

INT

B17

AC

_SD

AT

A_I

N10

5

MP

CIA

CT

122

SY

S_A

UD

IO_I

N.G

ND

118

VC

C5V

A12

3

GND.10 50

CLK

25

GND.1 114

RE

Q29

8PM

J-5

10

AD

3133

AD

2935

GND.9 55

AD

2739

AD

2541

RE

SE

RV

ED

_G93

C/B

E3

45

AD

2347

GND.4 83

AD

2151

AD

1953

8PM

J-8

9

AD

1757

C/B

E2

59

GND.15 23

IRD

Y61

+3.3V.288

DE

VS

EL

72

GND.7 69

EM

C4

EM

C4

PE

RR

71

8PM

J-2

6

SE

RR

67

8PM

J-7

7

C/B

E1

73

AD

1475

GND.6 77

AD

1279

AD

1081

EM

C2

EM

C2

AD

885

AD

787

RE

SE

RV

ED

_B21

AD

591

AD

395

GND.5 82

AD

199

EM

C3

EM

C3

CH8GND 15

RE

SE

RV

ED

_E36

RE

SE

RV

ED

_C22

+3.3V.628

+3.3V.719

+3.3VAUX.1124

+3.3VAUX.224

+5V.197

AC

_BIT

_CLK

107

AU

DIO

_GN

D11

3M

OD

_AU

DIO

_MO

N11

1

AC

_CO

DE

C_I

D0#

108

AC

_SD

AT

A_O

UT

106

AC

_CO

DE

C_I

D1#

109

AC

_RE

SE

T#

110

GND.16 74

C7

0.1

uF

C8

0.1

uF

R1

8N

O-P

OP

R1

40

C1

2

0.1

uF

R8

NO

-PO

P

+C

53

3uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CT

I_E

MU

0C

TI_

EM

U1

CT

I_T

CK

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_1

.8V

VC

C_

1.8

VV

CC

_3

.3V

DS

P_

TD

I8

DS

P_T

MS

8

DS

P_

EM

U0

8

DS

P_

EM

U1

8

DS

P_T

RS

T#

8

PO

R_R

ST

z34

DS

P_T

DO

8D

SP

_R

TC

K8

DS

P_T

CK

8

EM

ULA

TO

R_

RS

Tn

34

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

Mo

nd

ay,

Ma

rch

06

, 20

06

333

5

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

DA

VIN

CI

EM

UL

AT

ION

HE

AD

ER

S2/S1 SETTINGS

TI COMPATABLE EMULATOR

S1 1-2

S1 4-5

S2 1-2

S2 4-5

R9

00

R9

233

R8

7N

O-P

OP

R7

910

K

R9

33

9

U1

TP

S38

08G

09

DB

VR

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

R8

6N

O-P

OP

R8

42

.2K

S1

CA

SD

20

TB

1 2 3

4 5 6

R8

32

.2K

J1

20

PIN

CT

I IN

TE

RF

AC

E

SR

ST

15

GN

D.1

8

GN

D.2

10

GN

D.3

12

GN

D.4

16

GN

D.5

20

EM

U0

13E

MU

114

EM

U2

17E

MU

318

TC

LK11

EM

U4

19

KE

Y6

TD

IS4

TD

O7

TD

I3

TR

ST

n2

TM

S1

TV

D5

TC

KR

TN

9

C8

0

NO

-PO

P

R8

80

S2

CA

SD

20T

B

1 2 3

4 5 6

R9

10

C8

10

.1u

F

R8

01

0K

R9

5N

O-P

OP

R8

12

.2K

R94

39

C8

2N

O-P

OP

R8

5N

O-P

OP

R8

90

R8

210

K


A-35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PB

SW

_RS

Tz

VC

C_

5V

AG

ND

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_1.

8V

VC

C_3

.3V

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

DS

P_

CO

RE

_V

DD

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

1.8

V

1.8

V.S

YS

_R

ES

ET

z8

,13

,15

,26

,29

,30

,31

EM

UL

AT

OR

_R

ST

n33

PO

R_

RS

Tz

33

3V3

_PW

R_

OK

35

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5081

62-0

001

We

dn

esd

ay,

No

vem

ber

16

, 2

00

534

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

PO

WE

R S

UP

PL

Y (

3.3

V )

& S

YS

TE

M R

ES

ET

LO

GIC

3.3 sq in AGND,

min

thermal pad

Connect

at pin 1

Sets

Voltage

3.3V @1.5Amp Max

2.5

MM

JA

CK

PO

WE

R IN

PUT

BBB

AAA

SENSE THRESHOLD FOR TPS3808G01 IS 0.405 VOLTS

BOXMOUNTING HOLES

CASE SHIELDING TABS FOR POWER SUPPLY

SENSE THRESHOLD FOR TPS3808G09 IS 0.840 VOLTS

R2

55

1K

Z3

1

+C

19

10

0 u

F

C2

39

NO

-PO

P

U19

TP

S5

431

0PW

P

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

X3

1

TP

14

1

L4

BLM

41P

750S

PT

TP

27

1

C9

782

00p

F

C2

38

0.1

uF

R3

1

71

.5K

1%

X4

1

C2

1

0.0

47

uF

R2

4910

K

C2

41

NO

-PO

P

C2

333

00pF

R2

480

TP70 1

R1

302

K 1

%

X5

1

TP

15

1

TP

5

1

C2

36

1u

F

TP

1 1

R3

03

.74

K 1

%

R2

50

10K

U4

4

TP

S3

808

G0

9DB

VR

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

R2

53

10K

C3

9

0.1

uF

R2

56

0

C2

400

.1u

F

L33

.3 u

H

SW

1S

WIT

CH

3

1

6

4

52 78

TP

68 1

DS

9

GR

EE

N

R1

281

07

1%

R1

291

0K

1%

R2

5210

K

S4

PU

SH

BU

TT

ON

SW

R2

45

33

+C

369

100

uF

4V

C2

24

70

pF

R1

31

10K

+C

24

10

uF

LE

SR

R2

47

10K

U4

5

TP

S3

808

G0

9DB

VR

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

R2

541

0K

TP

2 1

TP

16

1

TP

28

1

C2

6

0.0

39

uF

J6 HE

AD

ER

21 2

C9

9

NO

-PO

P

+C

20

100

uF

4V

Z4

1

C2

42

0.1

uF

+C

1447

uF

Z1

1

D5

BA

S16

-7

C2

5

0.1

uF

J14

RA

SM

712

CE

NT

ER

SH

UN

TS

LEE

VE

Z5

1

TP

3 1

X1

1

U4

6

TP

S38

08G

09D

BV

R

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

Z2

1

R1

00

220

C9

81

000p

F

R2

46

10K

C9

60

.1u

F

X2

1C

23

7

NO

-PO

P

R2

90

.025

R2

51

10K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

1.8

V

AG

ND

AG

ND

DS

P_

CO

RE

_V

DD

VC

C_

5V

VC

C_3

.3V

DS

P_

CO

RE

_V

DD

IMX

VC

C_

5V

VC

C_

5V

VC

C_1

.8V

VC

C_1

.8V

DS

P_

CO

RE

_S

UP

PL

Y

DS

P_

CO

RE

_S

UP

PL

YD

SP

_C

OR

E_

SU

PP

LY

VC

C_

5V

VC

C_

3.3

V

VD

DIM

X_

EN

28

VD

DIM

X_E

N28

3V

3_P

WR

_OK

34

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5081

62-0

001

Mo

nda

y, M

arc

h 0

6,

200

635

35

B

DA

VIN

CI

EV

AL

UA

TIO

N M

OD

UL

E

PO

WE

R S

UP

PL

Y (

1.8

V &

DS

P_

CO

RE

) &

EV

M P

OW

ER

CO

NN

3.3 sq in AGND,

min

thermal pad

Connect

at pin

1

Sets

Voltage

3.3

sq

in A

GN

D,

min

ther

ma

l pad

Co

nn

ect

at

pin

1

1.2V -> 28.0K 1%

1.05V -> 56.0K 1%

CORE VOLTAGE SUPPORT FOR 0.95 TO 1.2 VOLTS

0.95V -> 150K 1%

C5

3

0.0

47

uF

U3

8

TP

S54

310P

WP

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

R3

91

0.2

K 1

%

R38

0.0

25

U37

UM

C2

N

DT

R2C

4D

TR

2E3

DT

R1B

2

DT

R1C

/DT

R2B

6D

TR

1E1

C3

7

0.1

uF

C19

11

000p

F

R1

831

07

1%

+C

33

10

0 u

F

R1

85

1.6

5K 1

%

C1

24

100

0pF

TP

43

1

+C

44

10

uF

LE

SR

R1

461

0K

1%

C1

238

200p

F L11

2.7

uH

C1

92 NO

-PO

P

TP

25

1

C1

22

0.1

uF

C4

33

300

pF

TP

26

1

C3

4

0.0

47

uF

R1

890

C3

63

300

pF

TP

37

1

R1

47

2K 1

%

C4

6

0.0

39

uF

R1

86

10K

+C

50

100

uF

R2

10

NO

-PO

P

C3

54

70pF

R5

90

.02

5

R2

10K

R1

87

NO

-PO

P

C5

6

0.1

uF

+C

51

10

0 u

F

TP

291

R49

28

.0K

1%

TP

441

C3

8

0.0

39

uF

C1

590

.01

uF

C1

61

100

0pF

C4

5

0.1

uF

R1

451

07 1

%

C4

25

60pF

+C

41

10

0uF

4V

U2

7

TP

S54

310P

WP

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

DC

7

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9

R4

0

71

.5K

1%

+C

52

10

0u

F 4

V

L7

BLM

41P

750S

PT

R1

10K

C1

58

0.1

uF

R5

0

71

.5K

+C

32

100

uF

C5

5

0.1

uF

+C

54

10

uF

LE

SR

R18

810

0K

R2

0910

K

TP

361

U3

6A

O34

04

G G

SS

DD

C1

60

NO

-PO

P

R18

41

0K

1%

U3

1A

O34

04

G G

SS

DD

L82

.7 u

H

TP

351

L9

BLM

41P

750S

PT

R4

23

0

B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about the DM644xEVM produced by Spectrum Digital.


B-2 DM644x EVM Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE


B-3


B-4 DM644x EVM Technical Reference

Printed in U.S.A., October 2006508165-0001 Rev C