data sheet - fujitsu...bol pin conditions value unit min typ max power supply current icc vdd...

DS04-29130-1EaFUJITSU MICROELECTRONICSDATA SHEET

ASSP

Multi-output Spread Spectrum Clock Generator

MB88181

DESCRIPTIONThe MB88181 is a multi-output, EMI resistant clock generator that is suitable for applications such as LCD, PDPs,MFPs, and mobile phones. This chip has 8 output pins, of which a maximum of 3 pins can be used to output aspread-spectrum clock.

FEATURES• Built-in PLL : 4

Without spread-spectrum function : 3 (PLL1, PLL2, PLL3) With spread-spectrum function : 1 (SSCG)

• Output setting pins : 2 pins (Able to select from 4 different combinations of output frequency and modulation index) *

• Clock output pins : 8 pins (Spread spectrum clock output : 3 pins (Max) ) *• Input frequency : 16 MHz to 32 MHz• Output frequency : 8 MHz to 166 MHz (4 different combinations of output frequencies are selectable) *• Modulation index setting : selectable from no modulation, ± 0.5%, ± 1.0%, ± 1.5% or ± 2.0%*• Equipped with power down function• Clock output duty cycle : 45% to 55%

* : Set various settings by mask option.(Continued)

Copyright©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved2007.11

MB88181

2

(Continued)• Clock cycle-cycle jitter : Less than100 ps• Low current consumption by CMOS process :

At normal operation : 55 mA (power supply voltage : 3.3 V, normal temperature, no load) At power down : 5 µA (power supply voltage : 3.6 V, normal temperature, no load)

• Power supply voltage : 3.0 V to 3.6 V• Operating temperature : − 40 °C to + 85 °C• Package : TSSOP 20-pin

MB88181

PIN ASSIGNMENT

PIN DESCRIPTION

Pin no. I/O Pin no. Description

XIN I 1 Crystal oscillator connection pin/input pin

SL0 I 2 Frequency/modulation index setting pin 0

SL1 I 3 Frequency/modulation index setting pin 1

CLK9 O 4 Clock output pin 9

VDD 5 Power supply pin

VSS 6 GND pin




VSS 10 GND pin





VSS 15 GND pin


VSS 17 GND pin

XPD I 18 Power down pin (power down when set to “L”)


XOUT O 20 Crystal oscillator connection pin/input pin

XIN

SL0

SL1

CLK9

VDD

VSS

CLK1

CLK2

CLK3

VSS

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

XOUT

VDD

XPD

VSS

VDD

VSS

CLK8

CLK7

CLK6

CLK5

TOP VIEW

(FPT-20P-M06)

3

MB88181

4

I/O CIRCUIT TYPE

Pin Circuit type Remarks

XPD

• With pull-up resistanceThe pull-up resistance is discon-nected when the XPD line is “L”.

• CMOS hysteresis input

SL0, SL1

CMOS hysteresis input

CLK1 to CLK3CLK5 to CLK9

• CMOS output• At PD active high, “L” output or

Hi-Z output (selectable).

XIN, XOUT

• Oscillator circuit• Built-in feedback resistors 500 kΩ

50 kΩ

PD signal

XIN

XOUT500 kΩ

MB88181

HANDLING DEVICES (1) Preventing Latch-up

A latch-up can occur if, on this device, (a) a voltage higher than power supply voltage or a voltage lower thanGND is applied to an input or output pin or (b) a voltage higher than the rating is applied between power supplyand GND pins. The latch-up may cause components to burn out because the power supply current increasessignificantly. Make sure that the maximum ratings are not exceeded while the device is being used.

(2) Handling unused pins

Leaving unused input pins unconnected may cause a malfunction. Handle unused pins by connecting to a pull-up or pull-down resistor.

(3) Power supply pins

Ensure that the impedance of the connection from the power supply source to the power supply pins on thedevice is as low as possible.

It is recommended that a ceramic capacitor of approx. 0.01 µF and an electrolytic capacitor of approx. 10 µFare connected in parallel between the power supply pins and ground pins as near to the device as possible toact as bypass capacitors.

(4) Crystal oscillator circuit

Noise near the XIN and XOUT pins may cause the device to malfunction. Design the printed circuit so that thewiring between the crystal oscillator and the XIN and XOUT pins does not cross over any other wiring as muchas possible. It is strongly recommended that the circuit board artwork is designed such that the XIN and XOUTpins are surrounded by ground plane for more stable operation.

5

MB88181

6

BLOCK DIAGRAM

V SS

CLK1

CLK2

CLK3

CLK5

CLK6

CLK7

CLK8

CLK9

XOUT

XIN Rf = 500 kΩ

SL0

SL1

VDD

XPD

Clock input

Power down

SSCG (with SS function)

Oscillation frequency setting/Modulation setting

PLL1 (without SS function)


Oscillation frequency setting




Selector divider

Selector divider

Selector divider

Selector divider

Selector divider

Selector divider

Divider

Divider

MB88181

OSCILLATION FREQUENCYThe frequencies of the PLL1, PLL2, PLL3, and SSCG can be determined by the following formula.

Note : From among the range of frequencies that can be selected by the above formula, the range of frequencies that can actually be generated is from 128 MHz to 400 MHz.

M and N can be configured separately for each of the PLL1, PLL2, PLL3, and SSCG. Furthermore, these canbe configured separately for each of the SL0, SL1 pin settings.

MODULATION INDEX AND MODULATION PERIODThe SSCG is able to output the clock which is applied spectrum modulation. The modulation index is selectablefrom OFF, ± 0.5%, ± 1.0%, ± 1.5%, and ± 2.0%, and can be changed independently for each of the SL0 andSL1 pin settings.

The period of modulation can be determined from the following equation.

Note : The value of L is fixed by mask option.It can not be changed according to the SL0 or SL1 pin setting.

Oscillation frequency = M

× (reference clock (input clock) frequency) N

[M is an integer between 8 and 512, N is an integer between 7 and 32]

Reference clock frequency300 × L (L = 2, 3)

1

M

1

N

1

L*

Chargepump IDAC ICO

Phase Comparator

V/I conversion

Modulation logic

Clock outputInput clock

* : L is the modulation period setting

Loop filter

• MB88181 PLL unit block diagram

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MB88181

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OUTPUT FREQUENCYThe output pins can output the reference clock, or the clocks SSCG, PLL1, PLL2, or PLL3 frequency divided by2 to 16 (they can not output by dividing the reference clock). Pins which do not need the clock output can beconfigured as fixed “L” outputs or as Hi-Z. The frequency division ratio can be configured by mask option andby setting SL0 and SL1 pins.

The clock sources that can be selected for each of the clock outputs are as shown in the following table.

: Enable, : Disable

Note : Set by mask option.

POWER DOWNXPD = “H” : Normal operating mode

XPD = “L” : Power-down mode. Clock outputs (CLK pins) are set to “L” or Hi-Z.

Note : If the XPD pin is set to “L”, all of the PLL oscillator circuits are stopped and are placed in the power-down state, and the device enters a low-power consumption mode. In the power-down state, the clock output pins CLK1 to CLK3 and CLK5 to CLK9 output “L” or are placed in the Hi-Z state.The output pin state during power-down is fixed by mask option.The SL0, SL1 pin settings do not enable to switch the fixed states between “L” and “Hi-Z”.

PLL1 PLL2 PLL3 SSCG Reference clock Output stop“L” or Hi-Z

CLK1

CLK2

CLK3

CLK5

CLK6

CLK7

CLK8

CLK9

MB88181

ABSOLUTE MAXIMUM RATINGS

*1 : The parameter is based on VSS = 0.0 V.

*2 : The current per pin.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter SymbolRating

UnitMin Max

Power supply voltage*1 VDD − 0.5 + 4.0 V

Input voltage*1 VI VSS − 0.5 VDD + 0.5 V

Output voltage*1 VO VSS − 0.5 VDD + 0.5 V

Storage temperature TST − 55 + 125 °C

Operation junction temperature

TJ − 40 + 125 °C

Output current IO*2 − 14 + 14 mA

Overshoot VIOVER VDD + 1.0 (tOVER ≤ 50 ns) V

Undershoot VIUNDER VSS − 1.0 (tUNDER ≤ 50 ns) V

VDD

VSSInput pin

Overshoot/Undershoot

tUNDER ≤ 50 ns

VIOVER ≤ VDD + 1.0 [V]

tOVER ≤ 50 nsVIUNDER ≤ VSS − 1.0 [V]

9

MB88181

10

RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of thesemiconductor device. All of the device’s electrical characteristics are warranted when the device isoperated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operationoutside these ranges may adversely affect reliability and could result in device failure.No warranty is made with respect to uses, operating conditions, or combinations not represented onthe data sheet. Users considering application outside the listed conditions are advised to contact theirrepresentatives beforehand.

Parameter Symbol Pin ConditionsValue

UnitMin Typ Max

Power supply voltage VDD VDD 3.0 3.3 3.6 V

“H” level input voltage VIH

XIN, SL0, SL1, XPD

VDD × 0.8 VDD + 0.3 V

“L” level input voltage VIL

XIN, SL0, SL1, XPD

VSS VDD × 0.2 V

Input clock duty cycle tDCI XIN 16 MHz to 32 MHz 40 50 60 %

Operating temperature Ta − 40 + 85 °C

XIN

VDD/2 + 1 [V] VDD × 0.5 [V]

VDD/2 − 1 [V]

ta

tb

Input clock duty cycle (tDCI = tb/ta)

MB88181

ELECTRICAL CHARACTERISTICS• DC Characteristics

(Ta = −40 °C to + 85 °C, VDD = 3.0 V to 3.6 V, VSS = 0.0 V)

* : The XPD pin input pull-up resistance is disconnected when the XPD pin is set to “L”.

Parameter Sym-bol Pin Conditions

ValueUnit

Min Typ Max

Power supply current

ICC VDD

Original oscillation : 20 MHz

SSCG : 200 MHz oscillation

PLL1 : 240 MHz oscillation



CLK1 : 20 MHz outputCLK2 : REF outputCLK3 : “L” outputCLK5 : 32 MHz outputCLK6 : 36 MHz outputCLK7 : 50 MHz outputCLK8 : 40 MHz outputCLK9 : 80 MHz output(No load capacitance at output)

55 60 mA

Power down current

IPD VDD XPD = 0 5 80 µA

Output voltage

VOHCLK1 to CLK3CLK5 to CLK9

“H” level output, IOH = − 8 mA

0.8 × VDD VDD V

VOLCLK1 to CLK3CLK5 to CLK9

“L” level output, IOL = 8 mA

VSS 0.2 × VDD V

Output impedance ZOCCLK1 to CLK3CLK5 to CLK9

8 MHz to 80 MHz 30 Ω

80 MHz to 166 MHz 20

Load capacitance CLCLK1 to CLK3CLK5 to CLK9

8 MHz to 166 MHz 15 pF

Input pull-up resistance

RXPD XPD VIH = 0.8 × VDD* 25 200 kΩ

11

MB88181

12

• AC Characteristics

(Ta = −40 °C to + 85 °C, VDD = 3.0 V to 3.6 V, VSS = 0.0 V)

* : The rated value when outputting on only one pin.The jitter value varies depending on the combination of output frequency and output pin.

Note : The modulation clock stabilization wait time is required after the power is turned on, or when the settings are changed for power down, multiplication index and modulation. Ensure that the modulation clock stabili-zation wait time has as long as the maximum lock-up time.

Parameter Symbol Pin ConditionsValue

UnitMin Typ Max

Input frequency fin XIN Crystal oscillator input 16 32 MHz

Crystal oscillator frequency

fxXIN,

XOUTFundamental frequency 16 32 MHz

Output frequency fOUTCLK1 to CLK3CLK5 to CLK9

8 166 MHz

Output clock rise time trCLK1 to CLK3CLK5 to CLK9

0.2 × VDD to 0.8 × VDD

Load capacitance 15 pF0.4 4.0 ns

Output clock fall time tfCLK1 to CLK3CLK5 to CLK9

0.2 × VDD to 0.8 × VDD

Load capacitance 15 pF0.4 4.0 ns

Output clock duty cycle tDCCCLK1 to CLK3CLK5 to CLK9

0.5 × VDD

Divided clock output45 55

%0.5 × VDD

Reference clock output40 60

Modulation period fMODCLK1 to CLK3CLK5 to CLK9

Input clock : 20 MHz 33.3 kHz

Lock-up time tLKCLK1 to CLK3CLK5 to CLK9

4 10 ms

Cycle-cycle jitter* tJCCLK1 to CLK3CLK5 to CLK9

Ta = + 25 °C, VDD = 3.3 V, No load capacitance,

Effective value 100 ps-rms

Power down enable “L” width

tPDLW XPD 1 µs

Power-on time tVDR VDD 0.0 V to 3.0 V 100 µs

“L” output start time after power down entry

tPELCLK1 to CLK3CLK5 to CLK9

When PD rise/fall time is 5 ns

10 ns

“L” output release time after power down exit

tPILCLK1 to CLK3CLK5 to CLK9


0 ns

Output start time after power down exit

tPIOCLK1 to CLK3CLK5 to CLK9


No load capacitance 15 pF 10 ns

MB88181

OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta)

INPUT FREQUENCY (fin = 1/tin)

OUTPUT SLEW RATE

CYCLE-CYCLE JITTER (tJC = |tn−tn+1| )

CLK1 to CLK3,CLK5 to CLK9

VDD × 0.8 [V]

VDD × 0.5 [V]

VDD × 0.2 [V]

ta

tb

tin

XINVDD × 0.8 [V]

VDD × 0.2 [V]

tftr

VDD × 0.8 [V]

VDD × 0.2 [V]


tn+1tn


Note : Cycle-cycle jitter is defined as the difference in the period between a given cycle and the following cycle (or the previous cycle).

13

MB88181

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POWER DOWN “L” WIDTH

POWER-ON TIME

“L” OUTPUT START TIME AFTER POWER DOWN ENTRY

tPDLW

XPDVDD × 0.8 [V]

VDD × 0.2 [V]

tVDR

VDD3.0 V

0.0 V

XPD VDD × 0.2 [V]

tPEL

CLK1 to CLK3,CLK5 to CLK9 “L” output or Hi-Z

MB88181

“L” OUTPUT RELEASE TIME AND OUTPUT START TIME AFTER POWER DOWN EXIT

MODULATION WAVEFORM

XPD VDD × 0.8 [V]

VDD × 0.8 [V]

tPIL

tPIO

CLK1 to CLK3,CLK5 to CLK9 “L” output or Hi-Z

− 1.5 %

+ 1.5 %

• ± 1.5%, example of center spread

[Output frequency]

Frequency at modulation OFF

[Time]

fMOD = 33.3 kHz (input clock : 20 MHz)

15

MB88181

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LOCK-UP TIMEThe clock outputs from the CLK1 to CLK3 and CLK5 to CLK9 pins conform to the ratings after the lock-up time(tLK) has elapsed after the states of all of the power supply, input clock, and pin settings have stabilized. Theoutput frequency, output clock duty cycle, modulation period, and cycle-cycle jitter are not guaranteed duringthe lock-up period. It is therefore recommended that processing, such as releasing device reset, is performeduntil after the lock-up time has elapsed.

Check the characteristics of the oscillator or clock being used for the stabilization wait time of the input clock. Ifthe built-in oscillator circuit is used, the stabilization wait time depends on the characteristics of the oscillator.

<At power-on>

The input clock oscillation stabilization wait time is required when the power is turned on.

When the XPD pin is fixed at “H”, the desired clock can be obtained after a maximum of the stabilization waittime of the clock being input to XIN plus the lock-up time (tLK) has elapsed.

3.0 VVDD

XIN

XPD

VIH


Oscillation stabilization wait time

tLK

(Lock-up time)

Setting pinSL0, SL1

MB88181

<On release from power-down when using clock input>

When the power down is controlled by the XPD pin, the desired clock is obtained after the pin is set to “H” leveluntil the maximum lock-up time tLK has elapsed.

<On release from power-down when using an oscillator circuit>

When the XPD pin is set to an “L” level, the device enters power-down mode, and oscillator on the XIN andXOUT pins is stopped in order to stop the internal oscillator circuit of the device.

When the XPD pin is set to the “H” level and the device changes to normal operating mode, the oscillator circuitbegins operating and the XIN and XOUT oscillator is started. However, a prescribed time is required until theinput clock becomes stable (the stabilization wait time). Furthermore, because the lock-up time is required beforethe output clock stabilizes, the maximum amount of time from when the power-down is released until the outputclock stabilizes is [oscillator stabilization time] + [lock-up time].

3.0 VVDD

XIN

XPD

VIH

VIL

VIH



tLK

(Lock-up time)

Setting pin SL0, SL1

XIN

XPD

VIH



tLK

(Lock-up time)

Setting pinSL0, SL1

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MB88181

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<When setting pins are changed>

If the clock is controlled by changing the setting pins (SL0, SL1) during operation, the desired clock signal canbe obtained when a maximum of the lock-up time (tLK) has elapsed after the setting pins are set.

XIN

XPD

VIH

VIH

VILVIH

VIL


tLK

(Lock-up time)

Setting pinSL0, SL1

tLK

(Lock-up time)

MB88181

RECOMMENDED CIRCUIT

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

C1 C2

C3

C6

XIN

SL0

SL1

CLK9

CLK1

CLK2

CLK3

VSS

XOUT

CLK8

CLK7

CLK6

CLK5

XPD

VDD

VSS

VDD

VSS

VSS

VDD

R9

R1

R2

R8

R7

R6

R5

R3

C5 C4MB88181

C1, C2 : Oscillation stabilization capacitors (refer to the following description) C3 : Tantalum capacitor or electrolytic of 10 µF or higherC4 to C6 : Laminated ceramic capacitor about 0.01 µF (connect the capacitor

close to the SSCG.) R1 to R3, R5 to R9 : Resistors for impedance matching with the board pattern

19

MB88181

20

CRYSTAL OSCILLATOR CIRCUITThe figure below shows an example of the connection of a generic crystal oscillator. The oscillator circuit has abuilt-in feedback resistance (500 kΩ). The values of the capacitors (C1 and C2) need to be set to the optimalvalues of the crystal oscillator.

C1

Rf (500 kΩ)

C2

XIN Pin

MB88181 LSI Internal

MB88181 LSI External

XOUT pin

MB88181

EXAMPLE OUTPUT SETTINGSThe following table shows examples of the M and N frequency dividers, the output frequency divider, and themodulation index settings for each of the SL0 and SL1 pin settings.

SL0 0 1 0 1Remarks

SL1 0 0 1 1

SSCG200 MHz

± 1.0% modulation200 MHz



± 2.0% modulation

PLL1 300 MHz 300 MHz 350 MHz 350 MHz No modulation



CLK1

Divided by 10 of SSCG

20 MHz output ± 1.0% modulation







CLK divided by SSCG or PLL2

CLK2 REF output REF output REF output REF outputCLK divided by PLL1 or REFCLK

CLK3 REF output REF outputDivided by 4 of

PLL365 MHz output

Divided by 5 of PLL3

52 MHz output

CLK divided by PLL3 or REFCLK

CLK5Divided by 4 of

PLL239.5 MHz output


39.5 MHz output


39.5 MHz output


39.5 MHz outputCLK divided by PLL2

CLK6Divided by 12 of

PLL327.5 MHz output


27.5 MHz output


27.5 MHz output


27.5 MHz outputCLK divided by PLL3

CLK7 No output No output





CLK divided by SSCG or PLL2

CLK8





No output No outputCLK divided by SSCG or PLL2

CLK9Divided by 15 of

PLL322 MHz output


66 MHz output


70 MHz output


25 MHz output

CLK divided by PLL1 or PLL3

21

MB88181

22

ORDERING INFORMATION

Note : The different figures XXX are assigned by the mask options.

Part number Package

MB88181PFT-G-XXX-BNDE120-pin plastic TSSOP

(FPT-20P-M06)

MB88181

PACKAGE DIMENSION

Please confirm the latest Package dimension by following URL.http://edevice.fujitsu.com/package/en-search/

20-pin plastic TSSOP Lead pitch 0.65 mm

Package width ×package length

4.40 × 6.50 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.10 mm MAX

Weight 0.08g

Code(Reference)

P-TSSOP20-4.4×6.5-0.65

20-pin plastic TSSOP(FPT-20P-M06)

(FPT-20P-M06)

C 2003 FUJITSU LIMITED F20026S-c-3-3

6.50±0.10(.256±.004)

4.40±0.10 6.40±0.20(.252±.008)(.173±.004)

0.10(.004)

0.65(.026) 0.24±0.08(.009±.003)

1 10

20 11

"A"

0.17±0.05(.007±.002)

M0.13(.005)

Details of "A" part

0~8˚

(.024±.006)0.60±0.15

(0.50(.020))

0.25(.010)

(.041±.002)1.05±0.05

(Mounting height)

0.07+0.03–0.07

+.001–.003.003

(Stand off)

LEAD No.

INDEX

*1

*2

Dimensions in mm (inches).Note: The values in parentheses are reference values.

Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).Note 2) *2 : These dimensions do not include resin protrusion.Note 3) Pins width and pins thickness include plating thickness.Note 4) Pins width do not include tie bar cutting remainder.

23

FUJITSU MICROELECTRONICS LIMITEDShinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South AmericaFUJITSU MICROELECTRONICS AMERICA, INC.1250 E. Arques Avenue, M/S 333Sunnyvale, CA 94085-5401, U.S.A.Tel: +1-408-737-5600 Fax: +1-408-737-5999http://www.fma.fujitsu.com/

EuropeFUJITSU MICROELECTRONICS EUROPE GmbHPittlerstrasse 47, 63225 Langen,GermanyTel: +49-6103-690-0 Fax: +49-6103-690-122http://emea.fujitsu.com/microelectronics/

KoreaFUJITSU MICROELECTRONICS KOREA LTD.206 KOSMO TOWER, 1002 Daechi-Dong,Kangnam-Gu,Seoul 135-280KoreaTel: +82-2-3484-7100 Fax: +82-2-3484-7111http://www.fmk.fujitsu.com/

Asia PacificFUJITSU MICROELECTRONICS ASIA PTE LTD.151 Lorong Chuan, #05-08 New Tech Park,Singapore 556741Tel: +65-6281-0770 Fax: +65-6281-0220http://www.fujitsu.com/sg/services/micro/semiconductor/

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.Rm.3102, Bund Center, No.222 Yan An Road(E),Shanghai 200002, ChinaTel: +86-21-6335-1560 Fax: +86-21-6335-1605http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.10/F., World Commerce Centre, 11 Canton RoadTsimshatsui, KowloonHong KongTel: +852-2377-0226 Fax: +852-2376-3269http://cn.fujitsu.com/fmc/tw

All Rights Reserved.

The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purposeof reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICSdoes not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-ing the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the useor exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICSor any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right orother right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectualproperty rights or other rights of third parties which would result from the use of information contained herein.The products described in this document are designed, developed and manufactured as contemplated for general use, including withoutlimitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufacturedas contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effectto the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control inweapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arisingin connection with above-mentioned uses of the products.Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures byincorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-currentlevels and other abnormal operating conditions.Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations ofthe Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Strategic Business Development Dept.

data sheet - fujitsu...bol pin conditions value unit min typ max power supply current icc vdd...

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