data mining for significance in yield-defect correlation analysis

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI10.1109/TSM.2014.2337251, IEEE Transactions on Semiconductor Manufacturing

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Abstract— A yield analysis method using basic yield and in-

line defect information in a statistical model to determine root-causes of yield loss in semiconductor manufacturing is presented. The goal of this analysis method is to provide the fab process line management yield loss accounting for defects identified at inspected process layers. Quantifying these losses, in terms of yield loss percent and statistical confidence allows the fab to set priorities for defect reduction work to achieve maximum yield enhancement. Separation of killer defects from nuisance defects and inspection or pattern related noise is a constant challenge. This tool provides statistical techniques for identifying the most effective inspection tool or recipe for a given inspection layer. Enhanced statistical resolution can be achieved through data mining by defect size, classification, or electrical failure bin information. These die level analysis techniques may be combined with memory bit level correlation analysis, and physical failure analysis to provide a comprehensive yield accounting assessment.

Index Terms— Data Mining, Integrated Circuit Yield, Kill Ratio, Probability, Semiconductor Device Manufacture, Statistics, Yield, Yield Learning

I. INTRODUCTION APID accurate identification of process defect related yield loss sources is critical to driving the semiconductor

yield learning curve. Previous work has provided some means of direct correlation of yield to process defects [1] but did not have an effective means for statistically separating true killer defects from inspection related noise or nuisance defects.

This paper presents a method to mine the die electrical failure data and in-process defect data to statistically determine and quantify defect root-causes of yield loss in semiconductor manufacturing. Basic statistical probability functions are applied to the die and defect populations to effectively separate true killer defects from nuisance defects and inspection noise. This is a critical tool in the constant

Manuscript received January 17, 2014; revised March __, 2014; accepted. Uwe Hessinger is Device Engineer, Lattice Semiconductor Corp.,

Hillsboro, OR 97124 USA, (e-mail: [email protected]). Wendy Chan is Device Engineer, Lattice Semiconductor Corp., Hillsboro,

OR 97124 USA, (e-mail: [email protected]). Brett Schafman is Director of Foundry Operations, Lattice Semiconductor

Corp., Hillsboro, OR 97124 USA, (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available

online at http://ieeeexplore.ieee.org. Digital Object Identifier

challenge of balancing defect inspection sensitivity and the generation of inspection noise. We call this probability function the “Confidence Factor (CF)” and it is the critical magnifying glass allowing us to discover true killer defects in the in-process inspection data.

The probability statistics are enhanced by larger die populations. For this reason small die size products provide excellent statistical Confidence Factors on killer defects for a single wafer sample. Identification of single wafer excursions whether occurring in Gross Fail Area (GFA) patterns or random elevated defect patterns can be identified without complex and computationally intensive wafer fail pattern analysis [2]. More complex larger die products and SOC’s can combine single wafer overlay populations into lot level or larger statistical population to extract lower level defect contributors.

Separating populations by specific electrical failure bins and defect classifications can further enhance the statistical confidence and give deeper insight into killer defects by removing non-killer subpopulations or non-correlated failure types. Analysis by geographic wafer zones can offer further insights into defect sources or benign defects with coincidental overlay results. These techniques are also discussed.

Die level analysis results may be combined with additional yield correlation data such as memory bitmap-to-defect correlations and physical failure analysis (PFA) for a complete and comprehensive yield loss accounting system, Fig 1.

This paper offers additional detail and expanded applications over our original work presented in [7].

Data Mining for Significance in Yield-Defect Correlation Analysis

Uwe Hessinger, Wendy Chan, Brett Schafman, Senior Member IEEE

R

Fig. 1. Yield accounting system



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II. MODEL DEVELOPMENT

A. Statistical Method The objective of this analysis is to determine if there is a

statistical significance in the distribution of detected defects on sort test failing dies from what would be expected from alignment of a random defect distribution on the entire population of dies on the wafer. So for each inspected layer we consider two populations:

1. All dies on the wafer, both sort pass and fail

2. Dies with defects detected in process

The statistical test looks to see if there is a significant

difference between the distributions of defects on electrically good dies versus electrically bad dies. In order to facilitate the visualization of the die populations a graphical representation we call Die Level Box Plots are used. Fig. 2a and 2b illustrate their construction. In the upper three boxes in each figure there are three 10x10 die arrays. From the left the first array shows a random distribution of sort fail dies, the next shows die with defects and the last the overlay of these two distributions. To better visualize the relationship between these populations we will reorder the boxes. All of the sort failure dies are moved to the left side of the 10x10 array. Dies with defects are all moved to the bottom of the array, however, dies which both fail sort and have a defect are placed within the failed die area at the left bottom. Only the dies with defects which pass sort test remain on the right bottom portion of the array. The proportions of each population are now clearly visible. Fig. 2a illustrates the case of failing dies and defects where there is no apparent correlation between the defects and failing dies. The defects might be benign. Whereas Fig. 2b shows a case where there is a much higher incidence of defects found on electrically failing dies. In this case some portion of the defects detected would appear to be killer defects.

Now let’s consider the die subpopulations of an inspected and sort tested wafer, Fig. 3, where:

N: Total gross dies per wafer

D: Dies on the wafer containing one or more defects detected in-process.

F: Dies which fail wafer sort electrical test

H: Dies which have detected in-process defect (D) AND fail wafer sort (F), defined as “Hits”

In order to complete the analysis of yield we must define three sub-categories of “Hits” as follows:

Hr: Random Hits, the expected number of failing dies with defects given random chance and no correlation with failure.

Hb: Benign Hits, the number of failing dies with defects which are most likely NOT killers.

Hk: Killer Hits, the number of failing dies with defects which most likely cause electrical failure.

Comparing the proportion of die with defects on failing die, versus the proportion of die with defects on passing die, gives both a yield loss percentage explained, and an indication of whether the defects are a root-cause of die failure. Defects which do not cause die failure, will exhibit a similar proportion for both passing and failing die, and a very small or zero yield loss number, Fig. 3a. On the other hand, defects with a high kill ratio would be found at a higher proportion on failing die compared to passing die and results in a higher yield loss number, Fig. 3b.

Die Level Box Plots as shown in Fig. 3, and throughout this paper, give a quick visual picture of alignments between die with defects for both failed and passed die. Nevertheless, proportions alone do not tell the full story. There can be a significant probability that a higher proportion alignment between failing die and die with defects is simply due to a random alignment, rather than due to cause and effect between defects and failing die. By considering the probabilities of given alignments, a confidence value for cause and effect can be defined.

To calculate the probability (P) of a random alignment between failing die and die with defects, the hypergeometric distribution (1) may be applied. This function gives the probability for n random draws delivering k successes of a finite population N divided into two groups of K and N-K.

Fig. 2. Die Level Box Plot construction. (a) Defects might be benign. (b) Killer defect correlation.



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−−

==

nN

knKN

kK

NKnkhkP ),,,()( (1)

Translated to the case of dies with and without defects using

the definitions above, the hypergeometric distribution (2) provides the probability for D, i.e. the number of die with defects, considered as the random draws, delivering H hits (successes) of these defects being aligned with F failed die, rather than with N-F passing die, with N being the total number of die on a wafer.

)!(!!

)!()!()!(

)!(!!

),,,()(

DNDN

HDFNHDFN

HFHF

DN

HDFN

HF

NFDHhHP

−

+−−−−

−=

−−

==

(2)

For illustration of the importance of probability, consider a

simple example of flipping a coin, resulting in a proportion of 40% tails and 60% heads. Such disproportion does not say much about the coin if the toss was done only ten times, i.e. with a result of four tails and six heads. Nevertheless if the coin toss was done 1000 times, the disproportion between 400 tails and 600 heads is very unlikely by random chance, and gives a much higher confidence of a cause and effect finding.

In the case of semiconductor wafers, the confidence or probability depends strongly on the number of die on a wafer, sort failing die, and die with defects. In general higher numbers give higher confidence for alignments to be due to cause and effect. This can provide a clear picture of killer defects. Fig. 4 shows an example of the probability function with significant difference between probabilities for a random alignment of Hr random hits and high confidence alignment of H hits larger than Hr where:

N

FDNND

NFH r == (3)

In this way we define the Confidence Factor (CF) as the

ratio of the probability of the most likely random hits Hr versus the probability of the actual hits H observed on the wafer occurring by random chance, using the hypergeometric function. CF forms the basis for determination of the Cause-Effect relationship between yield and in-process defect data.

=

)()(log

HPHPCF r (4)

We typically consider CF>1 as significant indicators for

non-random events. CF of 1 represent a ten times smaller probability for the actual hits event occurring by random chance, compared to the probability of the most likely random hits. For the example of 10, 100 and 1000 coin tosses, and a 60% heads outcome for each, rather than the most likely random outcome of 50% heads, the respective CF are 0.08, 0.9, and 8.7. Only the 1000 coin toss gives a very high confidence indicating a very likely non-random event. The 100 coin toss with a CF near 1 should be considered, but the 10 coin toss with 6 heads does not give any significant indication of a non-random event.

B. Calculation of Kill Ratios & Yield Loss Explained In order to account for the yield loss from any given

inspection layer the number of dies actually killed by the defects must be determined. This is described by Hk in Fig. 3b above and by the expression (5) below, derived from basic geometry of areas in Fig. 3b. We make the assumption here that benign defects on failed die occur at the same rate as on good die. This is a valid assumption if die failure is due to several causes. These benign hits Hb are not counted towards defects causing die failure, and prevents an over counting of die killed by defects. The “Die Level Kill Ratio”, k, is the fraction of failing dies with defects is described by (6).

FNFDHNHHH bk −

−=−= (5)

Fig. 4. Probability of alignment of H dies by random chance

Fig. 3. Subcategories of Hits. a) Random alignment between failed die and die with defects (left); b) Correlated alignment of failed die and die with defects (right).



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)( FND

FDHND

Hk k

−−

== (6)

In practice we found some low CF (<1.0) results provide

important yield loss information, and applied a scale factor (7) to the yield loss estimation.

CF

r

rCF HP

HPHPf −−=−

= 101)(

)()( (7)

This factor ranges from 0, for likely random alignment with

small CF, to 1 for likely non-random alignments with CF>1. This assures that only killer hit numbers Hk with high CF get fully counted, and that alignments potentially due to random chance will get strongly diminished in their yield loss contribution.

The resulting yield loss for any given inspection layer may be expressed in terms of an absolute yield loss (8), i.e. the fraction of dies killed as a portion of total gross dies per wafer, or relative to the total failing dies F as a fraction of the total yield loss (9) or the “ relative yield loss explained”.

NHfabsoluteY kCF /_ = (8) FHfrelativeY kCF /_ = (9)

C. Application to Product Yield Results For our smallest products with about 10,000 die per wafer,

we obtained alignments of very high confidence, explaining over 25% yield loss for a single defect layer inspection. Review of inspection images of these highly likely killer defects allows for very fast root-cause elimination.

For other products of 500-1500 die per wafer, and with inspection rates of about 10 layers per lot we typically achieve 25% of yield loss explained through this die level sort to defect correlation. A test lot with 35 layers inspected gave 54% of yield loss explained. These findings allow the fab process line to set high priority defect reduction on killer defects rather than benign defects. Determining root-causes through this method also frees up failure analysis resources for other defects not inspected or not captured. Furthermore, distinguishing between benign and killer defects can help in inspection sensitivity settings with the goal to detect the latter rather than the former.

This method has been streamlined for high volume production, by running automatic data alignment programs for each lot and wafer and for each inspection. Redundant defects detected at previous layers are eliminated and not included in the analysis to avoid double counting. Total number of die N, failed die F, die with defects D, and the alignment, hits H, between these two groups are the only numbers needed for the calculation of yield loss explained and confidence values for each alignment. Combined wafer maps of sort test results and defects provide a visual check for a correlation as well as valuable information regarding the nature of the defects, such as scratches, randomly distributed defects across wafer, and

wafer edge defects, which can help the fab process line to find causes of these defects.

To illustrate a real life case of yield enhancement, we found that for some of our smallest products (~10,000 die per wafer), up to 40% of yield loss could be explained by a single inspection layer with high confidence. A review of inspection images for the matching defects showed that most defects are of the same type. This information allowed the fab to quickly identify the root cause and implement a process fix. In subsequent lots, the yield loss explained decreased substantially to the 5% level, Fig. 5. We could be assured the previous defect type had been eliminated.

III. EXCURSION WAFER ROOT CAUSE DETECTION In semiconductor wafer processing and yield enhancement

there are many different yield loss modes of interest: baseline defect related yield loss affecting all wafers, excursion lots or wafers suffering unique yield loss mechanisms different from the baseline, parametric yield loss related to transistor or other device parametric shifts, etc. It is possible to quickly identify excursion wafers within a lot and layer by looking at the Confidence Factor excursions. A large CF would be indicative of an outlier and its cause. This identifies both a wafer of interest but also the root cause layer quickly so additional resource intensive effort like physical failure analysis (PFA) can be focused on other unknown causes. Fig. 6a shows the results for four lots of a product with 1400 gross die per wafer. Excursion wafers are easily identified. A wafer with a large CF may show a clear match between defects and die sort failure in a non-random pattern, Fig. 6b-c. This data allows quick identification of root cause layer for a low yielding wafer.

IV. IMPACT OF DIE SIZE ON CONFIDENCE FACTOR This model has been applied to product die sizes from

0.03cm2 to 1.6cm2. The Confidence Factor depends strongly on die size, and the analysis is highly effective for smaller die. The analogy described before is the reduction in CF for fewer total coin tosses. For large die sizes we observed substantially

Fig. 5. Yield loss explained before and after process fix



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lower CF, in which case it is beneficial to supplement the results with bitmap correlation to regain some sensitivity as noted by other authors related to process yield modeling [4]. To demonstrate this behavior, clusters of a smaller die product (2x2, 3x3, 4x4, 5x5) were created from a single wafer with 4483 gross die overlaid with a fixed defect map to show the change in Confidence Factor as the die size increases. The CF goes from 144 for the original die map to 10 for a 4x4 cluster, Fig. 7a-c. In the case where a product family of various die sizes are in production in the same line, a product with the smallest die size would be the optimal choice for yield improvement vehicle when only die pass/fail data (i.e. no memory bit mapping) is available and individual excursion wafer detection is desired. On the other hand, at the sacrifice of individual wafer results, large die wafer populations may be combined to lot level populations or larger to enhance the statistical confidence on individual yield loss contributors, Fig. 8. Once again as with the coin toss example above in Section II, increasing the die sample size by combining populations of multiple wafers can dramatically improve the statistics of the die overlay results.

We observed a case of a product with die size 0.86 cm2 and 712 gross dies per wafer where a low defect level critical layer inspection produced CF results on average <0.3 for all 25 wafers. Only a single wafer had a CF greater than 1.0, our defined threshold of significance. When the analysis is instead performed on the full lot combining all 25 wafers in a single population the resulting lot-level CF becomes 3.1 indicating a highly likely yield loss contribution. This data was lost in the

Fig. 6. Excursion wafer detection. (a) Variation of CF across wafers. (b) Wafer map with CF: 37.7. (c) Wafer map with CF: 12.2.

Fig. 7. Impact of dies size on CF. (a) CF vs. die size for example wafer. (b) Wafer map of 0.14 cm2 die size. (c) Wafer map of 2.3 cm2 die size

Fig. 8. Combining wafer populations (a) Die Level Box Plots of various wafers combined into single population. (b) CF as a function number of wafers for fixed Hk (712 d/w).



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defect and yield noise of individual wafer results. As a test case another product with 50% larger die size and a single wafer CF of 0.61 was duplicated 25 times and the CF was recalculated for the lot level CF. The resulting CF became 14.9 demonstrating the power of increasing to a lot level die sample for these large die products. Fig. 8b shows the power of combining wafer populations to increase sample size and confidence in the defect overlay results with fixed killer and benign defect ratios. This could be an especially powerful tool in a mature production line where comparing different equipment or process treatments returns low level but important yield improvements. A set of pilot lots comparing the different treatments or tools combined into one population will yield enhanced sensitivity needed to resolve subtle differences which cannot be detected with confidence on raw yield results alone. Concomitant single wafer analysis remains an important analysis element to assure that single wafer effects from excursion events do not contaminate the larger population results for low level defect contributors.

V. INSPECTION TOOL CHARACTERIZATION Silicon wafer foundries typically have several different

defect inspection tools and many options for inspection modes or approaches. Some of the obvious trade-offs in tool selection are inspection time versus sensitivity. Some inspection tools may be very slow but capture a larger number of killer defects. This tool may only be applied to a small sample of wafers. Other tools may be quick enough to allow full lot inspection but lack sensitivity to smaller defects. The Confidence Factor offers an additional figure of merit in addition to cost based considerations [3] in evaluating tools, recipes, and defect classifications in optimizing a defect monitor plan.

A. Inspection Tool Effectiveness by Confidence Factor Fig 9. shows the case of two different inspection tools with

substantially different yield loss explained and kill ratios. In this example, a small die product (~3700 gross die) is inspected at a given layer using two different inspection tools. Yield loss explained is clearly higher for Tool A: 16.6% vs. 6.2% for Tool B, Fig. 9a; however, kill ratio is much lower for Tool A, Fig. 9b. Only 5.5% of the die with defects caused a dice to fail, meaning the majority of the defects are non-killer and nuisance defects, yet both tools show a similar Confidence

Factor, Fig 9c. Both are effective tools. A trade-off decision has to be made between the tools. Tool A has a higher capture of killer defects yet a random defect review would include 95% benign defects, whereas Tool B defect review would include 33% killers. In spite of its lower yield loss explained Tool B may be a better choice provided there is not some special defect mode missed by this tool. A detailed review of defect capture results by size and type could prove the final determining factor. In the end for yield prediction Tool B would require a larger scale factor to yield loss explained.

B. Filtering by Defect Classification In the case of a highly sensitive inspection tool and recipe,

Fig. 9. Tool Effectiveness Tool A vs B, (a) Relative Yield loss (b) Kill Ratio. (c) Confidence Factor

Fig. 10. Filtering by defect classification. (a) Total defects vs. classified defects. (b) Relative Yield Loss Explained. (c) Confidence Factor, d. Kill Ratio. (e) All defects Wafer Map & Die Level Box Plot CF. 1.2. (f) Classified Wafer Map & Die Level Box Plot CF. 8.3.



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similar to Tool A above, the inspection effectiveness can be improved upon greatly with defect type filtering and classification. The example in Fig. 10 is for a larger die product (~700 gross die). This layer has typically low confidence when all defects are included in the analysis. In order to reduce the effect of nuisance defects, key defect types are classified, Fig. 10a. However, the percent yield loss explained using only classified defects is comparable to when all defects are used for analysis, Fig. 10b. In addition, both Confidence Factor and kill ratio improve dramatically, Fig. 10c-d. Wafer maps including all defects and classified defects are given in Fig. 10e and Fig. 10f respectively, with the latter wafer map of significantly increased CF providing more valuable insight into the nature of the killer defects.

In general, for a quick visual evaluation of sort versus defect alignment and its statistical significance, the Die Level Box Plot introduced in the model development (Fig. 3) can be used. For the specific case here for non-filtered defect data (Die Level Box Plot insert Fig. 10e), the proportion of die with defects on failed die are higher but comparable to die with defects on passing die. For the case of filtered defect data (Die Level Box Plot insert Fig. 10f), the proportion of die with defects is significantly higher for failed die than for passing die giving the much higher CF in this case.

VI. ENHANCING CONFIDENCE BY SEGREGATION Even though die level correlation has proven to be a simple,

yet powerful tool for automatic extraction of killer defects, we would like to further enhance this tool for two reasons. First to reduce statistical limitations and low confidence correlations, especially for large products with fewer die per wafer, and second to extract more detailed information about defects and their impact on sort test, such as a critical size of a defect for causing electrical failures.

Both of these enhancements can be achieved by segregation of defect and/or sort fail data into sub groups, such as groups di of different defect sizes, as well as fail bins fj for the different tests used at sort. Any information for defects and sort fails can be used to define these sub groups. Correlations can be run for each combination of sub groups di and fj. High confidence correlations can be filtered out and used to extract valuable information about killer defects and their impact on sort.

Consider an example of a process layer with defects of varying sizes. Defects above a critical size, i.e. large defects, could have a high kill ratio, and cause sort fail, whereas small

defects may be mostly benign in terms of sort fail. Splitting the defects into two independent groups dLarge and dSmall, provides two die level correlations, with group dLarge giving a high Confidence Factor compared to a basic die level correlation with all defects combined.

Fig. 11a shows the Die Level Box Plot of the basic die level correlation for a wafer of 450 die (N), with 200 failed die (F), 100 defects (D) and 50 hits (H). The CF is low at 0.3. Splitting the defects into small and large defects, gives smaller and larger CF for these sub groups. Fig. 11b shows the box plot for 70 small and benign defects with only 30 hits and a similar hit rate on passing die, therefore a CF near 0. Fig. 11c on the other hand shows 30 large defects with 20 hits, a significantly higher hit rate for failed die, and therefore an improved correlation with CF of 1.4. Please note that splitting defects by size is arbitrary and can be varied to potentially determine a critical size above which kill ratios and CF increase significantly.

Using the same data, a second example for sub group correlation is illustrated in Fig. 11d. All defects of a layer are correlated versus three sort fail bins, showing a clear impact of considered defects on sort test 3. Forty die in fail bin f3, including 26 die with defects, and 250 passing die, including 50 die with defects, in a total population 290, (250 passing and 40 f3 failed die), provide a significantly increased CF of 2.0, as well as a cause and effect relationship between process step defects and sort test bins.

Taking this one step further, splitting and correlating all combination of subgroups for both defects and sort fails, provides even further resolution between defects and sort. Fig. 11e illustrates again the same data but for the large defects, and three sort fail bins. The hit rate between large defects and fail bin f3 stands out compared to the defect level on passing die. This is also an example of Die Level Box Plots providing quick visual measures of cause and effect. Nevertheless for full probability evaluation absolute numbers matter, and for 40 fail bin f3 die, including 12 die with large defects, versus 250 passing die, including 10 die with large defects, the CF increases to 3.3 for large defects and bin f3.

All three examples of correlation enhancements raised the low basic die level CF from 0.3 above our set limit of 1.0. The enhancements also provided more detailed cause and effect information. These links between process layers and sort test can be very beneficial in semiconductor manufacturing, when occurrence of high fail bin can quickly be related back to a likely process layer, and expedite root-cause elimination.

Fig. 11. Die Level Box Plots. (a) Basic. (b) Small defects. (c) Large defects. (d) By sort bin, (e) By sort bin and defect size



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A drawback to using subgroup correlation is an increase in data complexity and an increase in the number of calculations. Another drawback is the reduction in die numbers due to the splitting of data, which can reduce CF in the probability calculations. Detailed defect data may also be unavailable to fabless companies, and detailed test data may be difficult to extract or manage. This can limit the use of these enhanced methods.

Basic die level correlation should remain the first level analysis tool, while enhanced methods through data segregation can be employed in parallel when detailed data is available, and higher resolution to root-causes is needed.

VII. INTEGRATION OF YIELD ANALYSIS RESULTS The analysis of die overlay with in-line defects is just one

tool in the yield analysis box. On any given lot or wafer more information might be needed to account for the yield loss and identify corrective actions. When defects are the primary issue of concern and the product contains significant memory, such as with FPGA’s, defect correlation to memory fail bitmap may be the logical next step. As mentioned above the die level statistics become weaker for larger die sizes but these same products have substantial block memory arrays and distributed configuration memory which can be mapped.

While the die level yield accounting described above can provide accurate accounting for known defect causes the analysis doesn’t actually identify the killed dies. You don’t know which ones are killed by defects at a given inspection layer. You only know how many are killed. This is where bitmap correlation can also be a strong asset. When you match a defect with a memory bit location you can be sure that that die was killed by the detected defect. In addition, adding physical failure analysis (PFA) can tell defect modes captured as well as those missed by the inspection system. Depending

on the inspection system and sensitivity, small defects in dense arrays may be missed, Fig. 13. This information once again can assist in designing the most effective inspection strategy.

Table I shows an example of a wafer with die level, bit level and PFA results and the composite yield loss accounted for. In this case we use a PFA defect sample of 10% of the SRAM failing bitmap dies to project the yield loss by layer. Fig. 12 and Fig. 13 show examples of defects detected and undetected by the in-line inspection system respectively.

VIII. PRACTICAL CONSIDERATIONS

A. Dissimilar Populations Even though the die level analysis discussed in this paper

was developed for individual wafers, it can be applied to various populations, e.g. the sum of all wafers in a lot to enhance the statistics with higher numbers, as discussed in section IV, as well as sub groups of wafer data to extract more detailed root-cause information. A combination of analyses might be needed at times to fully extract and confirm findings.

An individual wafer population can be considered as a combined population of wafer zones which may have been impacted by different aspects of process issues, such as radially distributed defects and failed die. Splitting wafer data into wafer zone sub groups such as wafer edge and wafer center can filter out high confidence cases and potential root-causes for these individual zones.

An error can be made for the calculation of random hits when data sets of dissimilar characteristics are combined, potentially impacting the die level analysis results. Consider two sets of data, 1 and 2, of equal size for simplicity. If Hr is the full population random hit estimation and the sub population random hit numbers hr are proportional to the number of failed die f, and the number of die with defect d

Table I. Integration of Yield Analysis Results

Figure 12. Detected defects at FEOL inspection Figure 13. Undetected defects at FEOL inspected layer



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(10). When comparing the sum (11) to the die level calculation for the combined population Hr in (12) the difference is obvious due to the mixed terms in the multiplication.

22r2

11r1

dfhdfh

∝∝ (10)

2211r2r1 dfdfhh +=+ (11) ( )( )2121 ddff ++∝rH (12)

Nevertheless, the % error calculates to (13) and is only significant when both f and d are significantly different between the sub groups.

+

+

−

−

=

2

1

2

1

2

1

2

1

dd1

ff1

dd1

ff1

rHε (13)

This error is plotted as a surface plot in Fig. 14, which

shows a flat region <10% for most of the parameter space of both ratios f1/f2 and d1/d2. Even for both ratios at 0.5, e.g. a wafer edge with both double the fail and defect rate compared to the wafer center, the error is only around 10%. Such non uniformities are rare in our wafer production. For an extreme nonuniform case for both f and d, shown in Fig. 10e the error in Hr amounts to less than 7%, with an error of only 0.2 for Confidence Factor, which would not have altered the correlation findings significantly. In our typical production data, failed die data differ by less than 15% between wafer edge and wafer center. Even for defect data of very unusual and uneven distribution, such as in Fig. 10e, the error in Hr is less than 3%, which will increase CF numbers by less than 0.1, and not change the wafer die level calculation findings drastically. Similarly, die level analysis of production lot data with variation between wafers, produced similar CF compared to summing random hit numbers of individual wafers. No difference was found for filtering out high CF cases.

In summary, errors can be part of die level analysis due to cases of nonrandom distributions of fail and defect data. Nevertheless in our experience the error is small and typically does not alter results. In questionable cases it can be advisable to run die level analysis on different groups of data, i.e. on lot level, wafer level and/or wafer zones, to filter out root-cause information.

B. Coincidental Correlations In wafer fabrication it is common to have distributions in a

radial pattern on a wafer, parametric variations, defects, and yield. For these radial distributions one has to proceed with additional checks to avoid erroneous conclusions with regard to root cause analysis. The analysis presented in this paper can also be prone to erroneous conclusions under certain conditions. For example, suppose that a wafer has very low or

zero yield in the outer 10% of the wafer radius. Suppose as well that an inspection layer detected a high defect level entirely in this same outer zone. Using the statistics outlined here on the entire wafer would lead you to conclude there was a high probability that the failures were caused by the detected defects. The conclusion may be false. The correlation of defects and failed dies could be coincidental. What techniques might be used to accurately conclude about the root cause?

In Fig. 10 above we showed an example of using defect classification to segregate defect populations from one tool. However, if the defects still overlay a 100% die fail zone, you cannot conclude statistically that you have identified the root cause. Bin analysis as described in Section VI above might provide the needed separation of the die populations allowing an overlap between defects and failures. An embedded memory bitmap overlay with defects might provide the needed resolution, but ultimately in order to conclude statistically from die and defect overlay alone whether within a wafer zone or another die population, both pass and fail dies, and dies with and without defects are required in the zone analyzed in order to conclude a correlation is found. Some common patterns such as shown in Fig. 6b, may be concluded based on 100% fail zones and defect correlations, but the wafer was identified by the statistical test, the conclusion in this case is by engineering judgment. When there is significant risk of coincidental correlation, it may only be possible to conclude about the root cause through physical failure analysis (PFA), but in 100% fail zones not very many samples are required to conclude the primary root cause.

IX. CONCLUSION This paper presents a yield analysis method using basic

yield and in-line defect information to statistically determine significant root-causes of yield loss in semiconductor manufacturing. Using simple statistics on pass/fail die and

Fig. 14. Error in Hr for combined populations of dissimilar failure and defect die counts



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defect maps, this method provides the fab process line with feedback on the yield loss impact for defect inspected process layers. This tool is also applied to the selection of the most effective inspection tool or recipe. A detailed understanding of the inspection equipment is not required for its application.

Analysis by test bins, defect size and type provide further resolution to killer defect risks and benefits of elimination. This model is readily extended to yield forecasting using a limited yield model or similar approach [5], [6].

Die level correlation quickly produces valuable information for root causes of yield loss. It is simple in data management without the need for detailed test or defect information. Enhanced methods through data segregation can be employed to extract higher resolution information of root-causes.

ACKNOWLEDGMENT The authors wish to thank Toan Nguyen and Shiree Burt of

the Lattice Foundry Operations team for their tireless efforts in failure analysis development and practice in support of the comprehensive failure accounting system. Without their help this effort would only be half done. We would also like to acknowledge Toshio Takayama of Fujitsu Semiconductor Limited and the entire fab team for their strong support over the many years of our partnership. Without their cooperation and support this work would not have been possible.

REFERENCES [1] K. Mori, S. Hsieh, “Yield improvement procedures for particle defects,”

Proceedings of The 4th Annual International Conference on Industrial Engineering Theory, Applications and Practice, November 17-20, 1999, San Antonio, Tx.

[2] M. P.-L. Ooi, W. J. Tee, Y. C. Kuang, L. Kleeman, S. Demidenko, “Fast accurate automatic defect cluster extraction for semiconductor wafers,” International Symposium on Electronic Design, Test & Applications, 2010, pp. 276-280

[3] R. Nurani, R. Akella, A.J. Strojwas, “In-line defect sampling methodology in yield management: An integrated framework,” IEEE Transactions on Semiconductor Manufacturing, Vol. 9. No. 4, November 1996

[4] B.Walsh, J. Colt Jr., D. Poindexter, T. Joseph, “45nm yield model optimization,” Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI, pp1-4.

[5] M. Baron, A. Takken, E. Yashchin, M. Lanzerotti, “Modeling and forecasting of defect-limited yield in semiconductor manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 21, No. 4, November 2008.

[6] S. L. Riley, “Limitations to estimating yield based on in-line defect measurements,” International Symposium on Defect and Fault Tolerance in VLSI Systems, 1999, pp 46-54.

[7] U. Hessinger, W. Chan, B. Schafman, T. Nguyen, S. Burt, “Statistical Correlation of Inline Defect to Sort Test in Semiconductor Manufacturing,” Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24nd Annual IEEE/SEMI, pp 212-219

Uwe Hessinger received a Ph.D. degree in physics, and a Master of Science in Material Science from University of Washington, Seattle, WA, in 1996.

He is currently a Senior Staff Device Engineer for Lattice Semiconductor, Hillsboro, OR. Since 1996 he has primarily worked in technology

development and foundry operations. He has managed several manufacturing process lines, with focus on root-cause analysis, development of yield enhancement methods, and new product releases.

Dr. Hessinger published and presented “Statistical Correlation of Inline Defect to Sort Test in Semiconductor Manufacturing” at ASMC 2013. He has publications for his university research in growth kinetics in semiconductor processing, and received awards from the Materials Research Society and American Vacuum Society for this work.

Wendy K. Chan received the B.S. degree in electrical engineering from Cornell University, Ithaca, NY, in 1992.

She is currently a Staff Device Engineer for Lattice Semiconductor, Hillsboro, OR. Since 1997 she has worked in technology development and foundry operations, with a focus on parametric test, yield

enhancement, and data mining and automation. From 1992 to 1997, she worked as a Device Engineer for Motorola Semiconductor in the MEMS fab, Phoenix, AZ.

Brett T. Schafman. (M’79-SM’06) received a B.S. degree in electrical engineering from University of Illinois at Urbana, Illinois, in 1981 and certificates in project management from Portland State University in 1991 and Stanford Executive Institute from Stanford University in 2001.

He is the Director of Foundry Operations at Lattice Semiconductor where he has been since 1991. Prior to Lattice he worked on the development and manufacturing of laser reticle writing systems for ATEQ Corporation from 1986, and in technology development and new technology engineering departments for Intel Corporation from 1981. He has previously authored papers for SPIE and ASMC conferences.

Mr. Schafman is a senior member of IEEE.

data mining for significance in yield-defect correlation analysis

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