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Data Converter Architectures

DAC Architectures

Figures from CMOS Circuit Design, Layout, and Simulation

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DAC Architectures

Digital to analog Conversion can be

achieved using :

A) Voltage Division

B) Current Steering

C) Charge Scaling

DAC Architecture that we will study will be primarily

based on these!

Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

Different types of input codes to DAC

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Figures from CMOS Circuit Design, Layout, and Simulation

A simple resistor string DAC fails in maintaining balance between area and power.

As resolution increases, relative accuracy of the resistor string becomes an important factor

(Derivation of INL).

High RC time constant (slow). Remedy is to use binary switch array.

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

+ terminal always at GND/Virtual Gnd.

There are problems: a) Vomax=Vref/2-1LSB

Adv.: Common mode Voltage is fixed.

Requires matching to be within the resolution of the converter. Also switch resistance need to besmall (voltage drop will induce error).

Use dummy switches.

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7/32Figures from CMOS Circuit Design, Layout, and Simulation

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8/32Figures from CMOS Circuit Design, Layout, and Simulation

Two Flavors: a) Unit Elements (monotonic)

b) Binary weighted.

(2^N)-1 sources required.

Good current drive inherent in the system.

Area and size of elements?

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11/32Figures from CMOS Circuit Design, Layout, and Simulation

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12/32Figures from CMOS Circuit Design, Layout, and Simulation

When the capacitor is fabricated, undercutting of the mask causes an error in the ratio of thecapacitors, creating potentially large DNL and INL errors as N increases.

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Wet and Dry Etching

In etching, a liquid orplasma chemical agent removes the uppermost layer

of the substrate in the areas that are not protected by photoresist.

Undercutting of the Resist. Poor adhesion of the resist to the masking film

can lead to undercutting during the wet etching process, causing windows

or features that are larger in size than intended. Undercutting, or the

unwanted exposure and etching of a material beyond its defined limits, is aphenomenon caused by the capillary action of the wet chemicals used for

etching. Larger windows caused by undercutting can cause adjacent metal

lines to become short-circuited.

Figures from CMOS Circuit Design, Layout, and Simulation

http://en.wikipedia.org/wiki/Plasma_(physics)http://en.wikipedia.org/wiki/Plasma_(physics)

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15/32Figures from CMOS Circuit Design, Layout, and Simulation

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LSB first

For n- bit word how many clock cycles are needed.

Biggest benefit?

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17/32Figures from CMOS Circuit Design, Layout, and Simulation

N clock Latency!

Just a variation of Cyclic

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All of them are clocked

comparators.

Sources of errors: RESISTOR

STRING MISMATCH &

COMPARATOR OFSET .

For N bits, how manyComparator/Resistors?

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19/32Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

How to Get rid-of RC?

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

At the end, RC is cancelled.

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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Figures from CMOS Circuit Design, Layout, and Simulation

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