method and apparatus for testing data converter

(19) United States US 20100079317A1

(12) Patent Application Publication (10) Pub. No.: US 2010/0079317 A1 Feddeler et al. (43) Pub. Date: Apr. 1, 2010

(54) METHOD AND APPARATUS FOR TESTING Publication Classi?cation DATA CONVERTER (51) Int CL

H03M 1/10 (2006.01) (76) Inventors: James R. Feddeler, Austin, TX H03M 1/66 (200601)

(Us); Michael T_ Berens’ Austin, (52) US. Cl. ....................................... .. 341/120; 341/144

TX (Us) (57) ABSTRACT

A data converter for converting analog signals to digital sig Correspondence Address: nals, or for converting digital signals to analog signals is FREESCALE SEMICONDUCTOR, INC, provided. In one embodiment, a production self-test is pro LAW DEPARTMENT vided. In one embodiment, a high-speed lower-resolution 7700 WEST P ARMER LANE MD=TX32IPL02 method or mode for a data converter is provided. In one AUSTIN TX 78729 (Us) embodiment, a differential data converter With a more stable

’ comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data

(21) App1_ NO; 12/242,058 converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously

(22) Filed: Sep. 30, 2008 stored calibration value is provided.

VREFL 90 V PORTION OF DATA

66 Lg“ ‘glzN ‘QM / CONVERTER 12 H l

CALIBRATION DIFFERENTIAL CONTROL 80 -\ DAC COMPARATOR R 60 _ CI CUITRY FIGS. 4. 1O +\<,/ SAR REGISTER |/ 96

M REF - 64 _\ / SAR CONTROL — DAC \_ 82 CIRCUITRY E

DAC ARRAYS \ 6?. ‘\UNCALIBRATED

I RESULT 34

ERRoR / 78 DETERMINATION

CIRCUITRY

CALIBRATION ‘ STORAGE CIRCUITRY 72

i8. ACCUMULATOR 74 (.1

RESULT COMPUTATION ADJUSTMENT CIRCUITRY CIRCUITRY

;\REsuLT as

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Apr. 1, 2010 Sheet 5 0f 17

140 K START )

142 ?

CHARGE CAPACITOR BOTTOM PLATE TO VREFL 90 AND ALL LOWER

SIGNIFICANCE CAPACITOR BOTTOM PLATES ‘TO VREFH 88 IN SAMPLE

PHASE WHILE CHARGING COMPARATOR INPUTS TO VCM 94

f 170

160. ( START I

' g162

I - CHARGING COMPARATOR INPUTS TO

CHARGE BOTTOM PLATE OF ALL CAPACITORS TO VIN 92 WHILE

TO VCM 94

$163 145 2 ,

RELEASE COMPARATOR INPUTS

RELEASE COMPARATOR INPUTS

i164 144 2

SWITCH CAPACITOR BOTTOM PLATE TO VREFH 88 AND ALL LOWER

SIGNIFICANCE CAPACITOR BOTTOM PLATES TO VREFL 90 IN COMPARE

' PHASE

SWITCH BOTTOM PLATES OF ALL CAPACITORS TO VREFL 9O

‘ 165

PERFORM NORMAL SAR ROUTINE TO PRODUCE UNCALIBRATED RESULT 84

145 2 ,

RUN SUCCESSIVE-APPROXIMATION ON SELECTED BITS

, <166

146 2

ACCUMULATE RESULTS OF SAR REGISTER AND STORE IN

CALIBRATION STORAGE CIRCUITRY 68

ACCUMULATE CALIBRATION VALUES OF ALL CALIBRATED CAPACITORS WHOSE BOTTOM PLATES REMAINED AT VREFH 88 AT THE END OF

THE CONVERSION

T

CORRESPONDING TO THE CAPACITOR

147 HAVE

. ALL DESIRED

CAPACITORS BEEN CALIBRATED?

SUBTRACT .THIS ACCUMULATED VALUE FROM THE UNCALIBRATED CONVERSION RESULT TO PRODUCE THE CALIBRATED

RESULT

US 2010/0079317 A1

L 161 I

END

FIG. 6'


NON—MONOT$ITIES MISSING 0005(3)

/ 23mm

FIG. 7 —PRIOR ART —

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MISSING 0005(3)

VIN '92 FIG. 8

M

@w Z381 821243 N0 MISSING CODES. HIGH LINEARITY

VIN >92 FIG. .9


250 ( START ) ,/ 271

1

CHARCE BOTTOM PLATE OF ALL DAC NSB 252 CAPACITORS (E.G. BITS 15:11 ANO ExTRA CAPACITOR) TO vIN 92 wHILE CHARCINC

THE COMPARATOR INPuTS TO vCN 94

T

RELEASE CONPARATOR INPUTS THEN £53 SwITCH BOTTOM PLATES OF ALL

CAPACITORS TO vREEL 90

SWITCH ALL OF THE OAC MSB CAPACITOR 254 (EC. BITS 15:11 AND ExTRA CAPACITOR)

BOTTOM PLATES TO VREFH 88

THE COMPARATOR YES OUTPUT LOW? 258

4 256 F) N0 r_) SET AND CLEAR APPROPRIATE

BITS (EC. SET BIT 16 AND CLEAR EXTRA BIT (BIT 16) , ~()LEAR BITS 15;")

PERFORM NORMAL SAR ROUTINE ON »~J SELECTED BITS (EC. BITS 15:11)

' 259 PERFORM NORMAL SAR ROUTINE ON *‘J

REMAINING BITS (EC. BITS 10:0) TO PRODUCE AN UNCALIBRATED RESULT <

HAVINC AN EXTRA BIT (EC. 17 BIT RESULT UP TO $107FF)

1

MODIFY UNCALIBRATED RESULT TO ACHIEVE ~J DIGITAL CAIN, OFFSET, OR LINEARITY CALIBRATION TO PRODUCE CALIBRATED

RESULT (EC. 16 BIT RESULT UP TO SFFFF)

251 END

FIG. 11


AFTER OFFSET CALIBRATION IDEAL - “ ' AND ExTRA SUCCESSIVE 243

APPROXIMATION STEP ,_J /

I

UNCALIBRATED 241 RESULT AFTER OFFSET

l I l

CALIBRATION I 242 T l | l l | | LO NM 5 ‘Y4 240

FIG. 12

AFTER LINEARITY CALIBRATION, GAIN CALIBRATION, AND EXTRA

SUCCESSIVE APPROXIMATION STEP

IDEAL “ AFTER LINEARITY CALIBRATION, \

' GAIN CALIBRATION 4247

246 245 244 RESULT AFTER LINEARITY CALIBRATION

(ILLUSTRATES GAIN ERROR)

FIG. 13


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[320 300

( START I

$302 CHARGE BOTTOM PLATE OF MINUS DAC 282

CAPACITORS TO VIN 93 CHARGE BOTTOM PLATE 0F PLUS DAC 280 CAPACITORS TO VIN 92

CHARGE BOTTOM PLATE OF DIFFERENTIAL BIAS CAPACITOR 208 T0 VREFH 88 WHILE CHARGING

THE COMPARATOR INPUTS TO VCM 94

WAS DIFFERENTIAL

BIAS CAPACITOR 2O8 SWITCHED?

‘ y 303 RESULT 286 EQUALS

RELEASE cOMPARATOR INPUTS AND SWITCH ~ THE DIFFERENTIAL RESULT ‘

THE BOTTOM PLATES OF ALL CAPACITORS

To VREFL 90 SUBTRACT PREDETERMINE gIDA AMOUNT FROM DIFFERENTIAL

- RESULT TO PRODUCE PERFORM A PARTIAL SUCCESSIVE APPROxIMATIONl RESULT 286 ON THE MINUS- DAC 282 UNTIL THE INVERTING ( COMPARATOR INPUT 1S SUBSTANTIALLY NEAR . 310 THE COMPARATOR'S 260, 261 COMMON MODE INPUT VOLTAGE (VCM 94). (NOTE THAT 301

THE MINUS RESULT IS THE SERIAL OUTPUT END OF THE NON-CRITICAL COMPARATOR 261)

305 F596 SWITCH THE BOTTOM PLATE OF

THE DIFFERENTIAL CAPACITOR 208 TO VREFL 9O

THE CRITICAL COMPARATOR 260 OUTPUT HIGH?

NO

v

PERFORM FULL SUCCESSIVE APPROxIMATION 53,07 . ON THE PLUS DAC 280

(NOTE THAT THE PLUS RESULT IS THE SERIAL OUTPUT OF THE CRITICAL COMPARATOR 260)

Y

SUBTRACT MINUS RESULT 285 FROM PLUS $08 RESULT 284 TO PRODUCE A DIFFERENTIAL

RESULT

FIG. 15


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'( START I 500

Apr. 1, 2010 Sheet 15 0f 17

502 DURING THE SAMPLE PHASE: - CHARGE ALL CAPACITORS ON THE SAME SIDE (PLUS

DAC 480 OR MINUS DAC 480) SMALLER THAN CAPACITOR UNDER TEST To VREFH 88 THROUGH SWITCHING CIRCUITRY 299 ([SE FIG. 10) AND VIN 92

- CHARGE CAPACITOR UNDER EST AND ALL LARGER CAPACITORS ON THE SAME SIDE TO vREFL 9O

- CHARGE OPPOSING SIDE TO A PREDETERMINED OFFSET VOLTAGE . .

503 DURING THE HOLD PHASE: - RELEASE COMPARATOR INPUTS USING SwITC CIRCUITRY 102 (SEE FIG. 10) ' CHARGE CAPACITOR UNDER TEST TO vREFH as CHARGE ALL CAPACITORS ON OPPOSING SIDE TO vREFL 90 '

CHARGE ALL REMAINING CAPACITORS A ON THE SAME SIDE TO vREFL 90

T

I 504 DURING THE COMPARE PHASE: - ON THE OPPOSING SIDE, RUN FULLY SINGLE-ENDED

TO SUCCESSIVE APPROXIMATION

T

5Q5A DURING RESULT PROCESSING: — COMPARE ‘RESULT 484 (SEE FIG. 18) TO -

PREDETERMINED OFFSET VALUE STORED DURI SAMPLE PHASE -

- SET LIMITS ON COMPARISON BASED ON REQUIRE MATCHING TOLERANCE AND NOISE ALLOWANCE

501 END

_ FIG; 19

US 2010/0079317 A1

f 520

REPEAT FOR EACH CAPACITOR UNDER TEST EXCEPT SMALLEST UNIT OR UNITS LESS THAN THE NOISE OR MISMATCH TOLERANCE

- REPEAT FOR

CAPACITORS ON THE OPPOSING SIDE


@117 550

Apr. 1, 2010 Sheet 16 0f 17 US 2010/0079317 A1

g552 DURING THE SAMPLE PHASE: — CHARGE ALL UNITS SMALLER THAN

CAPACITOR UNDER TEST TO VREFH 88 EXCEPT X UNITS THROUGH SWITCHING CIRCUITRY 299 (SEE FIG. 10)

— CHARGE CAPACITOR UNDER TEST AND ALL LARGER UNITS TO VREFL 9O

— REFERENCE SIDE CHARGED TO VREFL 90 DURING ENTIRE SEQUENCE

gas; I

§556 T

DURING THE SAMPLE PHASE: — CHARGE ALL UNITS SMALLER THAN

CAPACITOR UNDER TEST TO VREFH 88 EXCEPT Y UNITS THROUGH SWITCHING CIRCUITRY 299 (SEE FIG. 10)

— CHARGE ONE UNIT > CAPACITOR UNDER TEST TO VREFH 88 FOR OFFSET SHIFT

— CHARGE CAPACITOR UNDER TEST AND ALL OTHER LARGER UNITS TO VREFL 9O

— REFERENCE SIDE CHARGED TO VREFL 9O DURING ENTIRE SEQUENCE

DURING THE HOLD PHASE: — RELEASE COMPARATOR INPUTS USING

SWITCH CIRCUITRY 102 (SEE FIG. 10) — CHARGE CAPACITOR UNDER TEST TO

VREFH 88

g554 DURING THE COMPARE PHASE: — RUN SUCCESSIVE APPROXIMATION

(RESULT SHOULD BE CENTERED AT X, AND SHOULD BE LESS THAN CAPACITOR UNDER TEST)

g555 T

DURING RESULT PROCESSING: ‘ — COMPARE RESULT TO X VALUE

STORED IN SAMPLE PHASE — SET LIMITS ON COMPARISON BASED

ON REQUIRED MATCHING TOLERANCE AND NOISE ALLOWANCE

CAPACITORS UNDER TEST GREATER THAN X

BEEN TESTED?

FIG. 20

§557 DURING THE HOLD PHASE/COMPARE/ RESULT: — FOLLOW PREVIOUS ROUTINE — RESULT SHOULD BE CENTERED AT

OFFSET + Y (CAPACITOR UNDER TEST SHOULD NOT SET)

CAPACITORS UNDER TEST GREATER THAN Y

BEEN TESTED?

NOTES: X REPRESENTS A NUMBER OF IDEALLY SIZED UNITS EQUAL TO THE MAXIMUM EXPECTED (UNSIGNED) ERROR OF THE CAPACITOR UNDER TEST, PLUS DESIRED OFFSET. FOR EXAMPLE, IF A CAPACITOR IS SUPPOSED TO BE 64LSB +/ 4LSB AND THE DESIRED OFFSET IS 12, X SHOULD BE EQUAL TO 16. WHEN X IS EQUAL/LARGER THAN CAPACITOR UNDER TEST, OFFSET MUST BE INCREASED TO BE GREATER THAN CAPACITOR UNDER TEST BY SETTING ONE UNIT GREATER THAN THE CAPACITOR UNDER TEST FOR OFFSET (TO KEEP RESULT FROM BEING TOO NEAR ZERO) AND THEN SETTING A NEW VALUE Y EQUAL TO THE EXPECTED ERROR ONLY.


COMPARATOR OFFSET TESTED AOAINST DESIRED

DIFFERENTIAL L IN H L IN H L IN H L IN H L IN H OFFSET VALUE SIDE TESTED IN REVERSE l i l COMPARATOR SPEED PROCEDURE ' \ ' \ ’ ‘ ' \ ' \ TESTED IN SUCCESSIVE

A g, ~ - - - ~ APPROXIMATION TESTS

VREFL SwITCH TESTED IN SAMPLET T T T T \ — ‘2

PHASE OF A CUTN N_1 TESTS , - - - - ~ +

AND 'HOLD PHASE-L J- "L J- J FOR CUTN+1 TESTS ' ' ' \

¥_,\ / S / \ , \ , \ fCUT AND CORRESPONDINC

- T T T T T T T T VREFH SwITCH TESTED T T T T I IN COMPARE PHASE OF r» L IN H L IN H -L IN H L IN H L IN H CUTN TEST

VIN SWITCH TESTED IN ' SMALLEST CUT(S) TESTED ACAINST SEQUENCE SAMPLE PHASE OF CUTNH LARCE CUTS IN SAMPLE PHASES TESTS AND A SINGLE, FULL FOR CUTN+1 TESTS ("+1 > MINIMUM

RAIL CONVERSION TO NOISE OR MATCHING TOLERANCE) VREFH FOR LARCEST CUT

FIG. 21 , 600

( START ) r620

CHARGE BOTTOM PLATE OF MSB CAPACITORS M9, 219 F302 (HALF OF THE TOTAL CAPACITANCE) TO VIN 92

WHILE CHARGING THE COMPARATOR INPUTS TO VCM 94

T

RELEASE COMPARATOR INPUTS AND SWITCH THE BOTTOM pg PLATE 0F MSB CAPACITORS 119, 219 T0 VREFL 90

Y

PERFORM A SUCCESSIVE APPROXIMATION ON THE 13 OR N694 14 MOST SIGNIFICANT BITS TO PRODUCE A 13 OR

14-BIT CONVERSION RESULT OF VIN/2

V

SHIFT THE CONVERSION RESULT LEFT (DOUBLE) AND i595 ROUND (IF DESIRED) TO GET THE 1/2 LSB SHIFT

TO PRODUCE A 12-BIT CONVERSION RESULT

@601 FIG. 22

US 2010/0079317 A1

METHOD AND APPARATUS FOR TESTING DATA CONVERTER

CROSS-REFERENCE TO RELATED

APPLICATION(S) [0001] This application is related to US. patent application Ser. No. (Attorney Docket No. AC50035TC), ?led on even date, entitled “DATA CONVERSION CIRCUITRY AND METHOD THEREFOR,” and assigned to the current assignee hereof. [0002] This application is related to US. patent application Ser. No. (Attorney Docket No. AC50036TC), ?led on even date, entitled “DATA CONVERSION CIRCUITRY AND METHOD THEREFOR,” and assigned to the current assignee hereof. [0003] This application is related to US. patent application Ser. No. (Attorney Docket No. AC50037TC), ?led on even date, entitled “DATA CONVERSION CIRCUITRY AND METHOD THEREFOR,” and assigned to the current assignee hereof. [0004] This application is related to US. patent application Ser. No. (Attorney Docket No. AC50038TC), ?led on even date, entitled “DATA CONVERSION CIRCUITRY AND METHOD THEREFOR,” and assigned to the current assignee hereof.

BACKGROUND

[0005] 1. Field [0006] This disclosure relates generally to electrical cir cuitry, and more speci?cally, to electrical circuitry for data conversion. [0007] 2. RelatedArt [0008] Data converters are very useful for converting ana log signals to digital signals, and for converting digital signals to analog signals. Many applications require data converters that have a high resolution, fast conversion time, alloW a broad range of inputs, and yet are cost effective. Other data conversion features may also be important for various appli cations. It is thus important to be able to provide data con ver‘ters that meet a Wide variety of potentially con?icting criteria, While at the same time remain cost effective.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention is illustrated by Way of example and is not limited by the accompanying ?gures, in Which like references indicate similar elements. Elements in the ?gures are illustrated for simplicity and clarity and have not necessarily been draWn to scale. [0010] FIG. 1 illustrates, inblock diagram form, a system in accordance With one embodiment. [0011] FIG. 2 illustrates, in partial block diagram form and partial schematic diagram form, a portion of a data converter in accordance With one embodiment. [0012] FIG. 3 illustrates, in partial block diagram form and partial schematic diagram form, a portion of a data converter in accordance With one embodiment.

[0013] FIG. 4 illustrates, in partial block diagram form and partial schematic diagram form, a portion of a DAC in accor dance With one embodiment.

[0014] FIG. 5 illustrates, in How diagram form, a sample calibration method in accordance With one embodiment. [0015] FIG. 6 illustrates, in How diagram form, a sample conversion method in accordance With one embodiment.

Apr. 1,2010

[0016] FIG. 7 illustrates, in graphical diagram form, non linearities due to capacitor mismatch in a binary-Weighted DAC in accordance With the prior art. [0017] FIG. 8 illustrates, in graphical diagram form, non linearities due to capacitor mismatch in a binary-Weighted DAC With oversiZed ?rst scaling capacitor in accordance With one embodiment.

[0018] FIG. 9 illustrates, in graphical diagram form, non linearities due to capacitor mismatch in a binary-Weighted DAC With oversiZed ?rst scaling capacitor after calibration in accordance With one embodiment. [0019] FIG. 10 illustrates, in partial block diagram form and partial schematic diagram form, a portion of a DAC in accordance With one embodiment.

[0020] FIG. 11 illustrates, in How diagram form, a sample conversion method for a 16-bit analog to digital converter (ADC) in accordance With one embodiment. [0021] FIG. 12 illustrates, in graphical diagram form, a transfer function of an ADC With digitally calibrated offset in accordance With one embodiment. [0022] FIG. 13 illustrates, in graphical diagram form, a transfer function of an ADC With digital linearity and gain calibration in accordance With one embodiment. [0023] FIG. 14 illustrates, in partial block diagram form and partial schematic diagram form, a portion of a data con ver‘ter in accordance With one embodiment.

[0024] FIG. 15 illustrates, in How diagram form, a sample differential conversion method in accordance With one embodiment. [0025] FIG. 16 illustrates, in graphical diagram form, an example of a differential conversion in accordance With one embodiment. [0026] FIG. 17 illustrates, in graphical diagram form, another example of a differential conversion in accordance With one embodiment.

[0027] FIG. 18 illustrates, in partial block diagram form and partial schematic diagram form, a portion of a data con ver‘ter in accordance With one embodiment. [0028] FIG. 19 illustrates, in How diagram form, a self-test method for a differential capacitive DAC in accordance With one embodiment.

[0029] FIG. 20 illustrates, in How diagram form, a self-test method for a single-ended capacitive DAC in accordance With one embodiment.

[0030] FIG. 21 illustrates, in schematic diagram form, test coverage of a self-test method in accordance With one embodiment. [0031] FIG. 22 illustrates, in How diagram form, a method for performing a 12-bit conversion in a 16-bit ADC in accor dance With one embodiment.

DETAILED DESCRIPTION

[0032] FIG. 1 illustrates one embodiment of a system 10. In alternate embodiments, system 10 may be implemented as a single integrated circuit, may be implemented as a plurality of integrated circuits, or may be implemented as a combination of integrated circuits and discrete components. Alternate embodiments may implement system 10 in any manner. [0033] In one embodiment, system 10 comprises data con ver‘ter 12, other modules 14, processor 16, memory 18, and external bus interface 20, Which are all bi-directionally coupled to each other by Way of a bus 22 or a plurality of electrical signals 22. In one embodiment, system 10 can receive inputs and provide outputs by Way of a bus 24 or a

US 2010/0079317 A1

plurality of electrical signals 24 coupled to external bus inter face 20. In alternate embodiments, system 10 may comprises feWer, more, or different blocks of circuitry than those illus trated in FIG. 1.

[0034] FIG. 2 illustrates one embodiment of a portion of data converter 12 of FIG. 1. In one embodiment, data con verter 12 comprises an ADC Which may be used to convert a differential input voltage VIN 92-VIN 93 into a digital rep resentation stored as a multi-bit binary value in a data register (e.g. ADCRHAzADCRLA or ADCRHBzADCRLB). In one embodiment, this digital representation may be of the value 2AAN*(V IN 92-VIN 93)/ (V REFSH 88-VREFSL 90), Where N is the resolution, or number of bits, in data converter 12. In one embodiment, data converter 12 comprises a ?rst input multiplexer Which chooses from among a plurality of positive input voltages (DADP[0:3], AD[4:23], TEMPP) based on softWare con?guration (ADCHN) to create VIN 92, and Which also comprises a second input multiplexer Which chooses from among a plurality of negative input voltages (DADM[0:3], TEMPM) to create VIN 93. Data converter 12 also comprises a reference multiplexer Which chooses from among a plurality of positive reference voltages (V REFH, VALTH, VBGH) to create VREFH 88, and a second reference multiplexer Which chooses from among a plurality of nega tive reference voltages (VREFL, VALTL, VBGL) to create VREFL 90. Note that the terms “positive” and “negative” indicate the polarity of the signal relative to the other, and not to a ?xed reference such as ground. In one embodiment, both positive and negative signals and references are alWays equal to or greater than a ground reference. Alternate embodiments may function in a different manner.

[0035] For one embodiment, the SAR (successive approxi mation register) control circuitry 76 begins a conversion by placing the SAR Converter in an initial condition by asserting the INITIALIZE signal. A conversion Will begin When a trigger to convert signal (TRIGGER) is received by the SAR control circuitry 76 from the conversion trigger control cir cuit. Alternate embodiments may provide a trigger signal due to a variety of different circumstances. For example, a trigger may be received When a softWare register bit is Written (ADTRG), or When a hardWare signal ADHWT is received in the right conditions (e. g. these conditions may be determined by softWare con?guration [ADCSC1A-ADCSC1N, ADCSC2, ADCCFG1 and ADCCFG2] and/or hardWare sig nal conditioning [ADHWTSA-ADHWTSN]). When the asserted trigger signal is received, the SAR control circuitry 76 asserts the SAMPLE condition to the SAR converter, Which in turn samples the differential input voltage VIN 92-VIN 93 on the SAR array. The sample value can be modi ?ed by the PG and MG con?gurations stored in the calibration storage circuitry 68. [0036] In one embodiment, the SAR converter samples for a period indicated by softWare con?guration (ADLSMP, ADLSTS) in a multiple of the ADC input clock (ADCK) periods. The ADCK period may be controlled by softWare con?gurations (ADIV, ADICLK, ADACKEN) and hardWare clock sources (ADACK, BUS_CLOCK, and ALTCLK). The SAR control circuitry 76 then places the SAR converter into CONVERT mode. In one embodiment of CONVERT mode, the SAR converter subsequently compares the input voltage (VIN 92-VIN 93) to different fractions of the reference volt age (V REFSH 88-VREFSL 90). During each comparison, the converter successively sets or clears the corresponding digital output bit based on the compare result, and then

Apr. 1,2010

changes either the reference voltage or the input voltage by the appropriate fraction of the reference voltage (eg if com paring the input voltage to the reference voltage divided by tWo, if the comparison is greater, the output bit is set and the next comparison is to 3/4 times the reference voltage; if less, the output bit is cleared and the next comparison is to 1A times the reference voltage; either the reference voltage or the input voltage may be modi?ed during successive approximation). [0037] As the SAR converter approximates, it may modify the result as it proceeds With the values CLPx and CLMx stored in the calibration storage circuitry 68. When the SAR converter has made the appropriate number of successive approximations, SAR control circuitry 76 indicates that it is COMPLETE to the SAR trigger circuitry and instructs the SAR converter to TRANSFER the results to the output cir cuitry. In one embodiment, this output circuitry ?rst adjusts for offset in the OFFSET SUBTRACTOR, then employs averaging if so con?gured in the AVERAGER, and then for mats the data in the appropriate manner in the FORMAT TING circuit. These circuits may be controlled by softWare con?guration (ADCOFS, AVGE and AVGS, and MODE and DIFFn, respectively). The offset value OFS used by the OFF SET SUBTRACTOR, as Well as the con?guration values PG, MG, CLPx, and CLMx, may be created before conversion by the calibration control circuitry 66. Once formatted the result is compared to a compare value (CV1) or range (CV1, CV2) in the COMPARE LOGIC. Based on the softWare con?gura tion to the COMPARE LOGIC (ACFE, ACFGT, ACREN) the comparator Will transfer the result to the result registers (AD CRHAzADCRLA to ADCRHNzADCRLN) and set COMP ARE_TRUE. In one embodiment, the conversion trigger logic and SAR control circuitry 76 Will then determine, based on softWare con?guration (ADCO), Whether to begin another conversion or to ABORT the sequence and turn the SAR converter off. Alternate embodiments of the data converter 12 of FIG. 2 may use more, less, or different circuitry to imple ment circuitry for performing data conversion. [0038] FIG. 3 illustrates one embodiment of a portion of data converter 12 of FIG. 1. Referring to FIG. 3, the illustrated successive approximation (SAR) analog-to-digital converter (ADC or A/D converter) comprises a digital-to-analog con verter (DAC) 62 and a comparator 60 in a feedback loop With logic including a successive-approximation (SAR) register 96. In one embodiment, DAC 62 comprises an array of binary Weighted elements (eg capacitors 110-119 of FIG. 4). Alter nate embodiments may use any type of charge redistribution array for data conversion. In addition, alternate embodiments may use any desired and appropriate binary Weighted ele ments (e. g. resistive elements, capacitive elements, a combi nation thereof, etc.). Note that “N”, “M”, and “P” are being used to represent integers. For example, “bN” is the “nth bit” or “bit N”; similarly “b(N+M+P)” is the “(N+M+P)th bit” or “bit (N+M+P)”. [0039] During a conversion, a voltage input VIN 92 is sampled onto the DAC 62; then during a compare phase the DAC capacitors 110-119 are controlled to successively approximate the input voltage VIN 92 using the comparator 60 output to make decisions on hoW to sWitch the capacitors 110-119. At each step of the approximation, the comparator 60 output is stored in the SAR register 96 and the resulting digital Word (uncalibrated result 84) is the digital representa tion of the analog input voltage VIN 92. [0040] As the resolution of an SAR ADC 12 (see FIG. 2) increases, one of the major limitations is element matching

method and apparatus for testing data converter

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