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D2.1 Specifications of PLATON’s 2x2 and 4x4 routing platforms

June 7, 2010 FP7-249135 – ©The PLATON Consortium of 60

ICT - Information and Communication Technologies

Grant Agreement Number 249135

D2.1: Specifications of PLATON’s 2x2 and 4x4 routing platforms

Due Date of Deliverable: 31/05/2010

Actual Submission Date: 07/06/2010

Revision: Final

Start date of project: January 1st 2010 Duration: 36 months Organization name of lead contractor for this deliverable: CERTH Authors: Nikos Pleros, Kostas Vyrsokinos, Dimitris Kalavrouziotis, Giannis

Giannoulis, Matthias Baus, Matthias Karl, Tolga Tekin, Emmanouil Kriezis,

Odysseas Tsilipakos, Alexandros Pitilakis

Merging Plasmonics and Silicon Photonics Technology towards Tb/s routing in optical interconnects

Collaborative Project



Project Information PROJECT

Project name: Project acronym: Project start date: Project duration: Contract number: Project coordinator: Instrument: Activity:

Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects PLATON 01/01/2010 36 months 249135 Nikos Pleros – CERTH STREP THEME CHALLENGE 3: Components, Systems, Engineering

DOCUMENT

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Specifications of PLATON’s 2x2 and 4x4 routing platforms Report

D2.1

31/05/2010

07/06/2010

Nikos Pleros

Kostas Vyrsokinos, Dimitris Kalavrouziotis, Giannis

Giannoulis, Matthias Baus, Matthias Karl, Tolga Tekin,

Emmanouil Kriezis, Odysseas Tsilipakos, Alexandros

Pitilakis

WP2

Design and Ongoing Evaluation of PLATON’s Platform

CERTH

PU

13/04/2010

4/6/2010

final

61

Final



TABLE OF CONTENTS

1 EXECUTIVE SUMMARY................................................................................................................6

2 INTRODUCTION ............................................................................................................................7

2.1 PURPOSE OF THIS DOCUMENT................................................................................................................7

2.2 DOCUMENT STRUCTURE..........................................................................................................................7

2.3 AUDIENCE..................................................................................................................................................7

3 OVERVIEW OF PLATON ROUTING CONCEPT ......................................................................8

4 NETWORK TRAFFIC AND DATA FORMATS..........................................................................9

5 SPECIFICATIONS FOR SOI PLATFORM, WAVEGUIDES AND INTERFACES.............. 14

5.1 SOI PLATFORM ......................................................................................................................................14

5.2 SILICON WAVEGUIDES ..........................................................................................................................14

5.3 DLSPP WAVEGUIDES ...........................................................................................................................15

5.4 FIBER‐TO‐SILICON COUPLING INTERFACES ......................................................................................15

5.5 SILICON‐TO‐DLSPP COUPLING INTERFACES....................................................................................16

6 PLATON COMPONENT SPECIFICATIONS ........................................................................... 17

6.1 SILICON‐ON‐INSULATOR MULTIPLEXING (MUX) CIRCUIT ............................................................17

6.2 HEADER DETECTION / PHOTODIODE.................................................................................................18

6.3 IC ELECTRONIC CONTROL CIRCUITRY ................................................................................................19

6.4 METAL INTERCONNECTS .....................................................................................................................20

6.5 2X2 DIELECTRIC LOADED – SURFACE PLASMON POLARITON (DLSPP) SWITCHING ELEMENT

21

6.6 4X4 DIELECTRIC LOADED – SURFACE PLASMON POLARITON (DLSPP) SWITCHING MATRIX 21

6.7 INTEGRATION CONCEPT.......................................................................................................................22

7 SPECIFICATIONS FOR 2X2 PLATON ROUTING PLATFORM......................................... 24

7.1 SIMULATIONS.........................................................................................................................................24

7.2 2X2 ROUTING PLATFORM SPECIFICATIONS.......................................................................................27

8 SPECIFICATIONS FOR 4X4 PLATON ROUTING PLATFORM......................................... 29

8.1 SIMULATIONS.........................................................................................................................................29

8.2 4X4 ROUTING PLATFORM SPECIFICATIONS.......................................................................................31

9 CONCLUSIONS ............................................................................................................................. 33

10 APPENDIX I: ROUTING LOOKUP TABLE ....................................................................... 34



10.1 ROUTING LOOK‐UP TABLE FOR 2X2 PLATON ROUTER ...............................................................34

10.2 ROUTING LOOK‐UP TABLE FOR 4X4 PLATON ROUTER ...............................................................35



1 Executive Summary

This document provides the preliminary component- and system-level specifications of PLATON’s 2x2 and 4x4 routing platforms. It includes the specifications for all specific PLATON router sub-blocks, like:

- Silicon-on-Insulator (SOI) platform

- Waveguides (Silicon waveguides and Dielectric Loaded – Surface Plasmon Polariton (DLSPP) waveguides)

- Interfaces (fiber-to-Silicon, Silicon-to-DLSPP, electrical)

- Silicon-on-Insulator Multiplexing (MUX) circuit

- Header detection / photodiode

- IC electronic control circuitry

- 2x2 Dielectric Loaded – Surface Plasmon Polariton (DLSPP) switching element

- 4x4 Dielectric Loaded – Surface Plasmon Polariton (DLSPP) switching matrix

- Network Traffic and Data formats

- Final 2x2 PLATON routing platform

- Final 4x4 PLATON routing platform

Since the 2x2 and 4x4 PLATON router systems are in their initial phase of logical and physical design (e.g. exact center wavelength channels for the lasers, the photonic and plasmonic resonant devices will be decided in due course), this document is a “living document”, which reflects the current development status of the different components, their operation, interaction and interface specifications.



2 Introduction

2.1 Purpose of this document

The objective of this deliverable is to provide the component- and system-level specifications for the final 2x2 and 4x4 PLATON router prototypes. It aims to provide an update on the specifications included in Annex I exploiting preliminary results that have been obtained within the project so far, serving also as the basis for eventually future modifications that may arise during project evolution.

2.2 Document structure

The present deliverable is split into six major chapters:

- Overview of PLATON routing concept - Network Traffic and Data Formats - Specifications for SOI platform, waveguides and interfaces - PLATON component specifications - Specifications for 2x2 PLATON routing platform - Specifications for 4x4 PLATON routing platform

2.3 Audience

This document is public.



3 Overview of PLATON routing concept

Figure 3-1: PLATON’s a) 2x2 and b) 4x4 router block diagram

Figure 3-1(a) and (b) show the block diagrams of the PLATON 2x2 and 4x4 router system, respectively. Both routing platforms operate with optical data line-rates of 40Gb/s and reside on a Silicon-on-Insulator Motherboard that hosts all the heterogeneous technologies, namely SOI-based components, Dielectric Loaded Surface Plasmon Polariton (DLSPP) switches, Photodiodes and Integrated Circuit Microcontrollers. The 2x2 router offers an aggregate switching throughput of 560 Gb/s, whereas the 4x4 router provides a total throughput of 1.12 Tb/s. Briefly the role of each router sub-unit is as follows:

1. 7x1 SOI MUX (Multiplexer): This subsystem is used to multiplex the 7 incoming 40Gb/s data traffic carrying wavelengths into a common, single optical traffic stream that will follow the same route through the network. Two and four 7x1 SOI multiplexing modules will be employed in the 2x2 and 4x4 PLATON router platforms, respectively. The SOI MUX will rely on silicon-based photonic integrated components.

2. PD O/E Conversion Stage: Photodiodes integrated on the SOI motherboard will form the O/E conversion stage of the routing platform. PDs will be used for converting the optical header information into respective electrical header pulses to be subsequently processed by the IC Header Processing and Control Circuit. One PD will be employed for every header wavelength, which in turn implies that in the case of the 2x2 and 4x4 router a total number of 2 and 4 PDs will be used, respectively.

3. IC Header Processing and Control Circuit: This subsystem is used for processing the incoming header information and for generating the appropriate electrical control signals that will drive the DLSPP switching matrix. For the 2x2 router, the IC circuit will have two input ports for receiving the respective electrical header pulse streams and will provide two electrical output signals for controlling the state of the 2x2 switching matrix. In the case of the 4x4 router, the IC circuit will incorporate four input and eight output ports.



4. DLSPP switching matrix: The DLSPP switching matrix routes the incoming traffic streams towards the different outputs depending on the header information. PLATON’s switching matrix will rely on Dielectric Loaded Surface Plasmon Polariton (DLSPP)-based thermo-optic switching elements. A 2x2 switching matrix will be used for the 2x2 routing platform, whereas a 4x4 switching matrix consisting of multiple interconnected 2x2 switching structures will be used for the 4x4 PLATON router.

4 Network Traffic and Data Formats

Every traffic stream will comprise 8 wavelengths, 7 of them carrying useful data and one wavelength carrying the header information. This format is fully compliant with optical interconnect applications as each wavelength can be considered as the traffic generated by a respective BladeCard.

1. Data wavelengths: For both the 2x2 and the 4x4 PLATON router demonstrations, the 7 data wavelengths will carry packet-formatted Non-Return-to-Zero (NRZ) traffic at 40Gb/s, with packets that correspond to different wavelengths overlapping in time. A low channel spacing of 100GHz is targeted between the different wavelengths in order to allow for maximum bandwidth utilization occupying a total spectral region of 600GHz, whilst ensuring effective spectral discrimination between the different 40Gb/s channels. The requirement for reserving the minimum possible total bandwidth for the 7 data wavelengths is a crucial factor also towards minimizing the wavelength dependence of the switching performance, given that all wavelengths belonging to the same input traffic stream will have to reside within the bandwidth of a single DLSPP-based interferometric switch in order to emerge at the same router output port. The total duration of each packet will be 1μsec, suggesting that each packet will deliver a total amount of 5kbytes of 40Gb/s data. Guardband intervals between successive packets will be incorporated, with their duration depending on the rise- and fall-times of the DLSPP thermo-optic response. A total guardband duration of less than 250nsec is targeted.

2. Header wavelength: For both the 2x2 and the 4x4 PLATON router demonstrations, the header wavelength will be spaced 100GHz from the 7th and last data wavelength and will carry all the necessary address information that will dictate the route of the total incoming 7-wavelength traffic stream. In the case of the 2x2 router where a decision between two output ports has to be made for each incoming traffic stream, the header information will incorporate two header pulses within a 1μsec interval, suggesting that each header pulse will have a time duration of 500nsec. In the case of the 4x4 router where 4 output ports will be available, the header will comprise 3 pulses within the 1μsec packet duration, implying a header pulse duration of 330nsec. A burst-switching approach will be adopted for the header and data synchronization scheme, with the header information being timely mistuned compared to the respective data packets so as to ensure enough available time for header processing in the IC circuitry. This scheme relaxes the need for delaying or storing the 40Gb/s data packets during switch state determination.

An overview of the network traffic and packet format specifications is provided below:



Figure 4-1: PLATON’s Traffic Format for the 2x2 routing scenario: a) time-domain representation of a single

Traffic Stream, and b) wavelength domain representation of the two traffic streams.

Table 1: Header Content for 2x2 routing

Header Bit#1 Bit#2 Header Content Interpretation 0 0 No packet present

0 1 Exits through Router Out#1 (BAR state) when entering through In#1 H1

1 0 Exits through Router Out#2 (CROSS State) when entering through In#1

0 0 No packet present

0 1 Exits through Router Out#2 (BAR state) when entering through In#2 H2

1 0 Exits through Router Out#1 (CROSS State) when entering through In#2



Table 2: Traffic & Data Specifications for 2x2 Routing

Parameter Symbol Min. Typ. Max. Unit

Data Wavelength λ1 TBD nm














Header Wavelength λH1 TBD nm

Header Wavelength λH2 TBD nm

Data channel spacing Δf 100 GHz

Data-Header channel spacing Δf 100 GHz

Traffic Stream spectral spacing (λH1-λ8) Δλ TBD nm

Data pulse format NRZ

Data line-rate B 40 Gb/s

Data packet size 5 kbyte

Data packet duration Tp 1 μsec

Guardband duration TG 0.25 μsec

Header-Data Offset time TBD

Header Line-rate 2 MHz

Header Size 2 bits

Header Pulse format NRZ

Header Pulse Duration 0.5 μsec



Similar parameter specifications will be used for the network traffic employed in the 4x4 routing scenario. The main differences compared to the 2x2 routing scenario will be:

- A total set of 4 incoming traffic streams will be used, suggesting that four sets of 7-wavelength packet traffic will be employed. This means that besides λ1-λ7 and λ8-λ15 already used in the case of 2x2 routing, two new wavelength groups of λ16-λ23 and λ24-λ31 will be incorporated. In addition, two new header wavelengths λΗ3 and λΗ4 will be used for designating the address information for traffic streams #3 and #4, respectively.

- The Header information will employ three consecutive bits, given that in the case of 4x4 routing a total number of 4 possible input-output combinations can be selected.

The new Header format and its parameters for the case of 4x4 routing are summarized below:

Figure 4-2: The main differences in PLATON’s Traffic Format for the 4x4 routing scenario: a) spectral arrangement of the four incoming multi-wavelength Traffic Streams, and b) the new Header information of every multi-wavelength packet.

Table 3: Header Content for 4x4 routing

Header Bit#1 Bit#2 Bit#3 Header Content Interpretation 0 0 0 No packet present 0 0 1 Exits through Router Out#1 0 1 0 Exits through Router Out#2 0 1 1 Exits through Router Out#3

H (irrespective

of traffic stream

number) 1 0 0 Exits through Router Out#4



Table 4: Header Specifications for 4x4 Routing


Header Line-rate 3 MHz

Header Size 3 bits

Header Duration 1 μsec

Header Pulse format NRZ

Header Pulse Duration 0.333 μsec



5 Specifications for SOI platform, waveguides and interfaces

5.1 SOI platform

PLATON’s 2x2 and 4x4 router platforms will be realized on a Silicon-on-Insulator (SOI) motherboard chip that will contain silicon nanophotonic elements (waveguides, couplers, multiplexing circuitry and photodetectors) and will be at the same time capable of hosting the plasmonic switching elements and the IC control circuitry. The SOI motherboard will involve:

a. Optical 7X1 MUX circuitry capable of multiplexing up to 7 optical data wavelengths with 100GHz channel spacing into a single waveguide.

b. Monolithically integrated Photodiodes that will be used for the optoelectronic conversion of the packet-rate header pulses in order to drive the IC micro-controller circuit with the electrical header information.

c. A gold lift-off chip area to enable subsequent DLSPP waveguide writing processes, so as to allow for the incorporation of the DLSPP-based switching matrix.

d. A chip-area for hosting the hybridly integrated IC microcontroller circuit.

e. Metal interconnects for guiding the electrical-RF signals inserted into or generated by the IC circuit and for thermal tuning of the SOI MUX circuitry.

5.2 Silicon waveguides

Figure 5-1: Cross-section of the Si-waveguide structure

Table 5: Silicon waveguide specifications


SiO2 Box Height HSiO2 2 2 3 μm Si waveguide width W 400 nm Si waveguide height H 340 nm TE Propagation losses@1550nm αTE 4 dB/cm TM Propagation losses@1550nm αTM 4 dB/cm

TE and TM Propagation@1550nm singlemode



5.3 DLSPP waveguides

These will be the DLSPP waveguides that will be employed in the final thermo-optic DLSPP switching elements.

Figure 5-2: Cross-section of the DLSPP-waveguide structure

Table 6: DLSPP waveguide specifications


Polymer Height H 600 nm Polymer width W 500 nm Polymer type Ormocer Polymer refractive index 1.45 1.52 1.58 Polymer thermo-optic coefficient TOC -2.5x10-4 Gold film height HAu 60 nm Gold film width WAu 3 μm Propagation losses@1550nm α 0.1 dB/ μm Propagation Length (1/e damping)

Lsp 44 46 51 μm

Mode effective index Neff 1.2 1.25 1.28

5.4 Fiber-to-Silicon coupling interfaces

PLATON’s final 2x2 and 4x4 routing platforms will employ high-index contrast gratings-based vertical coupling structures for low coupling loss and for large alignment tolerances.

Table 7: Grating-based Vertical fiber-to-Si coupling structure specifications


grating periods 25

grating width 11 µm



filling factor 0.5

pitch 250 µm optical 1dB-bandwidth BW 40 nm Incidence angle 8 deg Insertion losses αL 5 6 8 dB 1dB loss alignment tolerance ±2 µm No# of fibers in a single array 8 32 48

5.5 Silicon-to-DLSPP coupling interfaces

Calculations were performed by utilizing the 3D vectorial finite element method for separate DLSPP-to-SiWire and SiWire-to-DLSPP transitions. Transmission results for the two cases were found to be almost identical, as reciprocity dictates.

The DLSPP-to-SiWire transition geometry is depicted in Figure 5-3 below. A Silicon tapering section is used for optimizing the Si waveguide dimensions directly at the Si-to-DLSPP interface. The metal gap between the gold film and the SiWire has been enforced by the 500nm resolution limit of available fabrication processes.

Figure 5-3: a) Top and b) Side view of the DLSPP-to-Si interface

Table 8: DLSPP-to-Si and Si-to-DLSPP interface specifications


Si-taper initial width W1 400 nm

Si-taper end width W2 175 200 nm Si-taper length Lt 500 µm Metal gap LG 0.5 µm Vertical Offset Hoffset 150 200 nm Losses α 3 dB



6 PLATON component specifications

6.1 Silicon-on-Insulator Multiplexing (MUX) circuit

MUX circuitry will rely on an interconnected arrangement of 7 microring-based SOI structures. Seven respective heating structures relying on electrical current driving circuitry will be employed for enabling fine-tuning of the MUX resonating frequencies so as to optimally align them to the incoming data wavelengths.

Figure 6-1: a) Cross-sectional and b) Top view of the integrated micro-heaters

An overview of the targeted specifications is provided below:

Table 9: 7x1 SOI MUX specifications


No# of Input ports 7

No# of Output ports 1 SiWire Width W 400 nm SiWire Height H 340 nm

Si waveguide Top-Cladding SOG

Accuglass T512B

Material for electrical contacts Titanium Thickness of electrical contacts WTi 100 nm Operating Wavelength Range 1500 1600 nm Center Wavelength TBD nm Channel spacing Δf 100 GHz Channel 3-dB bandwidth Δλ 0.32 nm Footprint / Chip size (w)x(L) (without the electrical contacts)

20x250 μm2

Footprint / Chip size (w)x(L) (including electrical contacts)

40x250 μm2

Power loss per channel α 0.5 1 dB Channel Crosstalk -25 -20 -18 dB Power consumption per temperature deviation

1 mW/K



Maximum Heating power per heating element

10 100 mW

The optical characteristics of the ring resonators and the switching matrix will be controlled by the control IC circuit using heating resistors. The heating resistors will be realized by applying thin resistive layers to the devices that can be heated using an electrical current. The Heating resistors will optionally be driven by buffer amplifiers. In order to change the temperature the control IC generates a square-wave signal. The temperature can be controlled by changing the duty-cycle as well as the frequency.

6.2 Header detection / photodiode

Two alternative photodiode solutions will be investigated:

Monolithically integrated Ge photodiodes using two different integration techniques, namely butt coupling and evanescent coupling. These configurations are expected to provide outstanding performance values well beyond the requirements of PLATON’s routing platforms, coming, however, at the expense of increased fabrication complexity.

Si+-implanted photodetectors, that seem to be the most appropriate compromise for matching the requirements of PLATON whilst keeping the overall integration complexity relatively low. In that type of photodetectors, generation of charge carriers relies on linear absorption at incorporated defect states which constitute inter-band energy levels caused by silicon ion implantation.

Figure 6-2: a) Cross-sectional and b) Top view of the Si+-implanted photodetectors

The targeted specifications for the photodetector option used in the final 2x2 and 4x4 router platforms are summarized in the following table:

Table 10: Header O/E Conversion: Photodiode specifications


Footprint 0.1 mm²

Photodiode Reverse Voltage VPD 3 V Maximum average optical input power (NRZ signal)

Popt TBD

Maximum output peak voltage VPEAK TBD Operating Wavelength Range λ 1500 1600 nm



DC Responsivity @1550nm R 0.2 A/W Polarization Dependent Loss PDL TBD 3-dB cut-off frequency f3dB 1 GHz Photodiode Dark Current Idark 100 nA

6.3 IC electronic control circuitry The digital control IC will be responsible for processing the header information and for controlling the output DLSPP switches according to a pre-defined routing look-up table. The routing look-up tables for both the 2x2 and the 4x4 PLATON routers are presented in Appendix I.

The block diagram of the digital control IC for the case of the 2x2 routing platform is illustrated in Figure 5-4. A similar design will be used also for the 4x4 PLATON router employing however a total number of 4 input and 8 output ports. The control IC will be a synchronous design. The clock signal will be generated by an internal oscillator.

Figure 6-3: Block diagram of the control IC

A summary of the IC microcontroller specifications is provided below:

Table 11: Specifications of digital control IC

Parameter Description/Value

Technology Austriamicrosystems C35B4C3 Clock Speed up to 20 MHz

3.3V (supply voltage - VDD) digital CMOS signals 0.7 VDD input high level 0.7 VDD input low level

2 inputs/2 outputs for 2x2 router 4 inputs/8 outputs for 4x4 router

Bidirectional CMOS buffers up to 24mA Bidirectional Schmit-Trigger buffers up to 24mA

Input/Output - Options

Bidirectional TTL buffers up to 24mA



Tri-State output buffers up to 24mA Footprint/Dimensions 4x4 mm2 Latency TBD Assembly Wire bonding / Flip-chip

It has to be evaluated, whether the DLSPP switching elements will be able to be controlled directly by the digital CMOS output signals that offer a driving strength up to 24mA. In case this does not prove sufficient for the purposes of thermo-optic switching by means of the DLSPP switch modules, a separate external driving stage will be implemented.

6.4 Metal Interconnects

The metal interconnects will provide signal and power distribution between the components. Their design will rely on impedance controlled layouts so as to maximize the power delivered to the modulators and control the timing of the header signaling for the IC Microcontroller. In order to reduce the number of required metallization levels single metallization layer configurations will be employed. Initial designs for different TML configurations (Coplanar Waveguide, Coplanar Strips) and substrate build-ups (metal layer on BOX, metal layer on redistribution layer RDL) have been done based on numerical simulations. The electrical characteristics are compiled in Table 12. The designs take into account the different geometrical features of the processes.

Table 12: Specifications for PLATON’s electrical interconnects

Parameter Symbol TML on BOX TML on RDL Unit

CPW width of center conductor Wcpw 15 100 um

CPW gap signal to ground Gcpw 1 5 um CPS width of signal conductors Wcps 15 45 um CPS gap between signal lines Gcps 5 10 um

The metal interconnects will be deployed using:

• Alu metallization with thickness ranging between 300-1000 nm (~ 3x10-6 Ohmcm)

• top-cladding with thickness between 100-1500 nm

• Via etching down to the silicon layer

• Via etching down to the heater layer

For chip scale fabrication, photolithography with ~5 µm alignment accuracy and ~ 5 µm minimum feature size will be used.



6.5 2x2 Dielectric Loaded – Surface Plasmon Polariton (DLSPP) switching element

Preliminary simulation-based results have identified two alternative DLSPP switch architectures as the most promising designs for the 2x2 switching matrix: the Mach-Zehnder Interferometric (MZI) layout and the Waveguide Ring Resonator (WRR) setup. The specifications for both of them operating as a 2x2 switching matrix are summarized in Table 13:

Table 13: 2x2 DLSPP Switching Matrix Specifications

Parameter Symbol MZI WRR Unit

No. of ports (input x output) 4 (2/2) 4 (2/2)

No. of switching elements 1 1

Waveguide Type DLSPP-W DLSPP-W Operating Wavelength Region λ 1500-1600 1500-1600 nm Free Spectral Range FSR >100 50 nm Channel Bandwidth Δλ3dB >60 >4 nm Crossection (waveguide mode) dimensions

0.5x0.6 0.5x0.6 μm2

Footprint / Chip size (w)x(L) 15x40 15x15 μm2 Total power consumption Pelec 8 8 mW Optical Power Losses (input/output)

α 5 <8 dB

Latency tlatency 220 <100 fsec switching time Δtspeed 1 1 μsec Optical Crosstalk ER <-20 -10 dB

6.6 4x4 Dielectric Loaded – Surface Plasmon Polariton (DLSPP) switching matrix

The two alternative MZI and WRR-based 2x2 switches are considered also for adoption in the 4x4 switching matrix, yielding two different 4x4 matrix architectural designs. The targeted specifications are summarized in the following table:

Table 14: 4x4 DLSPP Switching Matrix Specifications

Parameter Symbol MZI-based 4x4 matrix

WRR-based 4x4 matrix

Unit

No. of ports (input x output) 8 (4/4) 8 (4/4)

No. of switching elements 4 4

Waveguide Type DLSPP-W DLSPP-W Optical Bandwidth Δλ >100 >100 nm



Operating Wavelength Region λ 1500-1600 1500-1600 Free Spectral Range FSR >100 50 nm Channel Bandwidth Δλ3dB >60 >4 nm Crossection (waveguide mode) dimensions

0.5x0.6 0.5x0.6 μm2

Footprint / Chip size (w)x(L) 60x150 50x50 μm2 Total power consumption Pelec <35 <35 mW Optical Power Losses (input/output)

α 10 <15 dB

Latency tlatency <0.75 <0.3 psec switching time Δtspeed 1 1 μsec Optical Crosstalk ER <-20 -10 dB

6.7 Integration Concept

The process flow for enabling heterointegration of silicon photonics, plasmonics and electronics onto the same board has been identified and is described below:

Table 15: PLATON Integration Concept

SOI fabrication

1. Waveguide patterning: a. Electron Beam Lithography with HSQ mask

b. HBr Etching

c. HF mask strip

2. Cavity etch d. Photolithography

e. Self aligned etching of the 200 nm recess into the BOX

3. Top-cladding: (if required, alternative solutions available):

a. PMMA: thermal stability ~ 100 °C, Thickness ~ 200..1000 nm

b. SOG (Spin-On-Glass): ACCUGLASS® T-512B (thermally stable

up to ~ 400°C), Thickness ~300..1500 nm. SOG is good for gap

fill of the grating couplers.

c. CVD SiO2: thermal stability similar to thermal oxide, Thickness

100..2000 nm. Fair gap fill

d. Combinations of the above (currently under development)

4. Metallization:

(if required)

a. 100 nm up to 1000 nm thick Aluminum (thermally stable up to

~ 400°C)

DLSPPW fabrication



5. Cleaning: a. Acetone – IPA

b. PLOX (Harrick PDC 30W 500mtorr 2 min)

6. Defining lift-off mask: a. Spin coating AZ nLOF

b. Soft bake 110°C Hotplate

c. UV exposure : Süss Microtech MJB4 – i-line configuration

d. Post exposure bake 110°C Hotplate

e. Development AZ826MIF and DI water rinse

f. UV flood exposure

g. Hard bake 110°C Hotplate

7. Metallization: a. 5nm Chromium (adhesion layer) evaporation (electron gun)

b. 50nm Gold evaporation (thermal)

8. Lift-Off: a. 50°C NMP Remover and IPA rinse

9. Patterning DL-SPP

waveguide:

a. Spin coating PMMA

b. Soft bake 170°C Hotplate

c. Deep-UV exposure : Süss MJB4 – UV250 configuration – Vacuum contact – Quartz Mask

d. Development MIBK and IPA rinse

Heterointegration

10. Plating base: a. Sputter etch Ar b. Ti W Au (sputtered)

11. Litho: a. Resist spin on b. Alignment (quartz mask) c. Exposure d. Development e. Bake

12. Electro-plating (Au) 13. Resist spinning 14. Etch plating base 15. Wire bonding / Flip-chip



7 Specifications for 2x2 PLATON routing platform

7.1 Simulations

The routing performance of the 2x2 PLATON router has been simulated by means of the commercially available VPI Transmission- and Component Maker tool employing a MZI-based DLSPP switch layout. The router setup that has been used for the simulations is illustrated in Fig. 7-1 and all the parameters that have been used for the SOI MUX and the 2x2 MZI switch were identical to the specifications summarized so far in the respective sections of the present Deliverable.

Figure 7-1: VPI Setup of 2x2 PLATON routing platform

The router setup employs two Data Inputs (Input 1 and 2), with every Input comprising an array of 7 DFB laser diodes each one modulated by a NRZ 40Gb/s 27-1 PRBS data signal and emitting 10dBm of optical power. The 7 generated data wavelengths are then multiplexed into a 7:1 SOI MUX device providing the single-Input multiwavelength Traffic Stream that will enter the 2x2 switch. The exact values of the 14 data wavelengths that have been used in the current simulation were ranging between 192.5 THz for λ1 up to 193.8THz for λ14, with all wavelength channels having a 100GHz spectral spacing.

The two multiplexed 7-channel Input Traffic Streams were then launched into respective inputs of the 2x2 MZI switch. The arm lengths of the MZI were intentionally selected to have a small length variation of 2μm so as to take into account possible imperfections arising during fabrication, yielding arm lengths of 40μm and 42μm, respectively. The upper MZI arm was driven by a dc electrical voltage so as to ensure optimal phase biasing conditions, whereas the lower MZI arm was driven by an electrical voltage signal representing the Control signal that has to be generated by the IC microcontroller based



on the content of the two Header wavelength channels. The phase shifts were induced by means of an ideal phase modulator driven by respective electrical signals and the amplitude of the electrical signals was selected so that the induced phase shift equals the expected value of the thermooptically induced phase variation, taking into account the specifications of the Ormocer-loaded SPP MZI arms. The 2x2 MZI switch configuration was completed by an optical coupler where the signals were forced to interfere, resulting to the respective Output 1 and Output 2 ports. Rectangular shape demultiplexing stages with 100GHz channel spacing were used at each Output port in order to monitor the performance of each separate wavelength channel at the router’s output.

Fig. 7-2a) and b) depict the pulse trace and the eye diagram of λ1 40Gb/s NRZ channel before inserted into the 7:1 SOI MUX circuit. As can be seen, λ1 is assumed to carry three distinct packets, each of them having a duration of 1μsec. Guardbands of 0.1μsec were used at the front and at the end of each packet. Fig. 7-2c) shows the optical spectrum of all 14 wavelength data packets before entering the SOI MUX stage.

Fig. 7-2d) illustrates the pulse trace and the eye diagram of λ1 right after exiting the 7:1 SOI MUX circuit. As can be clearly revealed by the eye diagram schematic, the almost ideal rectangular NRZ pulse is transformed into a Gaussian-like pulse as a result of the limited 3-dB SOI MUX bandwidth. Similar eye diagrams were obtained for every individual data channel. Fig. 7-2f) shows the multiplexed λ1-λ7 optical spectra as well as the multiplexed optical spectra of λ8-λ14.

Figure 7-2: a) Pulse trace of channel#1 packets before the SOI MUX stage, b) eye diagram of channel#1 traffic before the SOI MUX, c) superposition of optical spectra of all the 14 data channels before the SOI MUX, d) Pulse trace of channel#1 packets at the SOI MUX output, e) eye diagram of channel#1 traffic at the SOI MUX output, f) superposition of optical spectra of all the 14 data channels at the SOI MUX output. Time scale in a), d) 2μsec/div and in b), e) 10psec/div. Frequency scale in c), f) 0.5THz/div.

Figure 7-3 shows the principle of operation for the complete 2x2 router platform as well as the signals at the input and output of the 2x2 MZI switch. Fig. 7-3a) and b) depict the header λH1 channel information and the Input 1 multiwavelength traffic stream, whereas



Fig. 7-3c) and d) show the respective data and λH2 header content for Input 2 multiwavelength traffic stream. It should be noted that the two header channels were assumed to be available directly in the electrical domain without considering optical header information with subsequent opto-electronic conversion in the respective photodiode circuitry. As such, the two header contents are supposed to directly enter the IC microcontroller circuit in order to generate the appropriate electrical control signal for driving the MZI switch based on the proper routing look-up table information. Fig. 7-3e) represents the obtained control signal that is used for driving the MZI switch.

Figure 7-3: Pulse trace and eye diagrams at different stages of the 2x2 routing platform. a) Header#1 trace at λH1, b) Data Traffic Stream at λ1-λ7 used as respective Input#1, c) Data Traffic Stream at λ8-λ14 used as Input#2, d) respective Header#2 trace at λH2, e) Control signal generated by the IC circuit, f) Multi-wavelength traffic at output#1 of the 2x2 switch, g) eye diagram of single-wavelength packet traffic at output#1, h) Multi-wavelength traffic at output#2 of the 2x2 switch, g) eye diagram of single-wavelength packet traffic at output#2. Time scale in a)-e), f), h) 2μsec/div and in g), i) 10psec/div.

Fig. 7-3f) shows the multiwavelength packet stream obtained at MZI Output 1. As can be seen, 3 data packets of Input 1 appear time-multiplexed with three respective data packets of Input 2, yielding a multiwavelength signal that includes all 14 wavelengths. Fig. 7-3g) shows the eye diagram of the demultiplexed λ1, revealing that low crosstalk is obtained and that the overall signal quality has been only marginally affected by the



switch performance. The same is valid also for MZI Output 2 as can be verified by Fig. 7-3h) and i), which show the 14-wavelength pulse trace and the λ1-eye diagram, respectively. It should be noted that the eye diagrams of all 14 data channels were similar to the λ1 eye at both MZI Output ports.

Fig. 7-4 summarizes the quantified information obtained by these simulation results providing the total power loss and extinction ratio values for each channel. Fig. 7-4a) shows the power values for the logical ‘1’ and logical ‘0’ pulse levels in every channel at MZI Output 1, whereas the respective graphs for Output 2 are shown in Fig. 7-4b). As can be easily verified, extinction ratio (ER) values between 34dB and 40dB are obtained for each channel, with the ER variation owing to the wavelength dependence of the sinusoidal MZI transfer function. The optical power losses for the entire 2x2 router were found to be 11dB.

Figure 7-4: Power level of ‘1’ (high) and ‘0’ (low) in the data sequence of each demultiplexed channel at the 2x2 switch a) output#1 and b) output#2. The line formed by * denotes the 10dBm input power of each channel.

7.2 2x2 routing platform specifications

Based on the simulation results presented in Section 7.1 and on the PLATON subsystem specifications summarized so far, the targeted specification for the 2x2 PLATON router are provided in the table below:

Table 16: PLATON 2x2 Router Specifications

Parameter Symbol MZI-based 2x2 router

WRR-based 2x2 router

Unit

Chip throughput 560 560 Gb/s

No. of input/output ports 16/2 16/2

Line rate / input port 40 40 Gb/s

Line rate / output port 280 280 Gb/s



Operating Wavelength Range λ 1500-1600 1500-1600 nm

Total power consumption Pelec <2.5 <2.5 W

Chip size (w)x(L) up to full 6”

wafer up to full 6”

wafer

losses (non-pigtailed chip) αchip 11 <16 dB

losses (fiber-pigtailed chip) α <20 <25 dB

Latency (port-to-port) tlatency <1 <1 psec

Extinction Ratio ER >20 >9 dB

packet size @line rate 5 5 kbytes



8 Specifications for 4x4 PLATON routing platform

8.1 Simulations

The 4x4 PLATON router performance has been again evaluated by means of simulations utilizing the commercially available VPI Transmission- and Component Maker tool and exploiting a MZI-based DLSPP switch layout. The router setup used is illustrated in Fig. 8-1. All individual compoment parameters used in the SOI MUX and the 2x2 MZI switching elements were again identical to the specifications summarized so far in the previous sections of the present Deliverable.

The routing platform employs four Data Input ports (Input#1, #2, #3 and #4) and four Output ports (Output#1, #2, #3 and #4). A 7-wavelength traffic stream is inserted into every Input port generated by an array of 7 respective DFB laser diodes, each one modulated by a NRZ 40Gb/s 27-1 PRBS data signal and emitting 10dBm of optical power. These 7 data wavelengths are then multiplexed into a 7:1 SOI MUX device providing the single-Input multiwavelength Traffic Stream that will enter the 4x4 switching matrix. The exact values of the 7ch x 4input = 28 data wavelengths that have been used are spanning from 191.8 THz for λ1 (channel1) up to 194.5THz for λ28 (channel28), with an equal adjacent channel spectral spacing of 100GHz.

Figure 8-1: VPI Setup of 4x4 PLATON routing platform



Figure 8-2: Pulse trace (a, b, c, d) and optical spectra (e, f, g, h) of the four 7-wavelength input traffic streams

(In#1, In#2, In#3, In#4) before the SOI MUX stage. Time scale in a), b), c) and d): 2μsec/div. Frequency

scale and center frequency in e), f), g) and h):1THz/div and 192.8THz, 192.1THz, 193.5THz and 194.2THz,

respectively.

The four multiplexed 7-channel Input Traffic Streams were then launched into the respective inputs of the 4x4 MZI-based switching matrix. The 4x4 switching matrix is formed by four individual 2x2 DLSPP MZI switches being identical to the elements used in Section 7 for the simulation-based performance evaluation of the 2x2 PLATON router. Finally, rectangular shape demultiplexing stages with 100GHz channel spacing were used again at each one of the four router Output ports in order to monitor the performance of each separate wavelength channel at the router’s output.

Fig. 8-2a), b), c) and d) depict the pulse trace of the four 7-wavelength traffic streams entering the switching matrix through Input#1, #2, #3 and #4, respectively. All the pulse and packet format parameters are the same as in the case of the 2x2x PLATON router performance evaluation procedure presented in Section 7. Fig. 8-2e) to h) show the respective multiplexed optical spectra for every separate router input port.

Figures 8-3a) and b) show the pulse trace and the optical spectrum, respectively, of the signal exiting the router through Output#1, whereas Fig. 8-3c) depicts the eye diagram of output channel1 at λ1 after being demultiplexed. As can be easily identified by Fig. 8-3b), this signal comprises all 28 wavelengths since it has been produced by packets

Figure 8-3: Router output signal emerging at Output#1. a) Pulse trace, b)optical spectrum, and c) eye diagram

of channel 1. Time scale in a) and c) is 2μsec/div and 25psec/div, respectively. Frequency scale and center

frequency in b): 1THz/div and 193.15THz, respectively.



originating from all four router input ports and requiring the same output#1 port. Moreoevr, a clear eye diagram is obtained at the output revealing that the entire 4x4 router induces only a small amount of crosstalk levels yielding a high-quality signal at its output. Similar graphs have been obtained for all four different router output ports and for every separate of the 28 data channels.

Fig. 8-4a) and b) illustrate the power levels of the logical ‘1’s (signal pulses) and logical ‘0’s (crosstalk level) in every individual of the 28 channels appearing at outputs #1 and #2, respectively. The difference between each channel’s input power and its respective ‘1’-level output power yields the overall router’s optical power losses that are found to be 21dB. At the same time, the difference between the output power levels of ‘1’s and ‘0’s for every channel provides the channel’s extinction ratio obtained at the router output, revealing that ER values between 29dB and 40dB can be achieved depending on the specific data wavelength. This ER variation owes again to the wavelength dependence of the sinusoidal MZI transfer function and is now greater than in the case of the 2x2 router due to the employment of two cascaded MZI stages, suggesting that the total 4x4 switching matrix transfer function is given by the multiplication of the two individual 2x2 MZI switch transfer functions. Identical power loss and ER curves have been also ibtained for Output ports #3 and #4 of the 4x4 router.

Figure 8-4: Power level of ‘1’ (signal) and ‘0’ (crosstalk) in the data sequence of each demultiplexed channel at the 4x4 router a) output#1 and b) output#2. The line formed by * denotes the 10dBm input power of each channel. Similar curves have been also obtained for Output#3 and #4.

8.2 4x4 routing platform specifications

Based on the simulation results presented in Section 8.1 and on the PLATON subsystem specifications summarized so far in the sections before, the targeted specifications for the 4x4 PLATON router are provided in the table below:

Table 17: PLATON 4x4 Router Specifications

Parameter Symbol MZI-based 2x2 router

WRR-based 2x2 router

Unit

Chip throughput 1.12 1.12 Tb/s

No. of input/output ports 32/4 32/4



Line rate / input port 40 40 Gb/s

Line rate / output port 280 280 Gb/s

Operating Wavelength Range λ 1500-1600 1500-1600 nm

Total power consumption Pelec <4 <4 W

Chip size (w)x(L) up to full 6”

wafer up to full 6”

wafer

losses (non-pigtailed chip) αchip <21 <26 dB

losses (fiber-pigtailed chip) α <30 <33 dB

Latency (port-to-port) tlatency <1.5 <1.5 psec

Extinction Ratio ER >17 >9 dB

packet size @line rate 5 5 kbytes



9 Conclusions This deliverable is the specification sheet of PLATON’s 2x2 and 4x4 routing platforms. The requirements from the system point of view have been outlined and translated into detailed electrical, optical and mechanical specifications. The specifications for all the passive and active electrical, photonic and plasmonic components as well as the process flow have been specified. A small number of specifications (e.g. exact wavelength channels) will be defined as soon as all the details of the whole router system are set in more detail.



10 Appendix I: Routing Look-up table

10.1 Routing Look-Up Table for 2x2 PLATON router

PLATON’s 2x2 switching matrix in its MZI-based implementation is depicted in the following Figure. The respective routing look-up table considering a single driving signal generated by the IC circuit is appended in the Table below. In case differential driving scheme will be adopted (still under consideration), two driving signals will be generated by the IC circuit having the same logical value but different driving voltages. It should be noted that when the two input signals require at the same time the same router output, priority is given to Input#1 so that Input#1 signal exits the router through the desired output whereas Input#2 signal emerges at the remaining router output port. In that case, the 2x2 switch state is dictated by the Input#1 Header information.

Figure 10-1: The MZI-based 2x2 PLATON router

ROUTING LOOK‐UP TABLE for the 2x2 PLATON ROUTER

H1 (In#1 Header) H2 (In#2 Header)

Switch State (BAR or CROSS)

Out#1 Out#2 IC output driving the switch

1st Bit 2nd Bit 1st Bit 2nd Bit 0 0 0 0 NONE NONE NONE OFF 0 0 0 1 BAR NONE In#2 ON 0 0 1 0 CROSS In#2 NONE OFF 0 1 0 0 BAR In#1 NONE ON 0 1 0 1 BAR In#1 In#2 ON 0 1 1 0 BAR In#1 In#2 ON 1 0 0 0 CROSS NONE In#1 OFF 1 0 0 1 CROSS In#2 In#1 OFF 1 0 1 0 CROSS In#2 In#1 OFF



10.2 Routing Look-Up Table for 4x4 PLATON router

PLATON’s 4x4 switching matrix in its MZI-based implementation is depicted in the following Figure. The respective routing look-up table considering four driving signals generated by the IC circuit is appended in the Table below. In case differential driving scheme will be adopted for each switching element (still under consideration), two driving signals will be generated by the IC circuit for every individual switching structure having the same logical value but different driving voltages. This will lead to a total number of 8 driving signals. When two or more input signals require at the same time the same router output, priority is given serially to the router inputs according to their ranking. As such, Input#1 is always the highest priority input, being followed by Input#2, #3 and #4 with respect to priority ranking.

Figure 10-2: The MZI-based 2x2 PLATON router

ROUTING LOOK-UP TABLE for the 4x4 PLATON ROUTER

H1 (In#1 Header) H2 (In#2 Header) H3 (In#3 Header) H4 (In#4 Header) Out#1 Out#2 Out#3 Out#4 IC out#1

IC out#2

IC out#3

IC out#4

1st Bit

2nd Bit

3rd Bit

1st Bit

2nd Bit

3rd Bit

1st Bit

2nd Bit

3rd Bit

1st Bit

2nd Bit

3rd Bit

0 0 0 0 0 0 0 0 0 0 0 0 - - - - OFF OFF OFF OFF



0 0 0 0 0 0 0 0 0 0 0 1 In#4 - - - OFF OFF OFF OFF 0 0 0 0 0 0 0 0 0 0 1 0 - In#4 - - OFF OFF ON OFF 0 0 0 0 0 0 0 0 0 0 1 1 - - In#4 - OFF ON OFF OFF 0 0 0 0 0 0 0 0 0 1 0 0 - - - In#4 OFF ON OFF ON

0 0 0 0 0 0 0 0 1 0 0 0 In#3 - - - OFF ON OFF OFF 0 0 0 0 0 0 0 0 1 0 0 1 In#3 - In#4 - OFF ON OFF OFF 0 0 0 0 0 0 0 0 1 0 1 0 In#3 - In#4 - OFF ON OFF OFF 0 0 0 0 0 0 0 0 1 0 1 1 In#3 - In#4 - OFF ON OFF OFF 0 0 0 0 0 0 0 0 1 1 0 0 In#3 - - In#4 OFF ON OFF ON

0 0 0 0 0 0 0 1 0 0 0 0 - In#3 - - OFF ON ON OFF 0 0 0 0 0 0 0 1 0 0 0 1 - In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 0 0 1 0 0 1 0 - In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 0 0 1 0 0 1 1 - In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 0 0 1 0 1 0 0 - In#3 - In#4 OFF ON ON ON

0 0 0 0 0 0 0 1 1 0 0 0 - - In#3 - OFF OFF OFF OFF 0 0 0 0 0 0 0 1 1 0 0 1 In#4 - In#3 - OFF OFF OFF OFF 0 0 0 0 0 0 0 1 1 0 1 0 - In#4 In#3 - OFF OFF ON OFF 0 0 0 0 0 0 0 1 1 0 1 1 In#4 - In#3 - OFF OFF OFF OFF 0 0 0 0 0 0 0 1 1 1 0 0 In#4 - In#3 - OFF OFF OFF OFF

0 0 0 0 0 0 1 0 0 0 0 0 - - - In#3 OFF OFF OFF ON 0 0 0 0 0 0 1 0 0 0 0 1 In#4 - - In#3 OFF OFF OFF ON 0 0 0 0 0 0 1 0 0 0 1 0 - In#4 - In#3 OFF OFF ON ON 0 0 0 0 0 0 1 0 0 0 1 1 In#4 - - In#3 OFF OFF OFF ON 0 0 0 0 0 0 1 0 0 1 0 0 In#4 - - In#3 OFF OFF OFF ON

0 0 0 0 0 1 0 0 0 0 0 0 In#2 - - - OFF OFF ON OFF 0 0 0 0 0 1 0 0 0 0 0 1 In#2 In#4 - - OFF OFF ON OFF



0 0 0 0 0 1 0 0 0 0 1 0 In#2 In#4 - - OFF OFF ON OFF 0 0 0 0 0 1 0 0 0 0 1 1 In#2 - In#4 - OFF ON ON OFF 0 0 0 0 0 1 0 0 0 1 0 0 In#2 - - In#4 OFF ON ON ON

0 0 0 0 0 1 0 0 1 0 0 0 In#2 In#3 - - OFF ON ON OFF 0 0 0 0 0 1 0 0 1 0 0 1 In#2 In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 1 0 0 1 0 1 0 In#2 In#4 In#3 - OFF OFF ON OFF 0 0 0 0 0 1 0 0 1 0 1 1 In#2 In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 1 0 0 1 1 0 0 In#2 In#3 - In#4 OFF ON ON ON

0 0 0 0 0 1 0 1 0 0 0 0 In#2 In#3 - - OFF ON ON OFF 0 0 0 0 0 1 0 1 0 0 0 1 In#2 In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 1 0 1 0 0 1 0 In#2 In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 1 0 1 0 0 1 1 In#2 In#3 In#4 - OFF ON ON OFF 0 0 0 0 0 1 0 1 0 1 0 0 In#2 In#3 - In#4 OFF ON ON ON

0 0 0 0 0 1 0 1 1 0 0 0 In#2 - In#3 - OFF OFF ON OFF 0 0 0 0 0 1 0 1 1 0 0 1 In#2 In#4 In#3 - OFF OFF ON OFF 0 0 0 0 0 1 0 1 1 0 1 0 In#2 In#4 In#3 - OFF OFF ON OFF 0 0 0 0 0 1 0 1 1 0 1 1 In#2 In#4 In#3 - OFF OFF ON OFF 0 0 0 0 0 1 0 1 1 1 0 0 In#2 In#4 In#3 - OFF OFF ON OFF

0 0 0 0 0 1 1 0 0 0 0 0 In#2 - - In#3 OFF OFF ON ON 0 0 0 0 0 1 1 0 0 0 0 1 In#2 In#4 - In#3 OFF OFF ON ON 0 0 0 0 0 1 1 0 0 0 1 0 In#2 In#4 - In#3 OFF OFF ON ON 0 0 0 0 0 1 1 0 0 0 1 1 In#2 In#4 - In#3 OFF OFF ON ON 0 0 0 0 0 1 1 0 0 1 0 0 In#2 In#4 - In#3 OFF OFF ON ON

0 0 0 0 1 0 0 0 0 0 0 0 - In#2 - - OFF OFF OFF OFF 0 0 0 0 1 0 0 0 0 0 0 1 In#4 In#2 - - OFF OFF OFF OFF 0 0 0 0 1 0 0 0 0 0 1 0 In#4 In#2 - - OFF OFF OFF OFF



0 0 0 0 1 0 0 0 0 0 1 1 - In#2 In#4 - OFF ON OFF OFF 0 0 0 0 1 0 0 0 0 1 0 0 - In#2 - In#4 OFF ON OFF ON

0 0 0 0 1 0 0 0 1 0 0 0 In#3 In#2 - - OFF ON OFF OFF 0 0 0 0 1 0 0 0 1 0 0 1 In#3 In#2 In#4 - OFF ON OFF OFF 0 0 0 0 1 0 0 0 1 0 1 0 In#3 In#2 In#4 - OFF ON OFF OFF 0 0 0 0 1 0 0 0 1 0 1 1 In#3 In#2 In#4 - OFF ON OFF OFF 0 0 0 0 1 0 0 0 1 1 0 0 In#3 In#2 - In#4 OFF ON OFF ON

0 0 0 0 1 0 0 1 0 0 0 0 In#3 In#2 - - OFF ON OFF OFF 0 0 0 0 1 0 0 1 0 0 0 1 In#4 In#2 In#3 - OFF OFF OFF OFF 0 0 0 0 1 0 0 1 0 0 1 0 In#3 In#2 In#4 - OFF ON OFF OFF 0 0 0 0 1 0 0 1 0 0 1 1 In#3 In#2 In#4 - OFF ON OFF OFF 0 0 0 0 1 0 0 1 0 1 0 0 In#3 In#2 - In#4 OFF ON OFF ON

0 0 0 0 1 0 0 1 1 0 0 0 - In#2 In#3 - OFF OFF OFF OFF 0 0 0 0 1 0 0 1 1 0 0 1 In#4 In#2 In#3 - OFF OFF OFF OFF 0 0 0 0 1 0 0 1 1 0 1 0 In#4 In#2 In#3 - OFF OFF OFF OFF 0 0 0 0 1 0 0 1 1 0 1 1 In#4 In#2 In#3 - OFF OFF OFF OFF 0 0 0 0 1 0 0 1 1 1 0 0 In#4 In#2 In#3 - OFF OFF OFF OFF

0 0 0 0 1 0 1 0 0 0 0 0 - In#2 - In#3 OFF OFF OFF ON 0 0 0 0 1 0 1 0 0 0 0 1 In#4 In#2 - In#3 OFF OFF OFF ON 0 0 0 0 1 0 1 0 0 0 1 0 In#4 In#2 - In#3 OFF OFF OFF ON 0 0 0 0 1 0 1 0 0 0 1 1 In#4 In#2 - In#3 OFF OFF OFF ON 0 0 0 0 1 0 1 0 0 1 0 0 In#4 In#2 - In#3 OFF OFF OFF ON

0 0 0 0 1 1 0 0 0 0 0 0 - - In#2 - ON OFF OFF ON 0 0 0 0 1 1 0 0 0 0 0 1 In#4 - In#2 - ON OFF OFF ON 0 0 0 0 1 1 0 0 0 0 1 0 - In#4 In#2 - ON OFF ON ON 0 0 0 0 1 1 0 0 0 0 1 1 In#4 - In#2 - ON OFF OFF ON



0 0 0 0 1 1 0 0 0 1 0 0 - - In#2 In#4 ON ON OFF ON

0 0 0 0 1 1 0 0 1 0 0 0 In#3 - In#2 - ON ON OFF ON 0 0 0 0 1 1 0 0 1 0 0 1 In#3 - In#2 In#4 ON ON OFF ON 0 0 0 0 1 1 0 0 1 0 1 0 In#3 - In#2 In#4 ON ON OFF ON 0 0 0 0 1 1 0 0 1 0 1 1 In#3 - In#2 In#4 ON ON OFF ON 0 0 0 0 1 1 0 0 1 1 0 0 In#3 - In#2 In#4 ON ON OFF ON

0 0 0 0 1 1 0 1 0 0 0 0 - In#3 In#2 - ON ON ON ON 0 0 0 0 1 1 0 1 0 0 0 1 - In#3 In#2 In#4 ON ON ON ON 0 0 0 0 1 1 0 1 0 0 1 0 - In#3 In#2 In#4 ON ON ON ON 0 0 0 0 1 1 0 1 0 0 1 1 - In#3 In#2 In#4 ON ON ON ON 0 0 0 0 1 1 0 1 0 1 0 0 - In#3 In#2 In#4 ON ON ON ON

0 0 0 0 1 1 0 1 1 0 0 0 In#3 - In#2 - ON ON OFF ON 0 0 0 0 1 1 0 1 1 0 0 1 In#4 - In#2 In#3 ON OFF OFF ON 0 0 0 0 1 1 0 1 1 0 1 0 - In#4 In#2 In#3 ON OFF ON ON 0 0 0 0 1 1 0 1 1 0 1 1 In#3 - In#2 In#4 ON ON OFF ON 0 0 0 0 1 1 0 1 1 1 0 0 In#3 - In#2 In#4 ON ON OFF ON

0 0 0 0 1 1 1 0 0 0 0 0 - - In#2 In#3 ON OFF OFF ON 0 0 0 0 1 1 1 0 0 0 0 1 In#4 - In#2 In#3 ON OFF OFF ON 0 0 0 0 1 1 1 0 0 0 1 0 - In#4 In#2 In#3 ON OFF ON ON 0 0 0 0 1 1 1 0 0 0 1 1 In#4 - In#2 In#3 ON OFF OFF ON 0 0 0 0 1 1 1 0 0 1 0 0 In#4 - In#2 In#3 ON OFF OFF ON

0 0 0 1 0 0 0 0 0 0 0 0 - - - In#2 ON OFF OFF OFF 0 0 0 1 0 0 0 0 0 0 0 1 In#4 - - In#2 ON OFF OFF OFF 0 0 0 1 0 0 0 0 0 0 1 0 - In#4 - In#2 ON OFF ON OFF 0 0 0 1 0 0 0 0 0 0 1 1 - - In#4 In#2 ON ON OFF OFF 0 0 0 1 0 0 0 0 0 1 0 0 In#4 - - In#2 ON OFF OFF OFF



0 0 0 1 0 0 0 0 1 0 0 0 In#3 - - In#2 ON ON OFF OFF 0 0 0 1 0 0 0 0 1 0 0 1 In#3 - In#4 In#2 ON ON OFF OFF 0 0 0 1 0 0 0 0 1 0 1 0 In#3 - In#4 In#2 ON ON OFF OFF 0 0 0 1 0 0 0 0 1 0 1 1 In#3 - In#4 In#2 ON ON OFF OFF 0 0 0 1 0 0 0 0 1 1 0 0 In#3 - In#4 In#2 ON ON OFF OFF

0 0 0 1 0 0 0 1 0 0 0 0 - In#3 - In#2 ON ON ON OFF 0 0 0 1 0 0 0 1 0 0 0 1 - In#3 In#4 In#2 ON ON ON OFF 0 0 0 1 0 0 0 1 0 0 1 0 - In#3 In#4 In#2 ON ON ON OFF 0 0 0 1 0 0 0 1 0 0 1 1 - In#3 In#4 In#2 ON ON ON OFF 0 0 0 1 0 0 0 1 0 1 0 0 - In#3 In#4 In#2 ON ON ON OFF

0 0 0 1 0 0 0 1 1 0 0 0 - - In#3 In#2 ON OFF OFF OFF 0 0 0 1 0 0 0 1 1 0 0 1 In#4 - In#3 In#2 ON OFF OFF OFF 0 0 0 1 0 0 0 1 1 0 1 0 - In#4 In#3 In#2 ON OFF ON OFF 0 0 0 1 0 0 0 1 1 0 1 1 In#4 - In#3 In#2 ON OFF OFF OFF 0 0 0 1 0 0 0 1 1 1 0 0 In#4 - In#3 In#2 ON OFF OFF OFF

0 0 0 1 0 0 1 0 0 0 0 0 In#3 - - In#2 ON ON OFF OFF 0 0 0 1 0 0 1 0 0 0 0 1 In#4 - In#3 In#2 ON OFF OFF OFF 0 0 0 1 0 0 1 0 0 0 1 0 - In#4 In#3 In#2 ON OFF ON OFF 0 0 0 1 0 0 1 0 0 0 1 1 In#3 - In#4 In#2 ON ON OFF OFF 0 0 0 1 0 0 1 0 0 1 0 0 In#3 - In#4 In#2 ON ON OFF OFF

0 0 1 0 0 0 0 0 0 0 0 0 In#1 - - - ON OFF ON OFF 0 0 1 0 0 0 0 0 0 0 0 1 In#1 In#4 - - ON OFF ON OFF 0 0 1 0 0 0 0 0 0 0 1 0 In#1 In#4 - - ON OFF ON OFF 0 0 1 0 0 0 0 0 0 0 1 1 In#1 - In#4 - ON ON ON OFF 0 0 1 0 0 0 0 0 0 1 0 0 In#1 - - In#4 ON ON ON ON

0 0 1 0 0 0 0 0 1 0 0 0 In#1 In#3 - - ON ON ON OFF



0 0 1 0 0 0 0 0 1 0 0 1 In#1 In#3 In#4 - ON ON ON OFF 0 0 1 0 0 0 0 0 1 0 1 0 In#1 In#4 In#3 - ON OFF ON OFF 0 0 1 0 0 0 0 0 1 0 1 1 In#1 In#3 In#4 - ON ON ON OFF 0 0 1 0 0 0 0 0 1 1 0 0 In#1 In#3 - In#4 ON ON ON ON

0 0 1 0 0 0 0 1 0 0 0 0 In#1 In#3 - - ON ON ON OFF 0 0 1 0 0 0 0 1 0 0 0 1 In#1 In#3 In#4 - ON ON ON OFF 0 0 1 0 0 0 0 1 0 0 1 0 In#1 In#3 In#4 - ON ON ON OFF 0 0 1 0 0 0 0 1 0 0 1 1 In#1 In#3 In#4 - ON ON ON OFF 0 0 1 0 0 0 0 1 0 1 0 0 In#1 In#3 - In#4 ON ON ON ON

0 0 1 0 0 0 0 1 1 0 0 0 In#1 - In#3 - ON OFF ON OFF 0 0 1 0 0 0 0 1 1 0 0 1 In#1 In#4 In#3 - ON OFF ON OFF 0 0 1 0 0 0 0 1 1 0 1 0 In#1 In#4 In#3 - ON OFF ON OFF 0 0 1 0 0 0 0 1 1 0 1 1 In#1 In#4 In#3 - ON OFF ON OFF 0 0 1 0 0 0 0 1 1 1 0 0 In#1 In#4 In#3 - ON OFF ON OFF

0 0 1 0 0 0 1 0 0 0 0 0 In#1 - - In#3 ON OFF ON ON 0 0 1 0 0 0 1 0 0 0 0 1 In#1 In#4 - In#3 ON OFF ON ON 0 0 1 0 0 0 1 0 0 0 1 0 In#1 In#4 - In#3 ON OFF ON ON 0 0 1 0 0 0 1 0 0 0 1 1 In#1 In#4 - In#3 ON OFF ON ON 0 0 1 0 0 0 1 0 0 1 0 0 In#1 In#4 - In#3 ON OFF ON ON

0 0 1 0 0 1 0 0 0 0 0 0 In#1 - In#2 - ON OFF ON ON 0 0 1 0 0 1 0 0 0 0 0 1 In#1 In#4 In#2 - ON OFF ON ON 0 0 1 0 0 1 0 0 0 0 1 0 In#1 In#4 In#2 - ON OFF ON ON 0 0 1 0 0 1 0 0 0 0 1 1 In#1 - In#4 In#2 ON ON ON OFF 0 0 1 0 0 1 0 0 0 1 0 0 In#1 - In#2 In#4 ON ON ON ON

0 0 1 0 0 1 0 0 1 0 0 0 In#1 In#3 In#2 - ON ON ON ON 0 0 1 0 0 1 0 0 1 0 0 1 In#1 In#3 In#2 In#4 ON ON ON ON



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d2.1: specifications of platon’s 2x2 and 4x4 routing platforms · 2017-04-20 · d2.1...

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