d-type latch ii

8/3/2019 D-Type Latch II

1/19

1

D-Type Latch II

Clock Division Circuits

The hardware of our computer runs at different speeds. The different busses and componen

actually specify what maximum speed clock they can use for their edge triggered operation

The fastest signal is the clock signal of the processor. This signal is shared between otherhardware components that run slower than the processor. In order for those to share this sig

nal, the signal frequency must be divided by certain circuitry.

The Data Flip-flop can be used to do such division using a circuit shown below.

2

This circuit is simply a Data Flip-Flop but with its Q signal connected to its Data (D) input

We will do a few examples to show how this new circuit works.

TUTORIAL OBJECTIVES

Use a data flip-flop to create clock division circuitsCreate 4-bit binary counters using data flip-flops.

D Q

QCLK

Move onto Frame 2 and follow the frames on Example 1

EXAMPLE 1

A D-Type Flip-Flop is shown with its initial logical

state. For the following clock signal (CLK), complete

the timing diagram forQ andD.

D Q

QCLK

01


2/19

CLK

D

Q

3

Now, we know that when we reach the next rising clock signal, the value ofD is copied

across to Q. So at the first dotted line, we can draw in the new value ofQ. Hence we get a

new diagram of ...

CLK

D

Q

Because ...

at the dotten line, the clock rising from 0 to 1 triggers the flip flop to copy the value of Dat

D, equal to 1 across to Output Q. So Q is now equal to 1.

So now that Q is equal to 1, look back at our diagram:

D Q

QCLK

1

We can see that Q must now be 0 and because it is being fed around toD we can say thatD

is now 0. This all happens in one go when the clock rising from 0 to 1. On our timing dia-

gram we can now show the new value ofD which would give a diagram of ...


3/19

4CLK

D

Q

Now we can extend the values ofD and Q up until the next edge triggers an operation.

This would give us a new diagram of ...

Now we are at the next clock edge. Here, using the same reasoning as before: flip-flops cop

the value ofD across to Q on clock edges, so find the new values of bothD and Q ...

CLK

D

Q

D Q

QCLK

01

So after first edge-triggered operation, our data flip flop has the new state of.

5


4/19

6CLK

D

Q

D Q

QCLK

01

Because before the edge-triggered operation we had the state:

On execution of at edge,D is copied to Q so we now have:

D Q

QCLK

1

CLK

D

Q

Giving on the timing diagram:

Now that Q is 0, Q must now be 1 and because it is being fed around toD we can say thatD

is now 1. Hence we get the timing diagram shown below.


5/19

CLK

D

Q

Again, we can extend the values ofD and Q up until the next edge triggers an operation.

This would give us a new diagram of ...

7CLK

D

Q

Now on this edge, complete the diagram to show the new values ofQ andD. Remember th

the circuit now looks like:

D Q

QCLK

01

8CLK

D

Q


6/19

This is because ...

at the rising edge,D is copied to Q so we now have:

D Q

QCLK

1

Giving on the timing diagram:

CLK

D

Q

Now that Q is 1, Qbecomes 0 as they are always opposite. SoD is also now 0. So we get a

new advance on the timing diagram:

CLK

D

Q

We can extend the values of D and Q until the next clock rise but we will stop there. If we

wanted to, we could continue performing the edge-triggered operations but we will stop.

CLK

D

Q

Now compare this signal...

with this signal...


7/19

9

CLK

Q

CLKtime period

Q signal time period

D Q

QCLK

If we compare the time peroid of these peroid signals, we can see that the time peroid ofQ

twice as long as the time peroid ofCLK.

10

Write this in your notes then move onto frame 10

Now we can go back to talking about the components of a computer.

D Q

QCLKOscillating

Crystal Component

Requiring 0.5Mhz

1.0 MHz0.5 MHz

Here we imagine a system with a processor with a clock rate of 1.0 MHz. By using a our c

cuit we can divide this high frequency by two (equivalent to doubling the time peroid) and

output this signal to other parts of the computer hardware that can operate at this clock.

Of course, a real computer system would be far more complex and you certainly would no

find a single flip-flop like this seperating components. To put things in perspective, you m

remember that the Intel Pentium IV processor has around X transistors in its small centralprocessing microchip. Other computer components would also have thousands of transisto

Going back to our imaginary system however, what is the easiest way to obtain a clock sig

nal of 0.25MHz? Remember that we already had signal of 1.0MHz and got a signal of

0.5MHz.

Central Processing

Components

Think about it then move onto Frame 11 to compare answer


8/19

11 Use another D-type flip-flop to divide the 0.5MHz clock by two

You probably noticed the simple solution of dividing the 0.5MHz clock signal; giving a sig

nal of twice the time period, with a frequency of 0.25MHz. Such a circuit looks like this:

D1 Q1

Q1

CLK1 Q1

D2 Q2

Q2

Q2

Here we are using two Data Flip-flops. This circuit has one input (CLK) and has two outpu

(Q1 and Q2). Notice that Q1 will be the input clock signal with its frequency divided by tw

and Q2 will be the input clock signal with its frequency divided by four. So for example:

CLK2

Lets do an example to see how this circuit works.

D1 Q1

Q1

CLK1 Q1

D2 Q2

Q2

Q2

CLK21.0 MHz

0.5 MHz 0.25 MHz

12

Move onto frame 2 and follo the frames on Example 1

EXAMPLE 2

The Data Flip-Flops shown below are connected together. For their initial logical state, com

plete the timing diagrams forQ andD.

D1, Q1, and Q1(a)

D2 and Q2(b)


9/19

D1 Q1

Q1 Q2

CLK Q1

D2 Q2

Q2

CLK1

0

1

1

0

1

CLK

D1

Q1

For part (a) we have the following timing diagrams to complete:

Q1

This time we are additionally going to complete the diagram forQ1 to make part (b) easier.

13

Now extend these diagrams until the first rising edge and perform the flip-flop operation;

giving the new values ofD1, Q

1and Q

1...

D1

Q1

Q1

This is because when we are coming up the rising edge the state of the flip-flop (the left-

most flip-flop) is such thatD1 is equal to 1 and Q1 is equal to 0.

On the clock edge, the flip-flop operates by setting Q1 equal toD1. So now Q1 is 1.


10/19

D1

Q1

This gives us the following:

Q1

But we now remember thatD1 is connected to Q1:

D1 Q1

Q1

CLK Q1

1 Q1 is now 1

Because Q1 is now 1, Q1 falls to 0 and becauseD1 is connected to Q1,D1 also falls to 0.

Hence we have the timing diagrams that look like:

D1

Q1

Q1

CLK

Now repeat the same process at the next clock signal to work out the new values ofD1, Q1and Q1. The diagram you should get should be ...

14

Complete the diagrams above up until the next clock edge and check with Frame 14


11/19

D1

Q1

Q1

Because when we arrive at the second rising edge the state of the flip-flop hasD1 is equal to

0 and Q1 is equal to 1. On the clock edge, the flip-flop transfersD1 equal to Q1. So now Q1 i

0. So this means that Q1 andD1 are now equal to 1.

Hopefully by now, you are getting the hang of this. At each clock edge, the same thing hap

pens so indeed, explaining each stage becomes trivial once youre used to whats going on

So I leave it to you to complete the rest of the diagrams forD1, Q1 and Q1.

15

Finish the three timing diagrams completely and check it agrees with Frame 15

D1 Q1

Q1

CLK Q1

0 Q1 is now 0

D1 Q1

Q1

CLK Q1

soD1 is now 1

so Q1 is now 1

CLK

So now we have:

D1

Q1

Q1

1

1

0


12/19

D1

Q1

Q1

CLK

Now that we have got a clock we will use Q1 as a clock input to our second flip-flop. This

where we start to answer part (b). So we will copy its signal below.

Q1

Now notice that we will add the upwards arrows to help remind us that those edges are use

for triggering operations on right-hand flip-flop.

If you correctly got the above, then move onto frame 16. Otherwise, stay here to find out

where you went wrong as the solution is explained.

16


13/19

Q1

Part (b) of the question asks us to find the timing diagrams forD2 and Q2. From the diagram

it gave, it showed us that initially,D2 is 1 and Q2 is 0.

D2

Q2

17

Now to finish Example 2, we just need to repeat the process for the second flip-flip. So com

plete the diagrams above.

Finish the two timing diagrams completely then move on to Frame 1

Q1

D2

Q2

If you managed to get the above, then move onto Frame 18. Otherwise, stay here to see wh

errors you have made.


14/19

18

19

REVISION QUESTIONS


15/19

Binary Counters

20

Another fundamental circuit is a binary counter. Remember that each flop can represent tw

states. So a flip-flop can represent the numbers 0 and 1. Similarly two flip-flops can hold

four states and three flip-flops can hold ... states.

eight21

And in general n flip-flops can store 2n states. So going back to our binary counter circuit. I

we want a circuit that can count from zero to seven slowly: 0 ... 01 ... 10 ... 11 ... 100 ... 10

... 110 ... 111 - then we would need need ... flip-flops because our system has ... states.

we would need need three flip-flops because our system has eight states22

If we wanted a system that counted from 0 to 127, then we would need seven flip-flops.

So then, how many data-type flip-flops do we need to count from

(a) 0 to 255 (b) 0 to 63 (c) 0 to 7 (d) 7 to 0 (e) 1 to 16 (f) 1 to 4 (g) 8 to 1

(a) 8 (b) 6 (c) 3 (d) 3 (e) 4 (f) 2 (g) 323

Notice that we want to instead, design a circuit that counts down rather than one that count

up. In either case, we will still need as many n flip-flops to store 2nbinary numbers existing

to stored in the circuit. Essentially, each flip-flop would represent a binary digit.

So what does this binary counter circuit look like? It may seem a bit familiar:

D1 Q1

Q1 Q2

CLK Q1

D2 Q2

Q2CLK

Q3

D3 Q3

Q3CLK

This is exactly the same circuit that would be used for dividing a clock frequency by three.

So how can this same circuit be used as a counter? Notice that there are three d-type flip-

flops. So this circuit is probably be used to count from zero to seven (or maybe from seven

to zero). To understand fully, we look in detail at the timing diagrams for this circuit.


16/19

24

Q1

Q2

Q3

tItHtGtFtEtDtCtBtA tJ

Here is the timing diagram forQ1, Q2 and Q3.

Consider the values of these three variables at the certain times highlighted on the diagram

The first of these times is at tA, where Q1 is 0, Q2 is 0 and Q3 is 0. The state of the system atthis time is:

Q1 0 Q2 0 Q3 0

If we start to fill in a table, then with the first row it would look like:

Logic ofQ3 Logic ofQ2 Logic ofQ1

0 0 0tA

tB

tC

tD

tE

tF

tG

tH

tI

tJ

Notice that the column headers are in descending order of: Q3, Q2 then Q1.

Now onwards to tB. Here, the new state of the system has: Q1 at ..., Q2 at ... and Q3 at ...


17/19

25 Q1 at 1, Q2 at 0 and Q3 at 0

So the second row of the table would look like ...

26Logic ofQ3 Logic ofQ2 Logic ofQ1

0 0 0

0 0 1

tA

tB

tC

tD

tE

tF

tG

tH

tI

tJ

Q1 1 Q2 0 Q3 0

And the circuit with the logic ofQ1, Q2 and Q3 would look like ...

Now complete rows of the table for times tC to tJ showing the values ofQ1, Q2 and Q3.

For convenience, the timing diagrams have been repeated below.

Q1

Q2

Q3

tItHtGtFtEtDtCtBtA tJ

27

Take your time to complete the table for the remaining times and move onto Frame 2


18/19


19/19

By now, you should realise that the circuit is a binary counter that counts from zero to seve

Notice that once the system has counted up to 1112, it resets back to 0, then it will continue

counting again. This occurs at tI.

Each flip-flops Q contributes to a digit of our binary representation. So three Flip-Flops gi

a three digit binary representation for counting with. The biggest number we can count to i

1112

which is equivalent to 710

.

Also note that it is Q3 that contributes to the MSB not Q1. Remember that the table we com

pleted is arranged Q3, Q2 then Q1, not Q1, Q2 then Q3. You could say that the counters bits

are reversed when we are to look at the actual flip-flop system circuit. So for example attG,

the number we were currently on was 1102 which looked like:

D1 Q1

D1 D2

CLK Q1

D2 Q2

Q2CLK

D3

D3 Q3

Q3CLK

28

29

Make a note of this in your exercise book then move onto Frame 2

The outputsD1,D2 andD3 represent the binary numberD3D2D1.

To summarise, the circuit below counts the binary numbers from 0002 to 1112.

Q1 0 Q2 1 Q3 1

0 1 1tG

d-type latch ii

Documents