16-bit transparent d-type latch with 3-state … · sn74lvc16373a 16-bit transparent d-type latch...

1OE

1LE

1D1

To Seven Other Channels

1Q1C1

1D

1

48

472

2OE

2LE

2D1


2Q1C1

1D

24

25

3613

Pin numbers shown are for the DGG, DGV, and DL packages.

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SN74LVC16373ASCAS755B –DECEMBER 2003–REVISED JUNE 2014

SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs1 Features 2 Applications1• Member of the Texas Instruments • Servers

Widebus™ Family • PCs and Notebooks• Operates From 1.65 V to 3.6 V • Network Switches• Inputs Accept Voltages to 5.5 V • Wearable Health and Fitness Devices• Max tpd of 4.2 ns at 3.3 V • Telecom Infrastructures• Typical VOLP (Output Ground Bounce) • Electronic Points of Sale

<0.8 V at VCC = 3.3 V, TA = 25°C3 Description• Typical VOHV (Output VOH Undershoot)

>2 V at VCC = 3.3 V, TA = 25°C The SN74LVC16373A device is a 16-bit transparentD-type latch which is designed for 1.65-V to 3.6-V• Ioff Supports Live-Insertion, Partial-Power-DownVCC operation.Mode, and Back-Drive Protection

• Supports Mixed-Mode Signal Operation (5-V Input Device Information(1)and Output Voltages With 3.3-V VCC)

PART NUMBER PACKAGE BODY SIZE (NOM)• Latch-Up Performance Exceeds 100 mA Per TSSOP (48) 12.50 mm × 6.10 mm

JESD 78, Class IITVSOP (48) 9.70 mm × 4.40 mm

• ESD Protection Exceeds JESD 22 SSOP (48) 15.80 mm × 7.49 mmSN74LVC16373A– 2000-V Human-Body Model (A114-A) BGA MICROSTAR 7.00 mm × 4.50 mmJUNIOR (56)– 1000-V Charged-Device Model (C101)

BGA MICROSTAR 8.00 mm × 5.50 mmJUNIOR (54)

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

4 Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SN74LVC16373ASCAS755B –DECEMBER 2003–REVISED JUNE 2014 www.ti.com

Table of Contents1 Features .................................................................. 1 9 Detailed Description ............................................ 11

9.1 Overview ................................................................. 112 Applications ........................................................... 19.2 Functional Block Diagram ....................................... 113 Description ............................................................. 19.3 Feature Description................................................. 114 Simplified Schematic............................................. 19.4 Device Functional Modes........................................ 115 Revision History..................................................... 2

10 Application and Implementation........................ 126 Pin Configuration and Functions ......................... 310.1 Application Information.......................................... 127 Specifications......................................................... 610.2 Typical Application ............................................... 127.1 Absolute Maximum Ratings ..................................... 6

11 Power Supply Recommendations ..................... 137.2 Handling Ratings....................................................... 612 Layout................................................................... 137.3 Recommended Operating Conditions ...................... 7

12.1 Layout Guidelines ................................................. 137.4 Thermal Information .................................................. 712.2 Layout Example .................................................... 137.5 Electrical Characteristics........................................... 8

13 Device and Documentation Support ................. 147.6 Timing Requirements ................................................ 813.1 Trademarks ........................................................... 147.7 Switching Characteristics .......................................... 813.2 Electrostatic Discharge Caution............................ 147.8 Operating Characteristics.......................................... 813.3 Glossary ................................................................ 147.9 Typical Characteristics .............................................. 9

14 Mechanical, Packaging, and Orderable8 Parameter Measurement Information ................ 10Information ........................................................... 14

5 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (September 2005) to Revision B Page

• Updated document to new TI data sheet format. ................................................................................................................... 1• Removed Ordering Information table. .................................................................................................................................... 1• Added Applications. ................................................................................................................................................................ 1• Added Device Information table. ............................................................................................................................................ 1• Added Handling Ratings table. .............................................................................................................................................. 6• Changed MAX ambient temperature to 125°C. ..................................................................................................................... 7• Added Thermal Information table. .......................................................................................................................................... 7• Added Typical Characteristics. .............................................................................................................................................. 9

2 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated

Product Folder Links: SN74LVC16373A


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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

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48

47

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35

34

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31

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25

1OE1Q11Q2

GND1Q31Q4VCC

1Q51Q6

GND1Q71Q82Q12Q2

GND2Q32Q4VCC

2Q52Q6

GND2Q72Q82OE

1LE1D11D2GND1D31D4VCC

1D51D6GND1D71D82D12D2GND2D32D4VCC

2D52D6GND2D72D82LE

DGG, DGV, OR DL PACKAGE(TOP VIEW)

SN74LVC16373Awww.ti.com SCAS755B –DECEMBER 2003–REVISED JUNE 2014

6 Pin Configuration and Functions

Pin FunctionsPIN

I/O DESCRIPTIONNO. NAME1 OE I Output Enable2 1Q1 O 1Q1 Output3 1Q2 O 1Q2 Output4 GND — Ground Pin5 1Q3 O 1Q3 Output6 1Q4 O 1Q4 Output7 VCC — Power Pin8 1Q5 O 1Q5 Output9 1Q6 O 1Q6 Output10 GND — Ground Pin11 1Q7 O 1Q7 Output12 1Q8 O 1Q8 Output13 2Q1 O 2Q1 Output14 2Q2 O 2Q2 Output15 GND — Ground Pin16 2Q3 O 2Q3 Output17 2Q4 O 2Q4 Output18 VCC — Power Pin19 2Q5 O 2Q5 Output20 2Q6 O 2Q6 Output

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Pin Functions (continued)PIN

I/O DESCRIPTIONNO. NAME21 GND — Ground Pin22 2Q7 O 2Q7 Output23 2Q8 O 2Q8 Output24 2OE O Output Enable 225 2LE I Latch Enable 226 2D8 I 2D8 Input27 2D7 I 2D7 Input28 GND — Ground Pin29 2D6 I 2D6 Input30 2D5 I 2D5 Input31 VCC — Power Pin32 2D4 I 2D4 Input33 2D3 I 2D3 Input34 GND — Ground Pin35 2D2 I 2D2 Input36 2D1 I 2D1 Input37 1D8 I 1D8 Input38 1D7 I 1D7 Input39 GND — Ground Pin40 1D6 I 1D6 Input41 1D5 I 1D5 Input42 VCC — Power Pin43 1D4 I 1D4 Input44 1D3 I 1D3 Input45 GND — Ground Pin46 1D2 I 1D2 Input47 1D1 I 1D1 Input48 1LE I Latch Enable 1




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GRD OR ZRD PACKAGE(TOP VIEW)

J

H

G

F

E

D

C

B

A

21 3 4 65

GQL OR ZQL PACKAGE(TOP VIEW)

JHGFEDCBA

21 3 4 65

K


Pin Assignments (1) (56-Ball GQL or ZQL Package)1 2 3 4 5 6

A 1OE NC NC NC NC 1LEB 1Q2 1Q1 GND GND 1D1 1D2C 1Q4 1Q3 VCC VCC 1D3 1D4D 1Q6 1Q5 GND GND 1D5 1D6E 1Q8 1Q7 1D7 1D8F 2Q1 2Q2 2D2 2D1G 2Q3 2Q4 GND GND 2D4 2D3H 2Q5 2Q6 VCC VCC 2D6 2D5J 2Q7 2Q8 GND GND 2D8 2D7K 2OE NC NC NC NC 2LE

(1) NC – No internal connection

Pin Assignments (1) (54-Ball GRD or ZRD Package)1 2 3 4 5 6

A 1Q1 NC 1OE 1LE NC 1D1B 1Q3 1Q2 NC NC 1D2 1D3C 1Q5 1Q4 VCC VCC 1D4 1D5D 1Q7 1Q6 GND GND 1D6 1D7E 2Q1 1Q8 GND GND 1D8 2D1F 2Q3 2Q2 GND GND 2D2 2D3G 2Q5 2Q4 VCC VCC 2D4 2D5H 2Q7 2Q6 NC NC 2D6 2D7J 2Q8 NC 2OE 2LE NC 2D8

(1) NC – No internal connection




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7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVCC Supply voltage range –0.5 6.5 VVI Input voltage range (2) –0.5 6.5 VVO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 VVO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 VIIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±50 mA

Continuous current through each VCC or GND ±100 mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of VCC is provided in the Recommended Operating Conditions table.

7.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range –65 150 °CHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 0 2000pins (1)

V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification 0 1000JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.




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7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITOperating 1.65 3.6

VCC Supply voltage VData retention only 1.5VCC = 1.65 V to 1.95 V 0.65 × VCC

VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 VVCC = 2.7 V to 3.6 V 2VCC = 1.65 V to 1.95 V 0.35 × VCC

VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VVCC = 2.7 V to 3.6 V 0.8

VI Input voltage 0 5.5 VHigh or low state 0 VCCVO Output voltage VHigh-impedance state 0 5.5VCC = 1.65 V –4VCC = 2.3 V –8

IOH High-level output current mAVCC = 2.7 V –12VCC = 3 V –24VCC = 1.65 V 4VCC = 2.3 V 8

IOL Low-level output current mAVCC = 2.7 V 12VCC = 3 V 24

Δt/Δv Input transition rise and fall rate 10 ns/VTA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

7.4 Thermal InformationDL

THERMAL METRIC (1) UNIT48 PINS

RθJA Junction-to-ambient thermal resistance 68.4RθJC(top) Junction-to-case (top) thermal resistance 34.7RθJB Junction-to-board thermal resistance 41.0

°C/WψJT Junction-to-top characterization parameter 12.3ψJB Junction-to-board characterization parameter 40.4RθJC(bot) Junction-to-case (bottom) thermal resistance n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.




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7.5 Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNITIOH = –100 μA 1.65 V to 3.6 V VCC – 0.2IOH = –4 mA 1.65 V 1.2IOH = –8 mA 2.3 V 1.7

VOH V2.7 V 2.2

IOH = –12 mA3 V 2.4

IOH = –24 mA 3 V 2.2IOL = 100 μA 1.65 V to 3.6 V 0.2IOL = 4 mA 1.65 V 0.45

VOL IOL = 8 mA 2.3 V 0.7 VIOL = 12 mA 2.7 V 0.4IOL = 24 mA 3 V 0.55

II VI = 0 to 5.5 V 3.6 V ±5 μAIoff VI or VO = 5.5 V 0 ±10 μAIOZ VO = 0 to 5.5 V 3.6 V ±10 μA

VI = VCC or GND 20ICC IO = 0 3.6 V μA

3.6 V ≤ VI ≤ 5.5 V (2) 20ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 μA

Ci VI = VCC or GND 3.3 V 5 pFCo VO = VCC or GND 3.3 V 6.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.(2) This applies in the disabled state only.

7.6 Timing Requirementsover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 VUNIT

MIN MAX MIN MAX MIN MAX MIN MAXtw Pulse duration, LE high 3.3 3.3 3.3 3.3 nstsu Setup time, data before LE↓ 1.6 1.2 1.7 1.7 nsth Hold time, data after LE↓ 1 1.1 1.2 1.2 ns

7.7 Switching Characteristicsover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 VVCC = 2.7 VFROM TO ± 0.15 V ± 0.2 V ± 0.3 VPARAMETER UNIT(INPUT) (OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAX

D 1.5 6.4 1 4.2 1 4.9 1.6 4.2tpd Q ns

LE 1.5 7.1 1 4.8 1 5.3 2.1 4.6ten OE Q 1.5 6.7 1 4.7 1 5.7 1.3 4.7 nstdis OE Q 1.5 8.4 1 5 1 6.3 2.5 5.9 ns

7.8 Operating CharacteristicsTA = 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 VTESTPARAMETER UNITCONDITIONS TYP TYP TYPOutputs enabled 32 35 39Power dissipation capacitanceCpd f = 10 MHz pFper latch Outputs disabled 4 4 6




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Temperature (qC)

TP

D -

ns

-100 -50 0 50 100 1500

1

2

3

4

5

6

D001

TPD in ns

VCC - V

TP

D -

ns

0 0.5 1 1.5 2 2.5 3 3.50

1

2

3

4

5

6

7

8

D002

TPD in ns


7.9 Typical Characteristics

Figure 1. SN74LVC16373A Figure 2. SN74LVC16373A LE to Q TDPLE to Q Across Temperature 3.3-V VCC VCC vs TPD at 25°C




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VM

thtsu

From OutputUnder Test

CL(see Note A)

LOAD CIRCUIT

S1VLOAD

Open

GND

RL

RL

Data Input

Timing InputVI

0 V

VI

0 V0 V

tw

Input

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VI

0 VInput

OutputWaveform 1S1 at VLOAD(see Note B)

OutputWaveform 2

S1 at GND(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH − V∆

≈0 V

VI

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHLtPLZ/tPZLtPHZ/tPZH

OpenVLOADGND

TEST S1

NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.D. The outputs are measured one at a time, with one transition per measurement.E. tPLZ and tPHZ are the same as tdis.F. tPZL and tPZH are the same as ten.G. tPLH and tPHL are the same as tpd.H. All parameters and waveforms are not applicable to all devices.

OutputControl

VM VM

VM VM

VM VM

VM

VM VM

VM

VM

VM

VI

VM

VM

1.8 V ± 0.15 V2.5 V ± 0.2 V

2.7 V3.3 V ± 0.3 V

1 kΩ500 Ω500 Ω500 Ω

VCC RL

2 × VCC2 × VCC

6 V6 V

VLOAD CL

30 pF30 pF50 pF50 pF

0.15 V0.15 V0.3 V0.3 V

V∆

VCCVCC2.7 V2.7 V

VI

VCC/2VCC/21.5 V1.5 V

VMtr/tf

≤2 ns≤2 ns

≤2.5 ns≤2.5 ns

INPUTS


8 Parameter Measurement Information

Figure 3. Load Circuit and Voltage Waveforms




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1OE

1LE

1D1


1Q1C1

1D

1

48

472

2OE

2LE

2D1


2Q1C1

1D

24

25

3613

Pin numbers shown are for the DGG, DGV, and DL packages.


9 Detailed Description

9.1 OverviewThe SN74LVC16373A device is particularly suitable for implementing buffer registers, I/O ports, bidirectional busdrivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latchedat the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high orlow logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive thebus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lineswithout interface or pullup components. OE does not affect internal operations of the latch. Old data can beretained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven fromeither 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V systemenvironment. To ensure the high-impedance state during power up or power down, OE should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of thedriver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

9.2 Functional Block Diagram

Figure 4. Logic Diagram (Positive Logic)

9.3 Feature Description• Wide operating voltage range

– Operates from 1.65 V to 3.6 V• Allows down voltage translation

– Inputs accept voltages to 5.5 V• Ioff feature

– Allows voltages on the inputs and outputs when VCC is 0 V

9.4 Device Functional Modes

Function Table(Each Latch)

INPUTS OUTPUTQOE LE D

L H H HL H L LL L X Q0

H X X Z




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uC or

System Logic

OE Vcc

GND

1D

8D

1Q

8Q

Regulated 3.6 V

uC

System Logic

LEDs

LE


10 Application and Implementation

10.1 Application InformationThe SN74LVC16373A device is a high drive CMOS device that can be used for a multitude of bus-interface typeapplications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V.Therefore, this device is ideal for driving multiple outputs and for high speed applications up to 100 Mhz. Theinputs are 5.5 V tolerant allowing it to translate down to VCC.

10.2 Typical Application

Figure 5. Typical Application Diagram

10.2.1 Design RequirementsThis device uses CMOS technology and has balanced output drive. Care should be taken to avoid buscontention because it can drive currents that would exceed maximum limits. The high drive will also create fastedges into light loads; therefore, routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure1. Recommended Input Conditions

– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.

2. Recommend Output Conditions– Load currents should not exceed 50 mA per output and 100 mA total for the part.– Outputs should not be pulled above VCC.




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Vcc

Unused Input

Input

Output

Input

Unused Input Output

ICC - V

Fre

quen

cy -

MH

z

0 10 20 30 40 50 600

0.5

1

1.5

2

2.5

3

D003

ICC 1.8 VICC 2.5 VICC 3.3 V


Typical Application (continued)10.2.3 Application Curves

Figure 6. ICC vs Frequency

11 Power Supply RecommendationsThe power supply can be any voltage between the MIN and MAX supply voltage rating located in theRecommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a singlesupply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for eachpower pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin aspossible for best results.

12 Layout

12.1 Layout GuidelinesWhen using multiple bit logic devices inputs should never float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only twoinputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not beleft unconnected because the undefined voltages at the outside connections result in undefined operationalstates. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digitallogic devices must be connected to a high or low bias to prevent them from floating. The logic level that shouldbe applied to any particular unused input depends on the function of the device. Generally they will be tied toGND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,unless the part is a transceiver.

12.2 Layout Example

Figure 7. Layout Diagram




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13 Device and Documentation Support

13.1 TrademarksWidebus is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

13.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

13.3 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

74LVC16373ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC16373A

74LVC16373ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 LD373A

SN74LVC16373ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS& no Sb/Br)


SN74LVC16373ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 LD373A

SN74LVC16373ADL ACTIVE SSOP DL 48 25 Green (RoHS& no Sb/Br)


SN74LVC16373ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS& no Sb/Br)


SN74LVC16373ADLR ACTIVE SSOP DL 48 1000 Green (RoHS& no Sb/Br)


SN74LVC16373ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS& no Sb/Br)


SN74LVC16373AZQLR ACTIVE BGAMICROSTAR

JUNIOR

ZQL 56 1000 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85 LD373A

SN74LVC16373AZRDR ACTIVE BGAMICROSTAR

JUNIOR

ZRD 54 1000 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85 LD373A

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

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PACKAGE OPTION ADDENDUM


Addendum-Page 2

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC16373A :

• Enhanced Product: SN74LVC16373A-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

http://focus.ti.com/docs/prod/folders/print/sn74lvc16373a-ep.html

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74LVC16373ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1

SN74LVC16373ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1

SN74LVC16373ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1

SN74LVC16373AZQLR BGA MI CROSTA

R JUNI OR

ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1

SN74LVC16373AZRDR BGA MI CROSTA

R JUNI OR

ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC16373ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0

SN74LVC16373ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0

SN74LVC16373ADLR SSOP DL 48 1000 367.0 367.0 55.0

SN74LVC16373AZQLR BGA MICROSTARJUNIOR

ZQL 56 1000 336.6 336.6 28.6

SN74LVC16373AZRDR BGA MICROSTARJUNIOR

ZRD 54 1000 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040078/F 12/97

48 PINS SHOWN

0,25

0,15 NOM

Gage Plane

6,006,20 8,30

7,90

0,750,50

Seating Plane

25

0,270,17

24

A

48

1

1,20 MAX

M0,08

0,10

0,50

0°–8°

56

14,10

13,90

48DIM

A MAX

A MIN

PINS **

12,40

12,60

64

17,10

16,90

0,150,05

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold protrusion not to exceed 0,15.D. Falls within JEDEC MO-153

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PACKAGE OUTLINE

C

1 MAX

TYP0.350.15

5.85TYP

3.25 TYP

0.65 TYP

0.65 TYP

56X 0.450.35

B 4.64.4 A

7.16.9

(0.625) TYP

(0.575) TYP

JRBGA - 1 mm max heightZQL0056APLASTIC BALL GRID ARRAY

4219711/B 01/2017

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. No metal in this area, indicates orientation.

BALL A1 CORNER

SEATING PLANE

BALL TYP 0.1 C

0.15 C B A0.08 C

SYMM

SYMM

BALL A1 CORNER

K

C

D

E

F

G

H

J

1 2 3 4 5 6

A

BNOTE 3

SCALE 2.100

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EXAMPLE BOARD LAYOUT

56X ( 0.33)(0.65) TYP

(0.65) TYP

( 0.33)METAL

0.05 MAXSOLDER MASKOPENING

METAL UNDERSOLDER MASK

( 0.33)SOLDER MASKOPENING

0.05 MIN


4219711/B 01/2017

NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

SYMM

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:15X

1 2 3 4 5 6

A

C

D

E

F

G

H

J

K

B

NON-SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASK DETAILSNOT TO SCALE

EXPOSED METAL

SOLDER MASKDEFINED

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(0.65) TYP

(0.65) TYP56X ( 0.33)


4219711/B 01/2017

NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

SYMM

1 2 3 4 5 6

A

C

D

E

F

G

H

J

K

B

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