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CSE 494: CSE 494: Electronic Design Electronic Design Automation Automation Lecture Lecture Routing Routing

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CSE 494: Electronic Design Automation. Lecture Routing. Routing. placement. global Routing. Generates a “loose” route for each net. Assigns a list of routing regions to each net without specifying the actual layers of wires. - PowerPoint PPT Presentation

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Page 1: CSE 494: Electronic Design Automation

CSE 494: Electronic CSE 494: Electronic Design Automation Design Automation

LectureLecture

RoutingRouting

Page 2: CSE 494: Electronic Design Automation

RoutingRouting

Generates a “loose” route for each net.Generates a “loose” route for each net. Assigns a list of routing regions to each Assigns a list of routing regions to each

net without specifying the actual layers net without specifying the actual layers of wires.of wires.

Finds the actual geometric layout of each net within the assigned routing regions.

placement

global Routing

detailed Routing

compaction

Global Routing

Detailed Routing

Page 3: CSE 494: Electronic Design Automation

Routing ConstraintsRouting Constraints 100% routing completion + area minimization, 100% routing completion + area minimization,

under a set of constraints:under a set of constraints: Placement constraint : usually based on fixed placementPlacement constraint : usually based on fixed placement Number of routing layersNumber of routing layers Geometrical constraints: must satisfy design rulesGeometrical constraints: must satisfy design rules Timing constraints (performance-driven routing): must satisfy Timing constraints (performance-driven routing): must satisfy

delay constraints delay constraints Crosstalk?Crosstalk?

Two-layer routing Geometrical constraint

Page 4: CSE 494: Electronic Design Automation

Classification of RoutingClassification of Routinggraph search

steiner tree

hierarchical

iterative

Maze

Line search

Left-edge

greedy

hierarchical

clock-tree

power & ground

channel

switchbox

over-the-cell

river

general purpose

restricted

global

detailed

specialized

ROUTERS

Page 5: CSE 494: Electronic Design Automation

Maze Router : Lee AlgorithmMaze Router : Lee Algorithm Lee, “An algorithm for path connection and its Lee, “An algorithm for path connection and its

application”, application”, IRE Trans. Electronic ComputerIRE Trans. Electronic Computer, EC-10, 1961, EC-10, 1961

Discussion mainly on single-layer routingDiscussion mainly on single-layer routing StrengthsStrengths

Guarantee to find connection between 2 terminals if it Guarantee to find connection between 2 terminals if it existsexists

Guarantee minimum pathGuarantee minimum path

WeaknessWeakness Requires large memory for dense layoutRequires large memory for dense layout SlowSlow

Applications: global routing, detailed routingApplications: global routing, detailed routing

Page 6: CSE 494: Electronic Design Automation

Lee AlgorithmLee Algorithm

Find a path from Find a path from S S toto T T by “wave propagation” by “wave propagation”

Filing Retrace Time & space complexity for an Time & space complexity for an M X NM X N grid: grid: O(M N) O(M N) ( (huge!huge!))

Page 7: CSE 494: Electronic Design Automation

Reducing Memory RequirementReducing Memory Requirement Akers’s Observation (1967)Akers’s Observation (1967)

Adjacent labels for Adjacent labels for K K are either are either k - 1k - 1 or or k + 1k + 1 Want a labeling scheme such that each label has its preceding label different Want a labeling scheme such that each label has its preceding label different

from its succeeding label from its succeeding label

Way 1: coding sequence 1,2,3,1,2,3,…; states : 1,2,3, empty, Way 1: coding sequence 1,2,3,1,2,3,…; states : 1,2,3, empty, blocked (3 bits required)blocked (3 bits required)

Way 2: coding sequence 1,1,2,2,1,1,2,2…; states : 1,2, empty, Way 2: coding sequence 1,1,2,2,1,1,2,2…; states : 1,2, empty, blocked (only 2 bits)blocked (only 2 bits)

sequence 1,2,3,1,2,3,…sequence 1,2,3,1,2,3,… sequencesequence 1,1,2,2,1,1,2,2…1,1,2,2,1,1,2,2…

Page 8: CSE 494: Electronic Design Automation

Reducing Running TimeReducing Running Time

Starting point selection: Choose the point farthest from the center Starting point selection: Choose the point farthest from the center as the starting point.as the starting point.

Double fan out: Propagate waves from both fan out and target Double fan out: Propagate waves from both fan out and target cells.cells.

Framing: Search inside a rectangle area 10-20% larger than the Framing: Search inside a rectangle area 10-20% larger than the bounding box containing the source and target.bounding box containing the source and target.

--Need to enlarge the rectangle and redo if the search fails--Need to enlarge the rectangle and redo if the search fails

Page 9: CSE 494: Electronic Design Automation

Connecting Multiple Terminal NetsConnecting Multiple Terminal NetsStep 1: Propagate wave from the source s closest target

Step 2: Mark ALL cells on the path as s

Step 3: Propagate wave from ALL s cells to other cells

Step 4: Continue until all cells are reached

Step 5: Apply heuristics to further reduce the tree cost.

Page 10: CSE 494: Electronic Design Automation

Routing on a Weighted GridRouting on a Weighted Grid

Motivation: Finding more desirable paths

Weight(grid,cells) = # unblocked grid cell segments -1

Page 11: CSE 494: Electronic Design Automation

A Routing Example on a Weighted GridA Routing Example on a Weighted Grid

First wave reaches target Finding other paths min-cost path found

Initialize cell weights Wave propagation

Page 12: CSE 494: Electronic Design Automation

Hadlock’s AlgorithmHadlock’s Algorithm

Hadlock, “A shortest path algorithm for grid graphs”, Hadlock, “A shortest path algorithm for grid graphs”, Networks, 1977.Networks, 1977.

Uses detour number (instead of labeling wave front in Uses detour number (instead of labeling wave front in Lee’s router.Lee’s router.

Detour number, d(P) = # of grid cells directed away from its Detour number, d(P) = # of grid cells directed away from its target on path Ptarget on path P

M D(S,T) fixed! M D(S,T) fixed! Minimize d(P) to find the shortest path. Minimize d(P) to find the shortest path. Path length of P, I(P): = M D(S,T) + 2d(P)Path length of P, I(P): = M D(S,T) + 2d(P) For any cell labeled i, label its adjacent unblocked cells away For any cell labeled i, label its adjacent unblocked cells away

from Ti+1, label i otherwise.from Ti+1, label i otherwise. Time and space complexities: O(Time and space complexities: O(MNMN), but substantially ), but substantially

reduces the # of searched cells.reduces the # of searched cells. Find the shortest path between S and T.Find the shortest path between S and T.

Page 13: CSE 494: Electronic Design Automation

Hadlock’s AlgorithmHadlock’s Algorithm D(P): # of grid cells directed D(P): # of grid cells directed

away from its target on Path away from its target on Path P.P.

MD(S,T): the Manhattan MD(S,T): the Manhattan distance between S and T.distance between S and T.

Path length of P, I(P): = M Path length of P, I(P): = M D(S,T) + 2d(P)D(S,T) + 2d(P)

M D(S,T) fixed! M D(S,T) fixed! Minimize Minimize d(P) to find the shortest path.d(P) to find the shortest path.

For any cell labeled i, label its For any cell labeled i, label its adjacent unblocked cells adjacent unblocked cells away from Ti+1, label i away from Ti+1, label i otherwise.otherwise.

Page 14: CSE 494: Electronic Design Automation

Soukup’s AlgorithmSoukup’s Algorithm Scoukup, “Fast maze router,” DAC-78Scoukup, “Fast maze router,” DAC-78 Combined breadth-first and depth-first searchCombined breadth-first and depth-first search

Depth-first (line) search is first directed toward target T until an obstacle or T is Depth-first (line) search is first directed toward target T until an obstacle or T is reachedreached

Breadth-first (Lee-type) search is used to “bubble” around an obstacle if an Breadth-first (Lee-type) search is used to “bubble” around an obstacle if an obstacle is reachedobstacle is reached

Time and space complexities: O(MN), but 10-50 times faster than Lee’s Time and space complexities: O(MN), but 10-50 times faster than Lee’s algorithmalgorithm

Find A path between S and T, but may not be the shortest!Find A path between S and T, but may not be the shortest!

Page 15: CSE 494: Electronic Design Automation

Features of Line-Search AlgorithmsFeatures of Line-Search Algorithms

Lines generated by

“escape” points

Mikami-Tabuchi

Time and space complexities: O(L), where L is Time and space complexities: O(L), where L is the # of line segments generated the # of line segments generated

Hightower

Every point is

An escape point

One escape point

Per line segment

Works on line segment

source target

Set A Set B

intersect

Path is found

Some line

From A

Some line

From B

generate

lines

generate

lines

Page 16: CSE 494: Electronic Design Automation

Mikami- Tabuchi’s AlgorithmMikami- Tabuchi’s Algorithm

Mikami & Tabuchi, “A computer program for Mikami & Tabuchi, “A computer program for optimal routing of printed circuit connectors.” optimal routing of printed circuit connectors.” IFIP, H47, 1968IFIP, H47, 1968

Every grid point is an escapeEvery grid point is an escape

Page 17: CSE 494: Electronic Design Automation

Hightower’s AlgorithmHightower’s Algorithm

Hightower, “A solution to line-routing problem on Hightower, “A solution to line-routing problem on the continuous plane,” DAC-69the continuous plane,” DAC-69

A single escape point on each line segmentA single escape point on each line segment If a line parallels to the blocked cells, the escape If a line parallels to the blocked cells, the escape

point is placed just past the endpoint of the point is placed just past the endpoint of the segmentsegment

Page 18: CSE 494: Electronic Design Automation
Page 19: CSE 494: Electronic Design Automation

Comparison of AlgorithmsComparison of Algorithms

Soukup, Mikami, and Hightower all adopt some sort Soukup, Mikami, and Hightower all adopt some sort of line-search operations => cannot guarantee of line-search operations => cannot guarantee shortest pathsshortest paths

MazeMaze SoukupSoukup HadlockHadlock MikamiMikami HightowerHightower

TimeTime O(MN)O(MN) O(MN)O(MN) O(MN)O(MN) O(L)O(L) O(L)O(L)

SpaceSpace O(MN)O(MN) O(MN)O(MN) O(MN)O(MN) O(L)O(L) O(L)O(L)

Finds path if one exists?Finds path if one exists? yesyes yesyes yesyes yesyes nono

Is the path shortest?Is the path shortest? yesyes nono yesyes nono nono

Works on grids or lines?Works on grids or lines? gridgrid gridgrid gridgrid lineline lineline

Page 20: CSE 494: Electronic Design Automation

Multilayered Routing Multilayered Routing 3-D grid3-D grid Two Planer arrays Two Planer arrays

Neglect the weight of inter-layer connections through via. Neglect the weight of inter-layer connections through via. Pins are accessible from both layers.Pins are accessible from both layers.

Page 21: CSE 494: Electronic Design Automation

Multilayered RoutingMultilayered Routing

Page 22: CSE 494: Electronic Design Automation

Net OrderingNet Ordering Net ordering greatly affects routing solutionsNet ordering greatly affects routing solutions In the example, we should route net ‘b’ before net ‘a’ In the example, we should route net ‘b’ before net ‘a’

Page 23: CSE 494: Electronic Design Automation

Net OrderingNet Ordering

Page 24: CSE 494: Electronic Design Automation

Net OrderingNet Ordering Order the nets in the ascending order of the number Order the nets in the ascending order of the number

of pins within their bounding boxesof pins within their bounding boxes Order the nets in their ascending (or descending ?) Order the nets in their ascending (or descending ?)

order of their lengthsorder of their lengths Order the nets based on their timing criticalityOrder the nets based on their timing criticality

Page 25: CSE 494: Electronic Design Automation

A mutually intervening caseA mutually intervening case

Net OrderingNet Ordering

Page 26: CSE 494: Electronic Design Automation

Rip-up and Re routingRip-up and Re routing

Rip up and re routing is required if a global or a Rip up and re routing is required if a global or a local router fails to route all netslocal router fails to route all nets

Approach: Manual or AutomatedApproach: Manual or Automated Two steps in rip-up and re-routingTwo steps in rip-up and re-routing

Identify bottleneck regions, rip-off some already Identify bottleneck regions, rip-off some already routed netsrouted nets

Route the blocked connections, then re-route the Route the blocked connections, then re-route the ripped connectionsripped connections

Repeat the two steps until all connections are Repeat the two steps until all connections are routed, or a time limit is exceededrouted, or a time limit is exceeded

Page 27: CSE 494: Electronic Design Automation

Graph Models for Global Routing: Graph Models for Global Routing: Grid GraphGrid Graph

Each cell is denoted by a vertexEach cell is denoted by a vertex Two vertices are joined by an edge if they are adjacent Two vertices are joined by an edge if they are adjacent

to each otherto each other The occupied cells are represented as filled circles, The occupied cells are represented as filled circles,

while the unoccupied cells are represented by empty while the unoccupied cells are represented by empty circlescircles

Page 28: CSE 494: Electronic Design Automation

Graph Model: Graph Model: Channel Intersection GraphChannel Intersection Graph

Channels are represented as edgesChannels are represented as edges Channel intersections are represented as verticesChannel intersections are represented as vertices Edge weight denotes channel capacityEdge weight denotes channel capacity Extended channel intersection graph: terminals are also Extended channel intersection graph: terminals are also

represented as verticesrepresented as vertices

Page 29: CSE 494: Electronic Design Automation

Global Routing ProblemGlobal Routing Problem Given a netlist N={Given a netlist N={NN11, N, N22,….,N,….,Nnn } , a routing graph } , a routing graph

G = (G = (V, EV, E), find a Steiner tree ), find a Steiner tree TTii for each net for each net NNii , 1, 1

i i nn, such that U(e, such that U(ejj) ) c(e c(ejj), ), eejj E E and and nni=1 i=1 L(TL(Tii) )

is minimized, whereis minimized, where c(ec(ejj): capacity of edge e): capacity of edge ejj;;

xxijij = 1 if e = 1 if ej j is in is in TTii ; ; xxijij = 0 otherwise; = 0 otherwise;

U(eU(ejj) = ) = nni=1 i=1 xxij ij : # of wires that pass through the channel : # of wires that pass through the channel

corresponding to the ecorresponding to the ejj

L(TL(Tii) = ) = total length of Steiner tree total length of Steiner tree TTii

For high-performance, the maximum wirelength For high-performance, the maximum wirelength (max(maxnn

i=1 i=1 L(TL(Tii) ) ) ) is minimizedis minimized (or the longest path (or the longest path

between two points in between two points in TTi i is minimized)is minimized)

Page 30: CSE 494: Electronic Design Automation

Global Routing in different Design StylesGlobal Routing in different Design Styles

global routing

full custom standard cell gate array FPGA

flexible channels

most general problem

flexible channels

fixed feedthroughsfixed channels

fixed routing tracks

switchbox constraints

Page 31: CSE 494: Electronic Design Automation

Global Routing in Standard CellGlobal Routing in Standard Cell ObjectiveObjective

Minimize total channel heightMinimize total channel height Assignment of feedthrough: Placement ? Assignment of feedthrough: Placement ?

Global Routing?Global Routing? For high performance,For high performance,

Minimize the maximum wire lengthMinimize the maximum wire length Minimize the maximum path lengthMinimize the maximum path length

feedthrough

failed net

Page 32: CSE 494: Electronic Design Automation

Global Routing in Gate ArrayGlobal Routing in Gate Array ObjectiveObjective

Guarantee 100% routability.Guarantee 100% routability.

For high performanceFor high performance Minimize the maximum wire lengthMinimize the maximum wire length Minimize the maximum path lengthMinimize the maximum path length

Each Channel has a capacity of 2 tracks

Page 33: CSE 494: Electronic Design Automation

Global Routing in FPGAGlobal Routing in FPGA ObjectiveObjective

Guarantee 100% routability.Guarantee 100% routability. Consider switch-mobile architectural constraints.Consider switch-mobile architectural constraints.

For performance-driven routing,For performance-driven routing, Minimize # of switches usedMinimize # of switches used Minimize the maximum wire lengthMinimize the maximum wire length Minimize the maximum path lengthMinimize the maximum path length

Each Channel has a capacity of 2 tracks

Page 34: CSE 494: Electronic Design Automation

Classification of Global-Routing AlgorithmClassification of Global-Routing Algorithm

Sequential approach: Assigns priority to nets; Sequential approach: Assigns priority to nets; routes one net at a time based on its priority (net routes one net at a time based on its priority (net ordering?).ordering?).

Concurrent approach: All nets are considered at Concurrent approach: All nets are considered at the same time (complexity?). the same time (complexity?).

Page 35: CSE 494: Electronic Design Automation

Global Routing: Maze RoutingGlobal Routing: Maze Routing Routing channels can be modeled by a weighted Routing channels can be modeled by a weighted

undirected graph called channel connectivity graphundirected graph called channel connectivity graph Channel = node, edge = connection between channels, Channel = node, edge = connection between channels,

capacity = weightcapacity = weight

Page 36: CSE 494: Electronic Design Automation

Global Routing by Global Routing by Integer ProgrammingInteger Programming

Suppose that for each net i, there are n(i) possible trees t(i,1) , t(i,2) Suppose that for each net i, there are n(i) possible trees t(i,1) , t(i,2) … t (i,n)… t (i,n)

Constraint 1: For each net i, only one t(i,j) will be selectedConstraint 1: For each net i, only one t(i,j) will be selected The capacity of each cell boundary c(i) is not exceededThe capacity of each cell boundary c(i) is not exceeded Minimize the total tree costMinimize the total tree cost Feasible for practical problem sizes?Feasible for practical problem sizes?

Key: Hierarchical approachKey: Hierarchical approach

Page 37: CSE 494: Electronic Design Automation

An Integer Programming ExampleAn Integer Programming Example

gi,j Cost of tree tij => g1,1 = 2, g1,2 = 3, g1,3 = 3, g2,1 = 2, g2,2 = 3, g2,3 = 3, g3,1

= 2, g3,2 = 2.

BoundaryBoundary tt1111 tt22

11 tt3311 tt11

22 tt2222 tt33

22 tt1133 tt22

33

B1B1

B2B2

B3B3

B4B4

00

11

00

11

11

00

11

11

11

11

11

00

11

00

11

00

00

11

11

11

11

11

00

11

11

11

00

00

00

00

11

11

Minimize 2x1,1 + 3x1,2 + 3x1,3 + 2x2,1 + 3x2,2 + 3x2,3 + 2x3,1 + 2x3,1 Subject to

x1,1 + x1,2 + x1,3 = 1 (Constraint I : t1) x2,1 + x2,2 + x2,3 = 1 (Constraint I : t2)

x3,2 + x3,2 = 1 (Constraint I : t3)

x1,2 + x1,3 + x2,1 + x2,3 + x3,1 =< 2 (Constraint II : B1) x1,1 + x1,3 + x2,2 + x2,3 + x3,1 =< 2 (Constraint II : B2)

x1,2 + x1,3 + x2,1 + x2,2 + x3,2 =< 2 (Constraint II : B3)

x1,1 + x1,2 + x2,2 + x2,3 + x3,2 =< 2 (Constraint II : B4)

xi,j = 0,1,1 =< i, j <= 3

Page 38: CSE 494: Electronic Design Automation

Hierarchical Global RoutingHierarchical Global Routing Marek-Sadowska, “Router planner for custom chip design,” ICCAD, ‘86. At each level of the hierarchy, an attempt is made to minimize the cost

of nets crossing cut lines. At the lowest level of the hierarchy, the layout surface is divided into R x

R grid regions with boundary capacity equal to C tracks. Let Rl be the # of grid regions of a given cut line l; a cut line can be

divided into M = Rl/C sections.

Global routing can be formulated as a linear assignment problem:

- xi,j = 1 if net i is assigned to section j; xi,j = 0 otherwise

- Each net crosses the cut line exactly once: Σmj=1 xjj= 1,1 <= i <= N.

- Capacity constraint of each section: Σni=1 xij <= C,1 <= i <= M.

- wi,j : cost of assignment net i to section j. Minimize Σni=1 Σm

j=1 wij xij

Page 39: CSE 494: Electronic Design Automation

The Routing-Tree ProblemThe Routing-Tree Problem Problem: Given a set of net, interconnect the pins by a Problem: Given a set of net, interconnect the pins by a

“routing tree.”“routing tree.”

Minimum Rectilinear Steiner Tree (MRST) Problem: Given n Minimum Rectilinear Steiner Tree (MRST) Problem: Given n points in the plane, find a minimum-length tree of rectilinear points in the plane, find a minimum-length tree of rectilinear edges which connects the points.edges which connects the points. MRST(P) = MST(P U S), where P and S are the sets of MRST(P) = MST(P U S), where P and S are the sets of original points and Steiner points, respectivelyoriginal points and Steiner points, respectively

Page 40: CSE 494: Electronic Design Automation

Theoretic Results for MRST ProblemTheoretic Results for MRST Problem Hanan’s Thm: There exists an MRST with all Steiner points (set S) chosen

from the intersection points of horizontal and vertical lines drawn points of P.

- Hanan, “On Steiner’s problem with rectilinear distance,” SIAM J. Applied Math., 1966.

Hwang’s Thm: For any point set P,cost(MST(P))/Cost(MRST(P))<= 3/2. - Hwang, “On Steiner’s minimal tree with rectilinear distance,” SIAM J.

Applied Math., 1976. Best existing approximation algorithm: Performs bound 61/48 by

Fossmeier et al. - Fossmeier et al, “Fast approximation algorithm for rectilinear Steiner

problem,” Wilhelm Scickard-Institut fűr informatik, TR WSI-93-14, 93. - Zelikovsky, “An 11/6 approximation algorithm for the network Steiner

problem,” Algorithmica., 1993.

Page 41: CSE 494: Electronic Design Automation

Channel and Switchbox RoutingChannel and Switchbox Routing

Page 42: CSE 494: Electronic Design Automation

Order of Routing Regions and N-ChannelsOrder of Routing Regions and N-Channels

a)a) No conflicts in case of routing in the No conflicts in case of routing in the order of 1, 2, and 3order of 1, 2, and 3

b)b) No ordering is possible to avoid conflictsNo ordering is possible to avoid conflicts

c)c) The saturation of (b) can be resolved by The saturation of (b) can be resolved by using L-channelsusing L-channels

d)d) An L-channel can be decomposed into a An L-channel can be decomposed into a channel and a switchboxchannel and a switchbox

1

23

(a)

12

34

(b)

1

2

(c)

1

2

(d)

Switchbox

Page 43: CSE 494: Electronic Design Automation

Routing ConsiderationsRouting Considerations

a)a) Number of terminals (two-terminals vs. Number of terminals (two-terminals vs. multi-terminal nets)multi-terminal nets)

b)b) Net widths (power and ground vs. signal Net widths (power and ground vs. signal nets)nets)

c)c) Via restrictions (stacked vs. conventional Via restrictions (stacked vs. conventional vias)vias)

d)d) Boundary types (regular vs. irregular)Boundary types (regular vs. irregular)e)e) Number of layers (two vs. three, more Number of layers (two vs. three, more

layers?)layers?)f)f) Net types (critical vs. non-critical nets)Net types (critical vs. non-critical nets)

Page 44: CSE 494: Electronic Design Automation

Routing ModelsRouting Models

Grid-based model:Grid-based model: A grid is super-imposed on the routing region.A grid is super-imposed on the routing region. Wires follow paths along the grid lines.Wires follow paths along the grid lines.

Gridless model:Gridless model: Any model that does not follow the gridded approachAny model that does not follow the gridded approach

grid-based gridless

Page 45: CSE 494: Electronic Design Automation

Models for Multi-Layer RoutingModels for Multi-Layer Routing Unreserved layer model: Any net segment Unreserved layer model: Any net segment

is allowed to be placed in any layer.is allowed to be placed in any layer. Reserved layer model: Certain types of Reserved layer model: Certain types of

segments are restricted to particular segments are restricted to particular layer(s).layer(s). Two-layer: HV (horizontal-Vertical), VHTwo-layer: HV (horizontal-Vertical), VH Three-layer: HVH, VHVThree-layer: HVH, VHV

3 types of 3-layer models

Page 46: CSE 494: Electronic Design Automation

Terminology for Channel Routing ProblemsTerminology for Channel Routing Problems

• Local density at column i : total # of nets that crosses column i

• Channel density: maximum local density; # of horizontal tracks required >= channel density

Page 47: CSE 494: Electronic Design Automation

Channel RoutingChannel Routing ProblemProblem Assignments of horizontal segments of nets to Assignments of horizontal segments of nets to

tracks.tracks. Assignments of vertical segments to connect.Assignments of vertical segments to connect.

horizontal segments of same nets in different tracks, andhorizontal segments of same nets in different tracks, and the terminals of the net to horizontal segments of the net.the terminals of the net to horizontal segments of the net.

Horizontal and vertical constraints must not be Horizontal and vertical constraints must not be violated.violated.

Horizontal constraint between two nets: The horizontal span of Horizontal constraint between two nets: The horizontal span of the two nets overlap each other.the two nets overlap each other.

Vertical constraint between two nets: There exists a column Vertical constraint between two nets: There exists a column such that a terminal on top of the column belongs to one net and such that a terminal on top of the column belongs to one net and the terminal at the bottom of the column belongs to the other net.the terminal at the bottom of the column belongs to the other net.

Objective: Channel height is minimized ( Objective: Channel height is minimized ( i.e. i.e. channel area is minimizedchannel area is minimized) )