cs-ee 481 spring 2004 1founder’s day, 2004 university of portland school of engineering project...
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CS-EE 481 Spring 2004
Founder’s Day, 2004 1University of Portland School of Engineering
Project SteelheadA CMOS 4-Bit x 4-Bit Multiplier
AuthorsScott Sato
Ross Yoshioka
AdvisorDr. Osterberg, Dr. Lillevik
Industry RepresentativeMr. Michael M. DeSmith
Intel Corporation
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Agenda
• Introduction Ross Yoshioka
• Background/Demonstration Ross Yoshioka
• Methods Ross Yoshioka
• Results Scott Sato
• Conclusions Scott Sato
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Introduction
Dr. Osterberg, Dr. Lillevik, Michael DeSmith, Sandy Ressel, and Dr. Lu for your countless advice and support! ! !
- Solves the Problem of Serial Multiplication of two 4-bit binary numbers (0-15 in Decimal).
- Used as a Demo for Future Students- Answer sent out in 8-bit binary, converted to decimal
equivalent (Highest Value = 225)- Learn the general workings of how to design and create a 4-
bit x 4-bit Serial Multiplier.
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Background/Demonstration
1. Turn the 2 Rotary Devices on Our Input Pad
2. Both Numbers are Displayed on the Red Displays in Decimal Form
3. Press the Clear than the Equal Button
4. Answer Shows up in Decimal Form on Green Display.
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Methods
1. Designed the MOSIS chip using B²Logic (D-Flip Flops, Combinational Logic, etc.)
2. Converted B²Logic File to TPR File
3. Designed the Logic behind the input and output devices (GAL’s/ABEL, BCD-to-7-Segment Decoders, etc.)
4. Created Macro Model and System Model
5. Replace Macro Model with MOSIS chip
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B²Logic Simulation
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Results(Top Level Diagram)
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Block Diagram
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Chip Block Diagram
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Output Decoder Diagram
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B²Logic Simulation
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TPR File
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Conclusions- Demonstrated the Design of a CMOS Multiplier:
- B2Logic Simulation
- TPR File Creation
- I/O System Design and Implementation
- Integration of the Prototype’s Parts
- Keep on schedule throughout the Design Process
- Checking and Rechecking the TPR. File Until it is Absolutely Correct - In the future, maybe even use BLT (Project Pitroach)