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8-bit X 8-bit SRAM and 3 X 8 Decoder

Irina Vazir, Prabhjot Balaggan and Sumandeep Kaur

Advisor: Dr. David Parent

December 06, 2004

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Agenda• Abstract• Introduction• Project Details• Results• Cost Analysis• Conclusions

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Abstract

• We designed an 8-bit X 8-bit SRAM and a 3 X 8 decoder that operated at 200 MHz and uses 5.425 mW of Power and occupied an area of 462 m x 532 m.

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Introduction• SRAM: Memory circuit that permits writing and

reading, stored data can be retained indefinitely without any periodic refresh.

• 1-bit data storage cell: Full CMOS SRAM cell configuration.

• Equation used for wn and wp of the cell:

(W/L)3/ (W/L) 1 < 2(VDD – 1.5VT,n)1.5VT,n

(VDD – 2VT,n)2

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1-bit cell of the SRAM

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Project Details

• 8-bit X 8-bit SRAM that operates at 5ns.

• The project was divided into subsystems namely the SRAM cell, precharge circuit, sense amplifiers, write circuit, mux-based DFF’s and the decoder.

• Output of the decoder specifies address for the SRAM cells, where the data needs to be written or read from.

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SRAM Schematic #1

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SRAM Schematic #2

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SRAM Layout

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SRAM Test bench

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SRAM Verification

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SRAM simulation: Post Extracted

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SRAM Simulations

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Decoder Schematic

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Longest Path Calculations for the Decoder

Logic Level

Gate Cg to Drive

#CDNs #CDPs #LNs #LPs WN (H.C)

WP (H.C)

WN (S)

WP (S)

WN (L)

WP (L)

Cg of gate

1 Inv_Out 1 1 1 1 2.7 4.5 2.7 4.5 4.95 7.05 80 2 NAND 12.3 5 3 3 1 4.05 3.45 4.5 3.9 7.05 4.95 3 Inv_In 50.9 1 1 1 1 3.3 5.85 3.3 5.85 4.85 7.05

nsns

PHL 33.3

1 Note: All widths are in microns

and capacitances in fF

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Decoder Layout

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Decoder Verification

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Decoder Simulation: Post Extracted

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Cost Analysis

Task Number of days

• Verifying Logic: 4 days

• Verifying Timing: 7 days

• Layout: 8 days

• Post Extracted Timing: 1 day

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Lessons Learned

• Start early.

• Test at every phase.

• No IT support on weekends.

• Planning is very important.

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Summary

• We designed an 8-bit X 8-bit SRAM and a 3 X 8 decoder that operated at 200 MHz and uses 5.425 mW of Power and occupied an area of 462 m x 532 m.

• Future designs can definitely minimize area.

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Acknowledgements

• Thanks to our family members for putting up with us.

• Thanks to Cadence Design Systems for the VLSI lab.

• Thanks to Synopsys for Software donation.

• Thanks to Professor Parent for his guidance

throughout the project.