by Ira PitelExpert View

58 IEEE PowEr ElEctronIcs MagazInE zMarch 2019

current-Fed Power Processing—ride through robustness

Selecting the best power convert-er topology for a specific applica-tion can be somewhat over-

whelming considering the advances made in the past 20 years. Many of these advances were accomplished with better semiconductor switches providing faster switching rates, lower on-state voltages, lower power loss, lower power driver requirements, and so on. Selecting the best power convert-er topology must balance the applica-tion’s demands with priorities of cost, size/packaging, efficiency, and robust-ness. Magna-Power Electronics (Mag-na-Power), a programmable dc power product manufacturer in Flemington, New Jersey, United States, prioritized robustness in its topology selection. The topology choice was driven by the customers’ need for high reliability in demanding in dustrial environments.

With Magna-Power products often being used in experimental, proto-type validation applications, custom-er satisfaction required consistent power converter performance well beyond typical operating conditions. Having shipped tens of thousands of power supplies, the vast majority of field failures results from customer abuse, such as■■ corrosion■■ abnormal input voltage such as

lightning, power line transients, and power line harmonics

■■ output abuse, such as back-fed volt-ages and excessive ac currents

■■ susceptibility of electromagnetic interference in abnormal environ-ments

■■ poor packaging of power supplies in equipment racks resulting in restrictive air flow and exces-sive heating.Typical methods to improve re -

liability are the implementation of n + 1 redundancy and lowering the mean time between failure. These techniques can only partially improve long-term reliability if the cause of failure is a result of external conditions. For exam-ple, a power supply placed in an indus-trial environment, which is subjected to high incoming voltage transients, will be more reliable at utilizing input recti-fiers with a higher blocking voltage rat-ing. In this case, improving reliability with higher-voltage devices can be more beneficial than having redundant power supplies with lower component ratings, which will all fail from the same external environmental condi-

tion. Surviving an abnormal external influence, even if operation is temporal-ly aborted, is far better than the product failing and relying on a spare.

One of Magna-Power’s key objec-tives has been to develop power cir-cuits capable of riding through poten-tially damaging conditions. St rong ride-through capability, or fault resis-tance, lowers field returns, reduces cost-ly repairs, and, most importantly, pre-serves customer satisfaction. Fault pro-tection cannot be achieved under all conditions, but knowing the weak points in a design can give a better understand-ing to possible improvements.

Most power supply designs in the 1-kW and up power range use a volt-age-fed topology or a similar deriva-tive. As illustrated in Figure 1, the input stage is a dc source feeding a capacitor, bridge inverter, a trans-former for ohmic isolation, an output rectifier, and inductor-capacitor low-pass filter. The weak point of the design is the bridge inverter. If one of the devices should fail or erroneously

Digital Object Identifier 10.1109/MPEL.2018.2886110 Date of publication: 19 February 2019

C1

Q2

Q4

D6 D8

L1Q1

Q3 T1D5 D7

C2

Input

Output+–

D1 D3

D2 D4

FIG 1 A voltage-fed converter.

SL Series XR Series TS Series MS Series MT Series

60 IEEE PowEr ElEctronIcs MagazInE zMarch 2019

turn on, the resulting effects can be quite dramatic: failure of other bridge inverter devices, flames, and damage to surrounding circuitry. If the bridge inverter circuit does not switch with a near-perfect volt-second balance, the transformer core will saturate, possibly resulting in similar fail-ure conditions.

There have been considerable advanc-es in the fault detec-tion of voltage-fed con-verters. However, pro-tection schemes must still operate on the order of microsec-onds. Such failures are thermal and de -vice dependent. Pro-tect ion advances include detection of on-state conduction with antisaturation-sensing circuitry and current-mode con-trollers that limit peak current through transformers to prevent core saturation.

Any external influence causing a wrong switching state can result in a potential failure with little time to take correc-tive action.

Current-Fed ConverterFigure 2 shows the electrical dual of the voltage-fed converter, i.e., a current-fed converter. The current-fed topology has

been around for a long time, but it is rarely commercially deployed because of the need and added cost for creating a current source input plus the demand for a low-leakage trans-former [1]. The differ-ences between volt-age-fed and current-fed converters are very subtle. The volt-age-fed bridge devic-

es should never short the input dc bus, as opposed to the current-fed bridge devices, which should never open the

input dc bus. Second, output induc-tor L1 in a voltage-fed converter is on the output side of the converter, but it is on the input side of the current-fed converter.

As illustrated in Figure 3, the re -quirement for a current source input can be achieved with a buck converter or chopper operated as a voltage-to-current converter. While this is indeed a negative point of the topology, this added stage can be utilized for protec-tion between the two converter stages.

The inverter stage, which has the primary function of ohmic isolation and voltage transformation, should operate at a near 50% duty cycle. This stage can be operated at a lower switching frequency with virtually no degradation in dynamic performance. All of the converter control is governed by the buck converter stage. A low-leakage impedance for transformer T1 ensures high converter efficiency and low output voltage ripple. During com-mutation of the two inverter poles, the dc bus across the inverter shorts, and current is blocked from f lowing through the output stage.

With the current-fed converter, the time to protect any semiconductor device is dependent on the switching period of the buck converter and the design of inductor L1; both of these parameters govern the time needed to prevent core saturation of inductor L1. For a buck converter operating at 20 kHz, a typical 10-μs period can eas-ily be deployed to protect controlled semiconductor devices within the nor-mal operating limits. This protection

L1

Q1

Q3

Q2

Q4

T1D5 D7

D6 D8

C1

OutputInput

D1 D3

D2 D4

FIG 2 A current-fed converter.

Input C2 D9

Q5

L1

D12

D13

D14

D15

L2

D11

D10Q1

Q3

Q2

Q4

T1

D5 D7

D6 D8

C1

Output

D1 D3

D2 D4

FIG 3 A current-fed converter with a buck converter.

With the current-fed converter, the time to protect any semicon-ductor device is dependent on the switching period of the buck converter and the design of inductor L1.

March 2019 zIEEE PowEr ElEctronIcs MagazInE 61

can be applied to the inverter or buck semiconductor switches in the event of erroneous switching states, trans-former shorts, or output diode shorts. During a fault condition, the dc bus across the bridge inverter collaps-es, protecting the re -maining devices from catastrophic failure. With the dc bus cur-rent being limited to a current level set and maintained by the buck converter, core saturation of trans-former T1 is virtual-ly impossible.

With sufficient time, fault protec-tion circuitry can be devised to protect the inverter stage with the buck con-verter stage and the buck converter stage with the inverter stage. Also, fail-ure of a controlled semiconductor switch is current limited by the buck

converter, which prevents catastroph-ic failures. Because of the extended time for protection, special antisatura-tion circuitry is not required.

One additional attribute of current-fed topologies is scalabi lity to higher-

power, physically larg-er systems. Adding a little extra induc-tance in series with inductor L1 has vir-tually no effect on system performance. Stages can be easily pa ralleled without ma jor concern for lead inductances.

Despite the advantages of a current-fed design, voltage-fed designs are far more prevalent in industry. Voltage-fed topologies do require one fewer power conversion stage and have fewer mag-netic components. Both of these requirements have an impact on cost

and efficiency. Manufacturing a single-board power supply can be more cost-effective when power levels are lower—in the 1-kW and lower range. Many man-ufacturers gang multiple assemblies of the same design to achieve higher power levels, but such designs can have a negative effect on system reliability by additional parts count.

The Challenges of the Current-Fed ConverterManufacturing current-fed converters have their challenges in a compet-itive market. There is an extra power conversion stage taking up physical volume along with the materials cost associated with it. Conventional control circuits cannot be used be -cause of the duality of the design, and these circuits have to be de signed from fewer integrated devices. Trans-formers designed for extremely low leakage inductance require unique core

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Despite the advantag-es of a current-fed design, voltage-fed designs are far more prevalent in industry.

62 IEEE PowEr ElEctronIcs MagazInE zMarch 2019

geometries. The demands of tighter packaging and specialized magnetic circuits have required Magna-Power Electronics to vertically integrate its manufacturing operations to minimize outsourcing and to optimize its designs.

Today, Magna-Power Electronics manufactures all its assemblies in house. This decision has helped keep the company competitive in a global market, allowing it to realize the cur-rent-fed topology plus improving quality and delivery times. Manufacturing oper-ations include sheet metal fabrication, powder coating, robotic heat sink and fastener assembly, automated surface mount and through-hole printed circuit board assembly, magnetics winding and core fabrication, computer numerical control machining, wire harness fabri-cation, final assembly, and testing.

About the AuthorIra Pitel (ipitel@magna-power.com) received his B.S. degree from Rutgers, The State University of New Jersey; his M.S. degree from Bucknell Univer-sity; and his Ph.D. degree from Carne-gie Mellon University in 1972, 1975, and 1978, respectively. From 1973 to 1981, he worked for GTE Sylvania, Bell Laboratories, and Exxon Enter-prises as a research engineer specializ-ing in high-frequency ballasting tech-niques for gaseous discharge lighting, power distribution, and ac drives. In 1981, he founded Magna-Power Elec-tronics, a company specializing in cus-tom and standard power conditioning products. As president, he is responsi-ble for technology oversight and man-ufacturing of its line of 1.5–3,000+ kW ac to dc power supplies and electronic

loads. In 1986, he joined Texas A&M University as an adjunct professor. He holds 29 patents in the field of power electronics and is corecipient of the 1995 Society Prize Paper Award of the IEEE Industry Applications Society. He was honored as the Rutgers Out-standing Engineering Alumnus in 2000 and with the Gerald Kliman Innovator Award in 2008. He is a Life Fellow of the IEEE and has served in many IEEE capacities, including Society president of the IEEE Industry Appli-cations Society. He is a member of Eta Kappa Nu and Tau Beta Pi.

Reference[1] I. Abraham, Pressman: Switching Power

Supply Design, 2nd ed. New York: McGraw-Hill,

1998.

the unwillingness to license competi-tors while l icensing all other appli-cants. The TIA guidelines also state that the FRAND com-mitment is in tended to prevent a patent holder from securing a monopoly in any market as a result of the standardiza-tion process.

Qualcomm defend-ed its position by saying it was just following industry practice and that modem chip suppli-ers never receive SEP licenses. The court disposed of this argument in a couple of ways. First, the court noted, Qual-comm itself was the recipient of SEP licenses, suggesting that its claim that

this was industry practice was not the case. Besides, the court pointed out, Qualcomm argued in another lawsuit

that the TIA policy compels a competitor to license any patents required to develop products that are compl ia nt with a given standard.

Qualcomm also ar -gued that the FRAND requirement only ap -plies to applicants who “practice or im -plement whole stan-dards,” and since the chip could not imple-ment the whole stan-

dard, a license is not required. The court dismissed this argument by pointing to the TIA requirement that the licenses must be extended to “the

extent necessary for the practice of any or all of the normative portions for the field of use of practice of the standard.” Thus, even a portion trig-gers the FRAND commitment.

The takeaway lesson is that signing onto a FRAND commitment means that anyone who wants to participate in the industry involving the standard being established must be granted a license under FRAND terms.

About the Author Art MacCord (amaccord@maccord mason.com) has practiced patent, trademark, copyright, and trade-secret law for more than 35 years and is a graduate of the University of Virginia and George Washington University Law School. He currently practices with MacCord Mason PLLC in Greens-boro, North Carolina.

(continued from page 57)Patent Reviews

The takeaway lesson is that signing onto a FRAND commitment means that anyone who wants to participate in the industry involving the standard being established must be granted a license under FRAND terms.