crescent heart software - c-h-s.com

CRESCENT HEART SOFTWARE

CHS151 R7000D & CHS152 R7000E DISASSEMBLERS

FOR USE IN PROBING RM7000 & RM527X PROCESSORS

USING TEKTRONIX TLA7XX LOGIC ANALYZERS

Produced by Crescent Heart Software, Portland, Oregon, USATelephone (503)232-2232; Facsimile (503)232-2255; E-mail [email protected]; Internet http://www.c-h-s.com

Crescent Heart Software assumes no liability for errors, or for any incidental, consequential, indirect or specialdamages, including, without limitation, loss of use, loss or alteration of data, delays, or lost profits or savings,arising from the use of this document or any product which it accompanies.

Copyright © Crescent Heart Software 1998, 1999. All rights reserved. Licensed software products are owned byCrescent Heart Software or its suppliers and are protected by United States copyright laws and internationaltreaty provisions.

This manual revision supersedes all previously published material. Specifications change privileges reserved.

No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by anymeans, mechanical, photocopying, recording or otherwise, without the prior written permission ofCrescent Heart Software.

TEKTRONIX is a registered trademark of Tektronix, Inc. All others are trademarks of their respective companies.

Printed in the United States of America.

Manual part number: MAN-CHS151/2-R7000D/E-SFW7

Manual revision number 4 - August, 1999

Please register purchase of this software product upon receipt by requesting a registration form and returningthe filled-out form back to us. Registration enables us to provide you with top-flight technical support and tokeep you informed of product updates and new products. Obtain a registration form by sending e-mail with"CHS151/2-R7000D/E-SFW7 Registration" as the subject to [email protected].

Please communicate suggestions for product and documentation improvements to [email protected].

TABLE OF CONTENTSSection 1: Introduction

1.1 Connection To System Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.2 Installing Disassembler And Support Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.3 About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Section 2: Configuring The Acquisition Module2.1 Loading Support Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2 Channel Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.3 Clocking Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3.1 Clocking Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.3.2 Acquisition Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3.2.1 Request Cycle Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.3.2.2 Processor Nonissue Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.3.3 Inst Read Accesses Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.3.4 Data Read Accesses Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62.3.5 Write Accesses Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62.3.6 Miscellaneous Cycles Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4 Symbols And Symbol Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72.5 Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Section 3: Disassembly Display Of Data3.1 Acquiring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.2 Fundamental Disassembly Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2.1 Processor Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.2.1.1 PC-With-Displacement Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.2.1.2 Address Group Symbol Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2.2 Instruction/Data Block Read Ambiguity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.2.3 Memory Access Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.2.4 Subblock Data Transfer Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.2.5 Tracing Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3 Understanding The Disassembly Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43.4 Disassembly Format Definition Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.4.1 Display Mode Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53.4.1.1 Hardware Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63.4.1.2 Software Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.4.1.3 Control Flow Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83.4.1.4 Subroutine Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4.2 Disassemble Across Gaps Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.4.3 Inst/Data Display Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.4.4 Cache Display Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.4.5 NonCache Display Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103.4.6 Misc Display Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103.4.7 H/W Cycles Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113.4.8 Regs-Byte Order Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.4.8.1 Register Naming Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113.4.8.2 Byte Order Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.4.9 Exceptions Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113.4.10 Interrupt Ctrl Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.4.10.1 IV Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-133.4.10.2 Interrupt Spacing Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143.4.10.3 Interrupt Priority Levels Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.4.11 Label Display Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

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3.4.12 Write Reissues Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163.4.13 External Cache Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163.4.14 Processor Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173.4.15 Uncached Area1 Begin Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173.4.16 Uncached Area1 Size Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173.4.17 Uncached Area2 Begin Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173.4.18 Uncached Area2 Size Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183.4.19 Data Area1 Begin Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183.4.20 Data Area1 Size Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183.4.21 Data Area2 Begin Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183.4.22 Data Area2 Size Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.5 Marking Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-193.6 Alternative Data Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

3.6.1 State Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-203.6.2 Timing Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Section 4: Acquisition Clocking Choices4.1 Custom Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.2 External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.3 Internal Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

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ii R7000D/E Probe Adapter Manual

APPENDICES

Appendix A: Channel AssignmentsA.1 Connection To System Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1.1 Acquisition Module Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1A.1.1 Unused Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 Channel Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2A.2.1 SysAD-Hi Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2A.2.2 A Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4A.2.3 Address Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4A.2.4 SysAD Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4A.2.5 Control Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6A.2.6 TcLine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7A.2.7 TcWord Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8A.2.8 TcVM Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8A.2.9 Intr Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9A.2.10 Chk Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9A.2.11 TcCtrl Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10A.2.12 TcCtrl2 Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10A.2.13 Misc Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10A.2.14 Mode Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11A.2.15 XRAS Group (R7000E Support Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11A.2.16 Clk Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11A.2.17 JTAG Group (R7000E Support Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12

Appendix B: Software Warranty And Service

Appendix C: History Of RevisionsC.1 Manual Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1C.2 Software Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

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R7000D/E Probe Adapter Manual iii

LIST OF FIGURES

Figure 2.1: LA Module Setup Window (R7000D Support) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2Figure 2.2: LA Module Setup Window Clocking Options (R7000D Support) . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 3.1: Example Disassembly Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2Figure 3.2: Disassembly Properties Page (R7000D Support) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6Figure 3.3: Example Of Hardware Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7Figure 3.4: Example Of Special Cycles Hardware Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12Figure 3.5: Timing Display Of An Acquire-All-Cycles Custom Clocking Acquisition . . . . . . . . . . . . . . . . 3-21

Figure 4.1: Example Timing Display Of An Internal Clocking Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

LIST OF TABLES

Table 2.1: Control Group Symbol Table (R7000D_Ctrl, R7000E_Ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8Table 2.2: Intr Group Symbol Table (R7000D_Intr, R7000E_Intr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 3.1: Processor General Purpose Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13Table 3.2: Exception Vector Labeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14Table 3.3: Enhanced Interrupt Vector Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Table A.1: SysAD-Hi Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3Table A.2: A Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4Table A.3: Address Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5Table A.4: Control Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6Table A.5: TcLine Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7Table A.6: TcWord Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8Table A.7: TcVM Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8Table A.8: Intr Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9Table A.9: Chk Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9Table A.10: TcCtrl Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10Table A.11: TcCtrl2 Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10Table A.12: Misc Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10Table A.13: Mode Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11Table A.14: XRAS Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11Table A.15: Clk Group Channel Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11Table A.16: JTAG Group Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12

Table Of Contents

iv R7000D/E Probe Adapter Manual

This manual describes CHS151 R7000D and CHS152 R7000E disassembler software products for usein probing MIPS RM7000 processors using Tektronix TLA7xx logic analyzers.

Both disassemblers can be used to probe RM7000 processors which are not configured to performmultiple outstanding reads (MORs). The R7000D support requires use of a single acquisition modulehaving 136 channels. The R7000E support requires use of a two merged acquisition modules: thefirst (master module) having 136 channels, and the second (slave module) having at least 102channels.

The R7000D version of support makes no provision for probing the JTDI, JTDO, JTMS, JTCK,BigEndian, SysCmdP, PRqstB, PackB and RspSwapB processor signals, while all signals ofthe processor are probed by the R7000E support. Except for this difference and the relatedfact that some of the probe channel assignments are different, the two versions of softwarefunction identically. Note that only ten (10) of the channels of the second acquisition moduleare utilized in probing the processor under the R7000E support; the remainder of the channelsare available for probing other signals of the user’s system. Refer to Appendix A, ChannelAssignments, for further information.

In the remainder of this manual references to “the disassembler” apply to both the R7000D andR7000E versions of the disassembler, except as noted.

Provided with the disassembler are this manual and a 3.5" disk containing disassembly and supportsoftware.

1.1 PROCESSOR-PROBING APPLICABILITY

Normal use of the disassembler involves probing the non-MORs RM7000 and its RdType signal; useof the RdType signal allows the disassembler to unambiguously interpret memory reads as beingeither for instruction or data access.

For backward compatibility in using the same connection means to the system under test as was usedfor probing earlier MIPS processors with similar buses which do not provide a RdType signal (suchas the R5000), the disassembler also supports probing non-MORs RM7000s without requiringconnection of the RdType signal.

Use of the RdType signal is recommended where possible, as without it automatic resolutionof memory read accesses (instruction versus data) cannot be accomplished.

Further backward compatibility in probing the similar-pinout RM527x is also provided. The supportsoftware, although oriented toward probing the RM7000, does allow selection of either RM7000 orRM527x disassembly display; the software may thus be thought of as effectively providing thefunctionality of two disassemblers.

Where RM527x-RM7000 foward/backward probing compatibility is not an issue, it isrecommended that consideration be given to use of companion CHS134 R5270E and CHS135R5270F disassembler products (which provide support for probing the RM527x only) forprobing the RM527x.

This is because the R7000D/E products have defined certain probing signal groups (such asthe Control, TcLine and Intr groups, as well as the Control and Intr symbol tables) in accordwith the requirements of probing the RM7000 in particular, rather than the RM527x.

1. INTRODUCTION

R7000D/E Disassembler Manual 1-1

Note that when probing RM527x systems or RM7000 systems without benefit of the RdType signal, itis recommended that the RdType probe be attached to a constant high or low electrical level or thatthe probe be left disconnected (which is also equivalent to use of a high level due to the pullupcharacteristic of the probe). Ensure that the acquisition clocking choices selected (refer to Section 2.3,Clocking Choices) are appropriate for the level provided on RdType (electrically high is a logical 1: aninstruction read; electrically low is a logical 0: a data read)

1.2 CONNECTION TO SYSTEM UNDER TEST

No companion hardware probe adapter is available for use with this software-only product.

It is the responsibility of the user to provide the means in the system under test (SUT) to achieveproper attachment of the logic analyzer probes. Refer to Appendix A, Channel Assignments, fordetailed information concerning connection of SUT signals and logic analyzer probes.

1.3 INSTALLING DISASSEMBLER AND SUPPORT SOFTWARE

Install the new disassembly support software on the logic analyzer in the same manner that othersoftware is installed on a Windows95 system: insert the disassembly support disk in the floppy diskdrive (disk label facing forward on analyzers having a built-in display; disk label facing to the righton other analyzers); click on the Windows95 Start button; choose Settings...; choose Control Panel;double-click on Add/Remove Programs; click on Install... under the Install/Uninstall tab; thenfollow the on-screen directions.

Prior to installing the disassembly support software, remove any extant version of that same software(e.g., any earlier version). When in Add/Remove Programs, review the list of programs alreadypresent in the system. If a version of the support software already exists, select it and click onRemove. (Note that removal should be performed only after first exiting the TLA700 systemapplication, in case the application is using any of the support files.) Once removal is complete,continue on to install the new software then as instructed in the preceding paragraph.

1.4 ABOUT THIS MANUAL

This manual is organized as follows:

Section 1: Introduction - Presents information on: installing disassembler software and manualorganization.

Section 2: Configuring The Acquisition Module - Provides information on setting up theacquisition module in preparation for data acquisition and disassembly display.

Section 3: Disassembly Display Of Data - Information is provided on how to acquire data andview it, principally using the disassembly display.

Section 4: Acquisition Clocking Choices - A discussion of the acquisition clocking choicesavailable and their uses.

Appendix A: Channel Assignments

Appendix B: Software Warranty And Service

Appendix C: History Of Revisions

Introduction

1-2 R7000D/E Disassembler Manual

The disassembler software automatically defines the channel groups for the signals of the processor.The channel groups defined are: SysAD, SysAD-Hi, A, Address, Control, TcLine, TcWord, TcVM,XRAS, Intr, TcCtrl, TcCtrl2, Chk, Mode, JTAG, Clk and Misc (the XRAS and JTAG groups aredefined only for R7000E support). Refer to the LA module Setup window to view or change thechannel assignments; also refer to the channel assignment tables in Appendix A, Channel Assignments.

When probing RM527x systems (which do not have these RM7000-specific signals: IntB9,IntB8, IntB7, IntB6, RdType, TcLine17 and TcLine16), it is recommended that the probes forthose signals be connected to electrically constant high or low levels (or are kept disconnected,which is equivalent to being connected to an electrically high level). For example with theIntB9..6 probes held high and the TcLine17..16 probes held low, there will be minimal impactwith the display of the other signals’ values in the Intr and TcLine channel groups.

Proper operation of the disassembler generally requires that the definition of the SysAD-Hi, A,Address, Control, TcLine, TcWord, TcVM and XRAS groups not be changed and the channels ofthese groups not be transferred to other groups or swapped with channels of other groups. (The lastfour groups are relevant to the R7000E probing support product only.)

This section provides information on setting up the acquisition module in preparation for dataacquisition and disassembly display.

Information is provided on the following:

w loading support software

w channel groupings

w clocking choices

w symbols and symbol tables

w triggering

2.1 LOADING SUPPORT SOFTWARE

Assuming the software has already been installed on the analyzer (i.e., copied from floppy disk to thehard drive of the system; refer to Section 1.2, Installing Disassembler And Support Software), thesoftware can then be loaded into the acquisition module.

In order to get ready to perform a disassembly acquisition the support software must be loaded intothe acquisition module: select Load Support Package... from the File menu and select R7000E (foundin the C:\Program Files\TLA700\Supports folder).

Another way to get ready to perform a disassembly acquisition is to load a previously-saved systemsetup file: select Load System... from the File menu, and then select the setup file (.tla file extension)desired.

With the load performed, the LA module Setup window will show relevant acquisition-relatedinformation concerning: what channel groupings have been setup; the clocking mode; the memorydepth; etc. Changes to these parameters can be made also via the LA module Setup window.

Figure 2.1 shows the LA module Setup window.

2.2 CHANNEL GROUPINGS

2. CONFIGURING THE ACQUISITION MODULE


Figure 2.1 - LA Module Setup Window (R7000D Support)

Additional groups can be defined and displayed and the nonessential groups listed above can bechanged or removed as desired. Note that with the exception of the specific channels in the requiredgroups, a channel need not belong to a group.

Changes to the default values of threshold voltage (1.5 V: viewable under Set Thresholds... on theLA module Setup window) of any of the channels of the four required groups will likely adverselyaffect disassembly acquisition.

2.3 CLOCKING CHOICES

The Clocking selection on the LA module Setup window can be used to set clocking choices tocontrol data acquisition. The disassembler software provides a Custom clocking selection which isthe default setup.

In addition to Custom clocking, Internal, External and Advanced clocking can be selected. Theseclocking choices are not used for disassembly acquisition; refer to Section 4, Acquisition ClockingChoices, for an explanation of their use.

The Acquire selection on the LA module Setup window allows the choice of Normal, Blocks andGlitches (for Internal clocking only) modes of acquisition. For disassembly acquisition, Acquireshould be set to Normal. (Blocks mode, used in conjunction with a user-specified trigger program,may also be useful in certain situations.)

A collection of Setup/Hold Window fields and five Custom Options fields exist under the (clocking)Options selection of the LA module Setup window as described in the following. Refer to Figure 2.2.Note that Custom acquisitions are performed using the rising edge of CK3 (SysClk).

Configuring The Acquisition Module


Figure 2.2 - LA Module Setup Window Clocking Options (R7000D Support)

2.3.1 Clocking Delay

In order to insure reliable acquisition of bus signals in the face of signal skew, the timing (placement)of the clock edge can be effectively advanced or delayed internally by the analyzer before being usedto sample the signals.

Figure 2.2 shows that the Custom Options window provides means to set the setup time associatedwith each defined channel group of the disassembler support. Note that while a unique setup timerelative to the clock source’s clock edge can be defined for each separate group, a shift in the apparentoverall time of occurrence of the clock edge requires that the setup times for all groups be setuniformly to the same value.

The setup time shown under the Setup/Hold Window column is initially the “Support PackageDefault”, which is a setup time of 2 ns. For such a setup time, the signals being acquired by the logicanalyzer must be stable 2 ns before the clock source’s edge (2 ns setup time) and must remain stableuntil the clock edge has occurred (0 ns hold time); the signals must exhibit a 2 ns window-of-stabilitywhich ends with the occurrence of the clock edge. This default value is a clocking delay (change inthe acquisition sample point from the edge of the clock source) of 0 ns.

If a non-zero clocking delay is required, the setup times of all groups are changed appropriately. Forexample, if a clocking delay of 1 ns is required, the acquisition window-of-stability must be delayedin time by 1 ns. This is accomplished by changing the setup time from 2 ns to 1 ns (with acorresponding change in the hold time from 0 ns to 1 ns).



The setup time for a particular group can be accessed by clicking in the box corresponding to thatgroup under the Setup/Hold Window column. Setup time values ranging from 8.5 ns (an advance of6.5 ns compared to the default setup time of 2 ns) to -7 ns (a delay of 9 ns compared to the default) inincrements of 0.5 ns can be specified. Figure 2.2 shows the case where the setup time for the SysADgroup has been changed to 1 ns.

Note that the extent of the window-of-stability remains 2 ns no matter what the setup time chosen is.Note also again that it should be verified that all groups are set to have the same setup time value.

2.3.2 Acquisition Field

With Normal (the default selection), acquisition of the processor's bus activity is controlled (at least inpart) by the three tertiary cache (TC) control signals (TcTCEB, TcMatch and TcClrB). Additionally,four basic qualifiers are also used (ValidInB, ValidOutB, SysCmd8 and SysCmd6; refer toSection A.2.5, Control Group). With this field choice, acquisition of both cached and noncachedmemory transactions occurs.

Note that one additional acquisition qualifier is also utilized, the RdType signal.

With a selection of Cached Only, the same qualifiers are used and acquisition of only cached memorytransactions occurs; no acquisition of noncached memory transactions occurs.

With selection of NonCached Only, the same qualifiers are used and acquisition of only noncachedmemory transactions occurs; no acquisition of cached memory transactions occurs.

Note that for this selection as well as for the Normal and Cached Only selections, acquisitionof cache housekeeping bus cycles is controlled (only) by the setting of the MiscellaneousCycles field (refer to Section 2.3.6, Miscellaneous Cycles Field).

With selection of TC Ctrls Ignored, the three tertiary cache control signals mentioned above areignored when bus activity is being acquired; acquisition is controlled by the five other qualifiers.

Note that the values of any TcTCEB, TcMatch and TcClrB bus signals are still acquired; thesignals are simply not used to direct the acquisition process.

The TC Ctrls Ignored selection is appropriate for systems implemented without an external cache, forwhich there would be no defined TcTCEB, TcMatch or TcClrB signals. (Alternatively, such systemscould be probed using the Normal, Cached Only, or NonCached Only selections if the logicanalyzer's TcTCEB and TcClrB qualifier inputs are held inactive (logically 1, electrically high).)

With selection of Acquire All Cycles, every bus cycle is unconditionally acquired; in this mode noneof the qualifiers influence the acquisition of bus activity. This selection may be useful when gaugingprocessor bus utilization or system memory bandwidth. It is also useful for acquiring bus activity forview using the timing display to see a cycle-by-cycle (synchronous) display of the behavior of the bus(see Section 3.6.2, Timing Display). With this selection the settings of the Inst Read Accesses, DataRead Accesses, Write Accesses and Miscellaneous Cycles clock options are ignored (refer toSections 2.3.3 through 2.3.6).

Note that various special bus transactions and cycles which may be acquired in this mode(such as write "preissue" transactions (refer to Section 3.4.12, Write Reissues Field), nonissuerequest cycles (refer to Section 2.3.2.1, Request Cycle Acquisition, and Section 2.3.2.2, ProcessorNonissue Behavior) and data wait and idle cycles) are displayed by the disassembler only whenusing the Hardware display format (see Section 3.4.1.1, Hardware Display Format) and onlywhen the H/W Cycles Displayed field is set to As Acquired (see Section 3.4.6, H/W CyclesDisplayed Field).



Figure 3.4 shows the manner in which acquired special cycles are displayed under thedisassembler's Hardware format with As Acquired selected in the H/W Cycles Displayedfield.

2.3.2.1 Request Cycle Acquisition -

When a memory transaction occurs, superfluous processor request cycles are not acquired (unless theAcquisition field is set to Acquire All Cycles). A single sample is acquired of the processor'smemory request seen on the bus, even if the request is repeated for more than one bus cycle (e.g.,while waiting for the memory system to signal that it is ready to accept the request). The last requestcycle on the bus (if it is followed by one or more data cycles) is termed the "issue" cycle; anypreceding request cycles are termed "nonissue" cycles. It is the last request cycle (which is usually theissue cycle) which is acquired.

In the unusual case of a series of processor request nonissue cycles which are not followed byan issue request cycle (such as when a processor read or write request is being held off bydeassertion of RdRdyB or WrRdyB and then the processor's bus interface control logic grantsbus access to an external write transaction), the last of the request cycles will be acquired eventhough it is not an issue cycle; it will be labeled by the disassembler as a "NONISSUE" cycle.

2.3.2.2 Processor Nonissue Behavior -

When the RM7000 or RM527x processor outputs nonissue request cycles associated with a noncacheread or write transaction, such nonissue cycles contain the same information (SysCmd, SysAD, etc.)as is found in the issue cycle of the noncache transaction.

When the processor outputs nonissue cache read or write request cycles, such nonissue cycles do notcontain the same information found in the issue cycle of the cache transaction. Specifically, nocache-related information or control signals are asserted during the nonissue cycles; only in the issuecycle are the cache-related information and control signals valid.

Note that care should be exercised when using the R7000D_Ctrl (or R7000E_Ctrl) symbol table tointerpret the activity of the Control group (as in a State display; refer to Section 2.4, Symbols AndSymbol Tables), since nonissue request cycles of cached transactions will appear to be noncachedtransaction request cycles.

2.3.3 Inst Read Accesses Field

With Acquire (the default selection), acquisition of all CPU instruction read transactions occurs. WithDo Not Acquire, no acquisition of CPU instruction read transactions occurs.

This holds when probing an RM7000 system along with the RdType signal. If instead asurrogate RdType level is provided to the RdType probe (as when probing an RM527xsystem), the setting of this field (as well as that of the Data Read Accesses field (refer toSection 2.3.4, Data Read Accesses Field)) should be selected appropriately.

For example, with RdType constantly high (possibly via the probe being disconnected), theInst Read Accesses field can be used to control acquisition of all read transactions: when setto Acquire, all read transactions will be acquired; when set to Do Not Acquire, no readtransactions will be acquired. The setting of the Data Read Accesses field is immaterial here,since RdType is never low; Do Not Acquire can be selected.

Note that the setting of this field is ignored when the Acquisition field is set to Acquire All Cycles(see Section 2.3.2, Acquisition Field).



2.3.4 Data Read Accesses Field

With Acquire (the default selection), acquisition of all CPU data read transactions occurs. With DoNot Acquire, no acquisition of CPU data read transactions occurs.

This holds when probing an RM7000 system along with the RdType signal; refer to thediscussion above in Section 2.3.3, Inst Read Accesses Field.

Note that the setting of this field is ignored when the Acquisition field is set to Acquire All Cycles(see Section 2.3.2, Acquisition Field).

2.3.5 Write Accesses Field

With Acquire (the default selection), acquisition of all CPU write transactions occurs.

With Do Not Acquire, no acquisition of CPU write transactions occurs.

Note that acquisition of external write (interrupt assertion) transactions always takes place.

Note that the setting of this field has no effect when the Acquisition field is set to Acquire All Cycles(see Section 2.3.2, Acquisition Field).

2.3.6 Miscellaneous Cycles Field

When the Acquisition field is set to Normal, Cached Only or NonCached Only, this field controlsacquisition of cache housekeeping bus cycles: Cache Line Invalidate (such as may occurindependently on the bus or as part of a CPU cache read miss transaction with bus error); Cache LineUpdate (such as occurs as part of a CPU read miss transaction without bus error); Cache Probe; orCache Block Clear activities. With Acquire (the default selection) such cache housekeeping cycles areacquired; with Do Not Acquire such cache housekeeping cycles are not acquired.

Note that Cache Line Invalidate and Cache Line Update actions which occur together with(i.e., in the same cycle as) the transmission of external response data (during CPU cache readmiss transactions) are not considered to be cache housekeeping cycles.

Note also that in addition to acquisition of a Cache Line Invalidate, Cache Line Update orCache Probe housekeeping cycle, the two cycles following (if they are bus idle cycles) are alsoacquired. Such acquisition is to permit the tag information associated with a Cache Probe tobe acquired; since the logic analyzer bus activity acquisition process (the clocking statemachine (CSM)) cannot distinguish between a Cache Probe and a Cache Line Invalidate orUpdate cycle (since the acquisition qualifiers do not include a TcCWEB signal), the extracycles are always obtained.

Note that the setting of this field has no effect when the Acquisition field is set to Acquire All Cycles(see Section 2.3.2, Acquisition Field).



2.4 SYMBOLS AND SYMBOL TABLES

Symbols can be used to represent specific pattern values of a channel group as well as ranges ofvalues. Symbol tables can be used for symbolic display of channel group information in state anddisassembly displays and as a help in specifying trigger conditions.

The disassembler software provides a pattern type symbol table named R7000D_Ctrl (orR7000E_Ctrl) for use in displaying the Control channel group during state display; see Table 2-1. Inthe table the Control group's seventeen (17) channels are presented most significant (left) to leastsignificant (right): RdType, ResetB, ValidInB, ValidOutB, ScTCEB, ScTDEB, ScCWE0B, ScClrB,SysCmd8, SysCmd7, SysCmd6, SysCmd5, SysCmd4, SysCmd3, SysCmd2, SysCmd1 andSysCmd0 (refer to Section A.2.5, Control Group).

Note when probing RM527x systems or RM7000 systems without the RdType signal, thatdisplay of the Control group’s value by use of the Control symbol table may be affected bythe RdType bit value.

The disassembler software provides a pattern type symbol table named R7000D_Intr (orR7000E_Intr) for use in displaying the Intr channel group during disassembly and state display andfor specifying trigger conditions; see Table 2-2. In the table the Intr group's eleven (11) channels arepresented most significant (left) to least significant (right): NMIB, IntB9, IntB8, IntB7, IntB6, IntB5,IntB4, IntB3, IntB2, IntB1, and IntB0 (refer to Section A.2.9, Intr Group).

Note when probing RM527x systems, that display of the Intr group’s value by use of the Intrsymbol table may be affected by the IntB9..6 bit values.

Note that the symbols are shown in the tables in this document in the order in which they exist in thesymbol tables of the logic analyzer. Note also that when a symbol table is used for display purposes,it is searched beginning at the top of the table; the first match encountered determines which symbolis displayed. Symbols suffixed with "*" in the table are thus never expected to be matched duringdisplay and are available and used (only) for defining trigger conditions.



Table 2.1 - Control Group Symbol Table (R7000D_Ctrl, R7000E_Ctrl)



Read single datum request, 8 bytesX 110X XXX0 0001 1111RdReq8Bytes




Read single datum request, 4 bytes, of any kindX 110X XXX0 0001 1011RdReq4BytesAny

Instruction read single datum request, 4 bytes1 110X XXX0 0001 1011InstRdReq4Bytes

Data read single datum request, 4 bytes0 110X XXX0 0001 1011DataRdReq4Bytes



Read single datum request, 1 byteX 110X XXX0 0001 1000RdReq1Byte

Read block request of any kindX 110X XXX0 0001 0XXXRdBlkReqAny*

Instruction read block request1 110X XXX0 0001 0XXXInstRdBlkReq

Data read block request0 110X XXX0 0001 0XXXDataRdBlkReq

External request or data cycleX 101X XXXX XXXX XXXXExtAny*

External write or response data or EOD, ok or w/ ERRX 101X XXX1 XXXX XXXXExtDataAny*

External write or response data or EOD, w/ ERRX 101X XXX1 XX1X XXXXExtDataErrAny*

External write or response data or EOD, okX 101X XXX1 XX0X XXXXExtDataOkAny*

External write data (not EOD), ok or w/ ERRX 101X XXX1 X1XX XXXXExtWriteDataAny*

External write data or EOD, w/ ERRX 101X XXX1 X11X XXXXExtWriteErrAny*

External response data (not EOD), ok or w/ ERRX 101X XXX1 X0XX XXXXExtRespDataAny*

External write data or EOD, w/ ERRX 101X XXX1 X01X XXXXExtRespErrAny*

External write data (not EOD) w/ ERRX 101X XXX1 111X XXXXExtWriteDataErr

External write data (not EOD) okX 101X XXX1 110X XXXXExtWriteData

External response data (not EOD) w/ ERRX 1011 XXX1 101X XXXXExtRespDataErr

External response data (not EOD) ok X 1011 XXX1 100X XXXXExtRespData

External write EOD w/ ERRX 101X XXX1 011X XXXXExtWriteEodErr

External write EOD ok X 101X XXX1 010X XXXXExtWriteEod

External response EOD w/ ERRX 1011 XXX1 001X XXXXExtRespEodErr

External response EOD okX 1011 XXX1 000X XXXXExtRespEod

External request of any kindX 101X XXX0 XXXX XXXXExtReqAny*

External null requestX 101X XXX0 0110 0XXXExtNullReq

External write requestX 101X XXX0 0101 1XXXExtWriteReq

Cache Probe cycleX 1110 011X XXXX XXXXCacheProbe

Cache Line Update cycleX 1110 101X XXXX XXXXCacheLineUpdate

Cache Line Invalidate cycleX 1110 001X XXXX XXXXCacheLineInval

Cache Block Clear cycleX 111X XX0X XXXX XXXXCacheBlockClear

No bus activity, per ValidInB, ValidOutB, TcTCEB and TcClrBX 1111 XX1X XXXX XXXX-BusIdle-

ValidInB and ValidOutB asserted in the same bus cycleX 100X XXXX XXXX XXXX-BusFault-

ResetX 0XXX XXXX XXXX XXXX-Reset-

MeaningControl Group ValueSymbol

Table 2.1 - Control Group Symbol Table (Continued)



Any bus cycle in which ResetB is not assertedX 1XXX XXXX XXXX XXXXAnyNonReset*

Processor-issued cycle of any kindX 110X XXXX XXXX XXXXCpuAny*

Processor write data cycle of any kindX 1101 XXX1 X1XX XXXXWrDataAny*

Processor write data or EOD w/ ERRX 1101 XXX1 X11X XXXXWrDataErrAny*

Processor write data or EOD okX 1101 XXX1 X10X XXXXWrDataOkAny*

Processor write data (not EOD) w/ ERRX 1101 XXX1 111X XXXXWrDataErr

Processor write data (not EOD) okX 1101 XXX1 110X XXXXWrData

Processor write EOD w/ ERRX 1101 XXX1 011X XXXXWrEodErr

Processor write EOD okX 1101 XXX1 010X XXXXWrEod

Processor request of any kindX 110X XXX0 XXXX XXXXCpuReqAny*

Processor noncache request of any kindX 1101 XXX0 XXXX XXXXCpuReqNoncacheAny*

Processor cache request of any kindX 1100 XXX0 XXXX XXXXCpuReqCacheAny*

Processor write request of any kindX 110X XXX0 0101 XXXXWrReqAny*

Processor write single datum request of any sizeX 110X XXX0 0101 1XXXWrReqSingleAny*

Processor write single datum request, 8 bytesX 110X XXX0 0101 1111WrReq8Bytes



Processor write single datum request, 5 bytesX 110X XXX0 0101 1100WrReq5bytes




Processor write single datum request, 1 byteX 110X XXX0 0101 1000WrReq1Byte

Processor write block requestX 110X XXX0 0101 0XXXWrBlkReq

Read request of any kindX 110X XXX0 0001 XXXXRdReqAny*

Read single datum request of any sizeX 110X XXX0 0001 1XXXRdReqSingleAny*

MeaningControl Group ValueSymbol

Table 2.2 - Intr Group Symbol Table (R7000D_Intr, R7000E_Intr)



IntB0 asserted; other interrupt signals possibly asserted alsoXXX XXXX XXX0 Int0+

IntB1 asserted; other interrupt signals possibly asserted alsoXXX XXXX XX0X Int1+

IntB2 asserted; other interrupt signals possibly asserted alsoXXX XXXX X0XX Int2+

IntB3 asserted; other interrupt signals possibly asserted alsoXXX XXXX 0XXX Int3+

IntB4 asserted; other interrupt signals possibly asserted alsoXXX XXX0 XXXX Int4+

IntB5 asserted; other interrupt signals possibly asserted alsoXXX XX0X XXXX Int5+

IntB6 asserted; other interrupt signals possibly asserted alsoXXX X0XX XXXX Int6+

IntB7 asserted; other interrupt signals possibly asserted alsoXXX 0XXX XXXX Int7+

IntB8 asserted; other interrupt signals possibly asserted alsoXX0 XXXX XXXX Int8+

IntB9 asserted; other interrupt signals possibly asserted alsoX0X XXXX XXXX Int9+

NMIB asserted; other interrupt signals possibly asserted also0XX XXXX XXXX NMI+

NMIB alone asserted011 1111 1111 NMI

IntB9 alone asserted101 1111 1111 Int9










No interrupt of any kind asserted111 1111 1111 -

MeaningIntr Group ValueSymbol

2.5 TRIGGERING

Refer to the Setup subsection of the Reference section of the Analyzer Manual for general informationconcerning triggering and trigger programs.

Trigger programs can check the values of the various defined groups as well as the values ofindividual probe channels. Note that the groups’ values used are those which have been acquiredfrom the processor (not to be confused with disassembler-synthesized values displayed for some ofthe groups, as explained in Section 3.3, Understanding The Disassembly Display).

Beyond basic logical equality or non-equality checks, the trigger program can employ “rangematching” to determine whether the value of a group is arithmetically greater than (or equal to), orless than (or equal to) a specified value. Range matching would usually be of interest for the SysADlines which specify the address of the memory access. The Address group is composed of the lower32 SysAD lines; the SysAD-Hi group is composed of the upper 32 SysAD lines. Use of either of thesegroups allows range matching to be performed on the lower (or upper) SysAD lines.

The SysAD group, representing all 64 SysAD lines, has been defined to allow range matching to becarried out on the complete (64-bit) SysAD value. (This group is not used by the disassembler and isnot required to be defined; it is redundant in the sense that between the SysAD-Hi and Addressgroups (which are used by the disassembler) all SysAD lines already have group representation.)

Note that the ordering of the analyzer channels for the purposes of arithmetic range matchingis as follows: C3, C2, C1, C0, E3, E2, E1, E0, A3, A2, D3, D2, A1, A0, D1, D0, Q3, Q2, Q1, Q0,CK3, CK2, CK1 and CK0 (where, for example, C3 represents the eight channels of the C3probe, #7..0; Q3 represents the Qualifier #3 channel, and CK3 represents the Clock #3 channel(note that all channels, including Clocks, acquire data)). For modules of widths other than136-channels the channels which are not implemented are ignored (for example, for a102-channel module E3, E2, E1, E0, Q3 and Q2 are not present).

When performing a disassembly (or other) acquisition, be sure to set the Trigger Pos setting on theLA module Trigger window as desired.

The most common use of triggering in conjunction with disassembly acquisition and display is tocontrol when the start of data acquisition occurs (e.g., following the end of ResetB assertion, or after aprocessor request to read or write a particular memory location). Use of the triggering mechanism to"filter out" certain bus cycles from acquisition memory (e.g., to retain only write request bus cycles)results in "gaps" in the acquisition; the disassembly display will likely be adversely affected.



This page has been left blank intentionally.



3. DISASSEMBLY DISPLAY OF DATAInformation is provided here on how to acquire data and view it, principally using the disassemblydisplay. The following are discussed:

w acquiring data

w fundamental disassembly issues

w understanding the disassembly display

w disassembly format definition overlay

w marking samples

w alternative data displays

Note that some of the logic analyzer screen displays presented in this section were obtained fromR5000E disassembler product documentation; they are applicable to describing RM7000 (andRM527x) probing support since the R5000 and RM7000 (and RM527x) buses (those not configured toperform multiple oustanding reads (MORs)) and disassemblers function similarly.

3.1 ACQUIRING DATA

After loading the disassembler support software, choosing Custom clocking and possibly settingvarious clocking options in the LA module Setup window, and possibly configuring a triggerprogram in the LA module Trigger window, data can be acquired. Click on the Run button in themain window toolbar to start acquisition. Click on the same button when labeled Stop to stopacquisition if a trigger did not occur.

If a previously-saved module (or system) setup file had been loaded which had a disassembly listingdata window displayed (as discussed in Section 2.1, Loading Support Software), the data window willshow the new bus activity when acquired as a disassembly display. (Alternatively, refer to theinstructions in the Display subsection of the Reference section of the Analyzer Manual concerninghow to create a New Data Window.) See for example Figure 3.1.

3.2 FUNDAMENTAL DISASSEMBLY ISSUES

The behavior of the RM7000 and RM527x processors places constraints upon the functionality of thedisassembler software, as now discussed.

3.2.1 Processor Bus Addresses

The processor translates the virtual addresses of the executing software into physical addresses whenplacing memory access requests on the processor bus. Therefore, all addresses seen by thedisassembler are physical addresses. This affects the reliability of the calculation of PC-relativeaddresses, as well as the way symbol tables may be defined for use with the R7000D/E Addressgroup.


Figure 3.1 - Example Disassembly Display

3.2.1.1 PC-With-Displacement Calculations -

The disassembler displays PC-relative branch instructions with absolute addresses calculated fromthe current address of the program counter (PC). Since the disassembler sees the current address ofthe PC as a physical address, the calculated absolute branch address will also be a physical address.This means that the displayed branch address may not match the processor software virtual branchaddress.

It is possible that incorrect physical branch addresses may be calculated and displayed when programexecution crosses page boundaries and the virtual-to-physical address mapping changes.

In cases where the sum of the current PC and the branch offset would be expected to cause a carryfrom the low-order 32 bits of the physical address into higher-order physical address bits, no change(no carry) takes place in any higher-order bits calculated and displayed by the disassembler.

3.2.1.2 Address Group Symbol Table -

It is possible to build a range-type symbol table for use with the R7000D/E Address group usingvirtual (rather than physical) addresses if all address symbols are defined with a virtual address thatis relative to the origin of the code and if the code is present in memory as one contiguous block.

Disassembly Display Of Data


Figure 3.1 shows the results of using a demonstration range-type symbol table to display theR7000D/E Address group.

Note that when the R7000D/E Address group is displayed symbolically, similar symbolic addressesare automatically utilized in the display of the Mnemonics information of the disassembly display.

Refer to Section 3.3, Understanding The Disassembly Display, for additional information aboutdisplaying groups. Also refer to the Display subsection of the Reference section of the Analyzermanual for information concerning the use of symbols and symbol tables.

3.2.2 Instruction/Data Block Read Ambiguity

When probing RM7000 systems with RdType available (refer to Section 3.4.14, Processor Field), eachmemory read transaction is labeled by RdType as being either an instruction fetch or a data read;there is no read-type ambiguity. However, when probing other systems (RM7000 systems withRdType unavailable, or RM527x systems), the disassembler cannot differentiate block read instruc-tion information and read data information.

When probing such systems information fetched in block read accesses matching the size of theinstruction cache line fill size will be disassembled as instructions by default, unless the read is ineither of the data block read area ranges specified by the Data Area1 Begin, Data Area1 Size, DataArea2 Begin and Data Area2 Size fields of the disassembly format definition overlay (refer toSections 3.4.19 through 3.4.22).

Also in such cases the disassembler assumes that non-block word (4 byte) reads that are word alignedand whose addresses are within either of the uncached instruction fetch area address ranges specifiedby the Uncached Area1 Begin, Uncached Area1 Size, Uncached Area2 Begin and Uncached Area2Size fields of the disassembly format definition overlay (refer to Sections 3.4.15 through 3.4.18) areinstruction accesses; the information fetched in such read accesses will also be disassembled bydefault.

The disassembler provides a sample-marking capability to allow assumed-instruction information tobe manually marked and treated as data, and to allow assumed-data accesses to be manually markedand disassembled as instructions (refer to Section 3.5, Marking Samples).

Note that the disassembler control fields described are ignored and the cycle-marking facility is notfunctional when probing RM7000 systems with RdType available.

3.2.3 Memory Access Caching

No bus traffic results from instruction and data accesses which are handled by the on-chip instructionand data caches of the processor; the disassembler sees no evidence of such accesses.

Running from an uncached region of memory allows all information reads to be monitored and theinstruction execution trace to be followed.

3.2.4 Subblock Data Transfer Order

The RM7000 and RM527x processors expect information provided in response to block reads to bereturned in "subblock order" (sequential ordering is used for block write data items). The order of theread items will not be the same as with conventional (sequential) ordering, except when the blockread request address has zeros in at least the low five (5) bit positions.

With the display mode set to Hardware, block read information cycles are displayed in the sameorder as they were transferred across the bus. In the other display modes of Software, Control Flowand Subroutine, information from instruction (or assumed-instruction) block reads is rearranged bythe disassembler to be in sequential address order. Refer to Section 3.4.1, Display Mode Field.



3.2.5 Tracing Control Flow

The processor generally gives no indication of when branches or jumps are taken. The disassemblerdisassembles all instructions (or assumed-instructions) from instruction block reads without knowingwhether all instructions of the block were actually executed.

3.3 UNDERSTANDING THE DISASSEMBLY DISPLAY

Refer again to Figure 3.1 for an example disassembly display.

The address of the memory location being fetched will appear under the R7000D Address column (orunder the R7000E Address in the case of the R7000E support product). The contents of the memorylocation and the disassembled instruction mnemonic display of the memory location contents willappear under the R7000D Data-Mnemonics column.

It is important to understand that the disassembler controls not only what is displayed under theR7000D Data-Mnemonics column but also what is displayed under the R7000D Address column. Infact, any column named "R7000D..." (such as R7000D SysAD-Hi, R7000D Address,R7000D Data-Mnemonics, etc.) presents information synthesized by the disassembly software; this isas opposed to columns having names without "R7000D..." (such as SysAD-Hi, Address, Intr, etc.)which can also be displayed and which present the raw data as it was acquired.

Display of both types of information (synthesized and raw) can be enabled in one display at the sametime as desired. Note that there is no "raw" version of the information presented under theR7000D Data-Mnemonics column. Also note that for example no "R7000D..." version of Intr can bedisplayed because the disassembler does not synthesize a version of that and some of the othergroups. A listing display consisting of just the raw groups' data is termed a State display; nodisassembly interpretation or synthetic group values are involved.

The disassembly display presents information best formatted to facilitate understanding of theprocessor's instruction execution trace, rather than to demonstrate the actual activity of the bus ineach acquired bus cycle. (For the latter, use of a state or timing display may be more appropriate.)This should be apparent upon examining a disassembly display when it is remembered that at leasttwo bus cycles are required for any memory transaction: a request cycle and at least one data cycle.

When the processor fetches instructions, the acquisition module first captures the memory readrequest cycle (from which the disassembler displays the instruction location under theR7000D Address column) and then the read information cycle (from which the disassembler displaysthe instruction location's contents and mnemonics under the R7000D Data-Mnemonics column).Each bus cycle does not transmit both address and data (instruction) information, as could beincorrectly inferred from casual examination of a disassembly display.

Recall too from Section 3.2.4, Subblock Data Transfer Order, that instruction (orassumed-instruction) block fetches may be reordered before being displayed (except when inHardware display mode); this is another manner in which the disassembly display may notreflect the actual behavior of the processor bus.

Note again that while synthesized data is presented under columns labeled such asR7000D SysAD-Hi, R7000D A and R7000D Address, the actual (raw: as acquired) values of theSysAD-Hi, A and Address groups may be completely different. For example, the A group is actuallycomposed of channels handling control signals; such control signals do not communicate addressinformation on the bus, which is what is displayed under the R7000D A column. (Refer toAppendix A, Channel Assignments).



Display of the R7000D A group may be enabled in order to view any upper bits of the physicaladdress emitted during request cycles, the lower 32 bits of which are displayed under theR7000D Address group column. Display of the R7000D SysAD-Hi group may be enabled instead toview all upper address bits. This permits viewing of any upper physical address bits as with theR7000D A group display, and the portion of the virtual address present on SysAD57..56 is alsoviewable.

3.4 DISASSEMBLY FORMAT DEFINITION OVERLAY

The Disassembly properties page, also referred to as the disassembly format definition overlay,provides a number of fields whose settings control the operation of the disassembler and the displayof disassembled data. The fields of the overlay are described in the following; see Figure 3.2.

Note that unless the settings of the Regs-ByteOrder and External Cache fields are set in accord withthe characteristics of the system under test being probed, the disassembly display will likely beincorrect.

Note also that the other fields, including (but not limited to) the Display Mode field and the H/WCycles field, must be set correctly since they may strongly influence the display produced.

3.4.1 Display Mode Field

Selections include Hardware (the default), Software, Control Flow and Subroutine:

- Hardware display format displays acquired cycles and instruction mnemonics in the order oftheir occurrence.

- Software display format does not display request cycles and data (non-instruction) read andwrite cycles; the result is similar to an assembly language listing.

- Control Flow display format displays only instructions which are capable of changing the flowof execution of the processor.

- Subroutine display format displays only subroutine calls, returns, system calls, breaks and trap-on-condition instructions.

Each selection in the list presents a subset of the types of displayed cycles of the preceding selection.



Figure 3.2 - Disassembly Properties Page (R7000D Support)

3.4.1.1 Hardware Display Format -

With the Hardware display format the contents of all acquired bus cycles are displayed (see howeverSection 3.4.7, H/W Cycles Field). Instruction block reads are decoded and displayed in mnemonic formin the order in which they occurred on the bus. Memory access requests are displayed and labeledwith cycle-descriptive information. Data cycles are likewise labeled.

Note that instruction fetch read cycles for which SysCmd5 is high (1; data error) are not disassembledas instructions.

Note that as explained in Section 3.2.5, Tracing Control Flow, the disassembler has no way ofdetermining whether all instructions decoded from instruction reads have actually been executed.

Figure 3.3 shows an example of the Hardware display format.



Figure 3.3 - Example Of Hardware Display Format

3.4.1.2 Software Display Format -

With the Software display format only instruction fetches are displayed; memory access requestcycles and read data cycles and write data cycles are not displayed. Instruction reads are decodedand displayed in mnemonic form, and the instructions from block fetches are reordered intosequential ascending address order within each block read.

This reordered display will match the true-order display (e.g., as would be seen under the Hardwaredisplay format) if the low five (5) address bits of the read request address are zeros.

If reordering occurs, the software-generated values displayed under the SysAD-Hi, A, Address andData-Mnemonics groups' columns are reordered. (Control group values, if enabled for display, arealso reordered; TcLine and TcWord group values, if enabled for display, are reordered in the case ofCPU cache read transactions. For further information refer to Section A.2, Channel Groupings.) Notethat the sequence numbers, the values of other groups (such as Intr) and the timestamp values are notreordered.

Note that instruction fetch read cycles for which SysCmd5 is high (1; data error) are notdisassembled. Note also that a single read cycle flagged with a data error in a block read results innon-display of the entire block.



Note that as explained in Section 3.2.5, Tracing Control Flow, the disassembler has no way ofdetermining whether all instructions decoded from instruction reads and displayed have actuallybeen executed.

Figure 3.1 shows an example of Software display format.

3.4.1.3 Control Flow Display Format -

The Control Flow display format is similar to the Software display format except that onlyinstructions capable of changing the execution flow of the processor are displayed. Such instructionsare:

BCzF BGEZAL BLTZALL JALR TGEU

BCzFL BGEZALL BLTZL JR TLT

BCzT BGTZ BNE SYSCALL TLTI

BCzTL BGTZL BNEL TEQ TLTIU

BEQ BLEZ BREAK TEQI TLTU

BEQL BLEZL ERET TGE TNE

BEQZ BLTZ J TGEI TNEI

BGEZL BLTZAL JAL TGEIU WAIT

Note that as explained in Section 3.2.5, Tracing Control Flow, the disassembler has no way ofdetermining whether all instructions decoded from instruction (or assumed instruction) cache lineblock reads and displayed have actually been executed.

3.4.1.4 Subroutine Display Format -

The Subroutine display format is similar to the Control Flow display format except that onlysubroutine calls, returns, system calls, breaks and trap on condition instructions are displayed. Suchinstructions are:

BGEZAL ERET TEQ TGEU TNE

BGEZALL JAL TEQI TLT TNEI

BLTZAL JALR TGE TLTI WAIT

BLTZALL JR R31 TGEI TLTIU

BREAK SYSCALL TGEIU TLTU

Note that as explained in Section 3.2.5, Tracing Control Flow, the disassembler has no way ofdetermining whether all instructions decoded from instruction (or assumed instruction) cache lineblock reads and displayed have actually been executed.



3.4.2 Disassemble Across Gaps Field

Selections include No (the default) and Yes.

A gap occurs when the trigger program directs that a sample (bus cycle) not be stored in acquisitionmemory. When the default trigger program is used, all accepted samples (as determined by thecurrent settings of the clock options fields in the Clock setup menu) are stored in acquisition memory,with no gaps resulting. Samples ignored due to the setting of the clock options fields do not result ingaps. Samples which otherwise would be stored in acquisition memory but which are not because ofthe trigger program, result in gaps.

A gap indicates a break in the tracing of the bus activity. Generally, the disassembler should beaware of the existence of gaps (i.e., set Disassemble Across Gaps to No).

3.4.3 Inst/Data Display Field

This field controls display of instruction and data transactions which may have been stored inacquisition memory.

The setting of SHOW ALL (the default setting) permits display of instruction, read data and writedata transactions, as does the setting of All Types. The SHOW ALL setting additionally causes theCache Display, NonCache Display and Misc Display fields to all be treated as if they were set totheir default values, so that all types of transactions are enabled for display (refer to Section 3.4.4,Cache Display Field, Section 3.4.5, NonCache Display Field and Section 3.4.6, Misc Display Field.)

The setting of Inst, RdData permits display of instruction and read data transactions (display of writetransactions is disabled).

The setting of Inst, WrData permits display of instruction and write data transactions (display of readdata transactions is disabled).

The setting of Inst Only permits display of instruction transactions (display of read and writetransactions is disabled).

The setting of All Data permits display of read and write data transactions (display of instructiontransactions is disabled).

The setting of RdData Only permits display of read data transactions (display of instruction andwrite data transactions is disabled).

The setting of WrData Only permits display of write data transactions (display of instruction andread data transactions is disabled).

The above holds when probing RM7000 systems with RdType available (refer toSection 3.4.14, Processor Field); when probing other systems, the settings selected for this fieldshould be appropriately chosen based on the constant level connected to the RdType probe.

3.4.4 Cache Display Field

This field controls display of external cache transactions which may have been stored in acquisitionmemory.

The setting of All Types (the default setting) permits display of cache read hit, cache read miss andcache write transactions. (Note that the same results when the Inst/Data Display field is set toSHOW ALL; refer to Section 3.4.3, Inst/Data Display Field.)

The setting of All Reads permits display of cache read hit and cache read miss transactions (displayof cache write transactions is disabled).



The setting of RdHits, Wr permits display of cache read hit and cache write transactions (display ofcache read miss transactions is disabled).

The setting of RdHits Only permits display of cache read hit transactions (display of cache read missand cache write transactions is disabled).

The setting of RdMiss, Wr permits display of cache read miss and cache write transactions (display ofcache read hit transactions is disabled).

The setting of RdMiss Only permits display of cache read miss transactions (display of cache read hitand cache write transactions is disabled).

The setting of Writes Only permits display of cache write transactions (display of cache read hit andcache read miss transactions is disabled).

The setting of None permits no display of any cache transactions.

3.4.5 NonCache Display Field

This field controls display of non-cached (normal) transactions which may have been stored inacquisition memory.

The setting of All Types (the default setting) permits display of non-cached read and writetransactions. (Note that the same results when the Inst/Data Display field is set to SHOW ALL; referto Section 3.4.3, Inst/Data Display Field.)

The setting of Reads Only permits display of non-cached read transactions (display of non-cachedwrite transactions is disabled).

The setting of Writes Only permits display of non-cached write transactions (display of non-cachedread transactions is disabled).

The setting of None permits no display of any non-cached transactions.

3.4.6 Misc Display Field

This field controls display of external cache maintenance and external write transactions which mayhave been stored in acquisition memory.

External cache maintenance activities include Cache Line Invalidate (such as may occurindependently on the bus or as part of a cache read miss transaction with bus error), CacheLine Update (such as occurs as part of a read miss transaction without bus error), Cache Probeand Cache Block Clear actions.

External write transactions are write transactions initiated by units (other than the processor)to effect changes in the processor’s interrupt control register.

The setting of All Types (the default setting) permits display of external cache maintenance andexternal write transactions. (Note that the same results when the Inst/Data Display field is set toSHOW ALL; refer to Section 3.4.3, Inst/Data Display Field.)

The setting of Maint Only permits display of external cache maintenance actions (display of externalwrite transactions is disabled).

The setting of ExtWr Only permits display of external write transactions (display of external cachemaintenance actions is disabled).

The setting of None permits display of neither external cache maintenance actions nor external writetransactions.



3.4.7 H/W Cycles Field

This field affects the type of cycles displayed under the Hardware display format (see Section 3.4.1.1,Hardware Display Format); it has no effect under Software, Control Flow or Subroutine displaymodes. With the setting of As Acquired (the default setting), all acquired cycles are displayed underthe Hardware display format.

With the setting of No Specials, the display of any acquired special cycles (write preissue transactions(refer to Section 3.4.12, Write Reissues Field), nonissue request cycles (refer to Section 2.3.2.1, RequestCycle Acquisition, and Section 2.3.2.2, Processor Nonissue Behavior) and data wait and idle cycles) issuppressed under the Hardware display format.

With the setting of No Requests, the result is similar to that of No Specials, with suppressionadditionally of all access request cycles.

Figure 3.4 shows various types of acquired special cycles as displayed under the disassembler'sHardware format with As Acquired selected in the H/W Cycles field.

3.4.8 Regs-Byte Order Field

Selections include:

w S/W-BigEnd (the default)

w H/W-BigEnd

w S/W-LilEnd

w H/W-LilEnd

3.4.8.1 Register Naming Selection -

The register names selection (S/W or H/W) affects the representation of the processor's generalpurpose registers in the instruction mnemonics. Table 3.1 shows the names of the registers asdisplayed for each of the two settings. Note that register names F0 through F31 are used for floatingpoint coprocessor opcodes, regardless of the selection made here.

3.4.8.2 Byte Order Selection -

The byte order selection (BigEnd or LilEnd) must be set to match the operation of the processor beingprobed (big endian or little endian). An incorrect byte order setting can result in incorrectdisassembly display.

3.4.9 Exceptions Field

Selections include:

w Bev = 1 (the default)

w Bev = 0

w Bev = X

w Unlabeled

When an instruction fetch is done from an exception vector location, the disassembler labels the fetchas shown in Table 3.2. (Note that when the contents of exception vector locations have been cached,no indication is given on the bus that execution of the instruction at the exception vector location hasoccurred.)



Figure 3.4 - Example Of Special Cycles Hardware Display

The processor BEV bit controls the base address of the exception vectors (except for the resetexception vector). Selection of the Bev = 0 setting enables display of exception labels per the first sixentries in the table; selection of the Bev = 1 setting enables display of exception labels per the last sixentries in the table; selection of the Bev = X setting enables display of exception labels per all tableentries. Selection of Unlabeled results in no exception labeling at all taking place.

Refer to Section 3.4.10, Interrupt Ctrl Field, for further information concerning the Interrupt exception.

3.4.10 Interrupt Ctrl Field

This field determines whether instruction fetches occurring at certain locations will be labeled asInterrupt exceptions, per the enhanced interrupt handling mechanism of the RM7000.

The field allows specification of an eight-digit hexadecimal value (the default value of the field iszero). Of the eight hex digits: the eighth (most-significant; left-most) digit is ignored; the seventhdigit corresponds to the Enable Priority Encode (IV) bit of the processor’s Cause register; the sixthand fifth digits correspond to the Spacing (VS) bits of the processor’s Interrupt Control register; andthe fourth through first (least-significant; right-most) digits specify which priority levels have beenenabled, as explained below.

When probing RM527x processors (refer to Section 3.4.14, Processor Field), this field is treatedas if it had a value of zero.



Table 3.1 - Processor General Purpose Register Names

3.4.10.1 IV Bit -

The seventh hex digit of the Interrupt Ctrl field must be set in accordance with the value of theprocessor’s IV bit. A 0 hex digit (actually, any even-valued hex digit) is used to indicate that the IVbit is off; a 1 hex digit (actually, any odd-valued hex digit) is used to indicate that the IV bit is on.



Return AddressRAR31

Frame PointerFPR30

Stack PointerSPR29

Global PointerGPR28

Kernel 1K1R27

Kernel 0K0R26

Temporary 9T9R25

Temporary 8T8R24

Saved 7S7R23

Saved 6S6R22

Saved 5S5R21

Saved 4S4R20

Saved 3S3R19

Saved 2S2R18

Saved 1S1R17

Saved 0S0R16

Temporary 7T7R15

Temporary 6T6R14

Temporary 5T5R13

Temporary 4T4R12

Temporary 3T3R11

Temporary 2T2R10

Temporary 1T1R9

Temporary 0T0R8

Argument 3A3R7

Argument 2A2R6

Argument 1A1R5

Argument 0A0R4

Variable 1V1R3

Variable 0V0R2

Assembler TemporaryATR1

Zero ValueZEROR0

Software Name DescriptionSoftware Register NameHardware Register Name

Table 3.2 - Exception Vector Labeling

With a value of 0 (even values), only instruction fetches to addresses as indicated for INTERRUPTEXCEPTION in Table 3.2 (per the setting of the Exceptions field (refer to Section 3.4.9, ExceptionsField) are labeled as interrupt exceptions. In this case the other hex digits of the Interrupt Ctrl fieldare ignored.

With a value of 1 (odd values), instruction fetches to potentially any of a variety of addresses asdetermined by the interrupt spacing and priority levels’ values specified via the other (lower-order)hex digits of the Interrupt Ctrl field are labeled as interrupt exceptions.

3.4.10.2 Interrupt Spacing Bits -

When the seventh hex digit of the Interrupt Ctrl field has been set to indicate that enhanced interrupthandling is enabled, the sixth and fifth digits of the field must be set in accordance with the value ofthe processor’s interrupt Spacing bits. Only the hex values 00, 01, 02, 04, 08 or 10 should be entered,corresponding directly to the value of the Spacing bits of the Interrupt Control register (indicatingvector spacings of 0x000, 0x020, 0x040, 0x080, 0x100 or 0x200 respectively).

3.4.10.3 Interrupt Priority Levels Bits -

When the seventh hex digit of the Interrupt Ctrl field has been set to indicate that enhanced interrupthandling is enabled, the least-significant four digits of the field must be set to specify which interruptpriority level(s) have been enabled. Each of the sixteen bits comprising the four hex digitscorresponds to one priority level. A bit value of 1 is used to indicate that an interrupt can occur onthe corresponding priority level; a bit value of 0 is used to indicate that no interrupts can occur onthat level. As many as sixteen (all) of the priority level bits can be enabled at one time.

For example, a value of 0x0001 indicates interrupts can occur only at priority level 0; a value of0x0002 indicates interrupts can occur only at priority level 1; a value of 0x0003 indicates interruptscan occur at priority levels 0 and 1; a value of 0x8000 indicates interrupts can occur only at prioritylevel 15; a value of 0xFFFF indicates interrupts can occur at all priority levels (15 through 0); a valueof 0x0000 indicates no interrupts can occur.

Refer to Table 3.3 where the instruction fetch addresses which will be labeled as INTERRUPTEXCEPTIONs (per the Spacing bits’ and interrupt priority levels’ values) are listed.



INTERRUPT EXCEPTION0 1FC00400 1

COMMON EXCEPTION0 1FC00380 1

CACHE ERROR EXCEPTION0 1FC00300 1

XTLB REFILL EXCEPTION0 1FC00280 1

TLB REFILL EXCEPTION0 1FC00200 1

RESET EXCEPTION0 1FC00000Either

INTERRUPT EXCEPTION0 00000200 0

COMMON EXCEPTION0 00000180 0

CACHE ERROR EXCEPTION0 00000100 0

XTLB REFILL EXCEPTION0 00000080 0

TLB REFILL EXCEPTION0 00000000 0

Disassembly Display LabelPhysical AddressBEV Bit

Table 3.3 - Enhanced Interrupt Vector Offsets

3.4.11 Label Display Field

Selection of Enabled enables display of cache transaction cycle-type labeling; selection of Disabled(the default) disables such display.

With cache cycle-type labeling enabled, information is displayed underneath the column twopositions to the left of the "M" in Mnemonics, regarding the type of cache or noncache transaction ofwhich the cycle is part.

Processor cache read or write transaction request cycles are labeled with "c" (for "cached request").

Processor cache read hit data cycles are labeled with "h" (for "hit data").

Processor cache read miss data cycles are labeled with "m" (for "miss data"). Note that data cycles inwhich (or prior to which) a Cache Line Invalidate or Cache Line Update occurred, are labeled with"M" instead.

Processor cache write data cycles are labeled with "w" (for "write data").

Processor noncache transaction cycles are labeled with "u" (for "uncached cycles").

Processor transaction cycles whose "cacheability" cannot be determined (e.g., data cycles whoseassociated request cycle was not acquired) are labeled with "?".

Other cycles unrelated to processor read and write transactions (such as external write transactioncycles, cache housekeeping cycles and bus idle cycles) are not labeled.



0x20000x11000x9800x5C00x3E00x20015

0x1E000x10000x9000x5800x3C00x20014

0x1C000xF000x8800x5400x3A00x20013

0x1A000xE000x8000x5000x3800x20012

0x18000xD000x7800x4C00x3600x20011

0x16000xC000x7000x4800x3400x20010

0x14000xB000x6800x4400x3200x2009

0x12000xA000x6000x4000x3000x2008

0x10000x9000x5800x3C00x2E00x2007

0xE000x8000x5000x3800x2C00x2006

0xC000x7000x4800x3400x2A00x2005

0xA000x6000x4000x3000x2800x2004

0x8000x5000x3800x2C00x2600x2003

0x6000x4000x3000x2800x2400x2002

0x4000x3000x2800x2400x2200x2001

0x2000x2000x2000x2000x2000x2000

Spacing = 0x10Spacing = 0x08Spacing = 0x04Spacing = 0x02Spacing = 0x01Spacing = 0x00Priority Level

3.4.12 Write Reissues Field

RM7000 and RM527x processors can be configured to perform writes to memory using a write reissueprotocol in which a write transaction (request and data) is repeated if the memory system signals thatit is unable to handle the initial transaction request. The write transactions which occur prior to thefinal transaction are herein termed "preissue" transactions, since they occur before the finaltransaction.

Since there is no clock option provided to control the selective acquisition of write preissuetransactions (refer to Section 2.3, Clocking Choices), write preissue transactions if performed by theprocessor are always acquired. The Write Reissues field is used to notify the disassembler whetherthe processor is configured to perform write reissues.

Not Enabled (the default) covers the case of processors which are not configured to perform writereissues. Any write reissue transactions actually present on the bus and acquired will appear in thedisassembly display as normal write transactions; the disassembler will not identify them as havingbeen part of a write reissue sequence.

Selection of Enabled should be made in the case of processors which are configured to perform writereissues. The disassembler then identifies any write transaction in which the issuing request cycle hasWrRdyB unasserted (logically 1, electrically high) as being a write preissue transaction. Acquiredwrite preissue transaction cycles will be labeled in the disassembly display with "PREISSUE", whilethe final write transaction of the write reissue sequence will appear in the disassembly display as ausual write transaction. (Note that nonissue write request cycles which are part of an acquiredprocessor write preissue transaction are identified by the disassembler with ".PREISSUE".)

Note that acquired write preissue transactions are displayed by the disassembler only whenusing the Hardware display format (see Section 3.4.1.1, Hardware Display Format) and onlywhen the H/W Cycles field is set to As Acquired (see Section 3.4.7, H/W Cycles Field).

3.4.13 External Cache Field

Selection of Not Enabled (the default) forces the disassembler to ignore any external cache controlsignal values in the Control and TcVM groups (refer to Section A.2, Channel Groupings) wheninterpreting the activity of the processor bus. Such a selection does not allow for the possibility ofexternal cache activity on the bus; all bus activity (even if external cache activity is actually present) isinterpreted as if the external cache control signals were unasserted.

Since no cache activity is reported in the disassembly display, the setting of the Label Displayfield is ignored and instead taken to be set to Disabled (refer to Section 3.4.11, Label DisplayField).

Selection of Enabled enables the disassembler to utilize the external cache control signals present inthe acquired values of the Control and TcVM groups in interpreting the activity of the processor bus.Such a selection allows for the possibility of external cache activity on the bus.

Usually the External Cache selection is set to Enabled if an external cache is connected to theprocessor bus; the Not Enabled selection is utilized when no external cache is present.

Note that an improper setting of this field can result in incorrect disassembly display.



3.4.14 Processor Field

This field is set in accord with the type of processor being probed. The RM7000 w/ RdType selection(the default) is used when probing RM7000 systems where the processor’s RdType signal is availableand probed. In this case the interpretation by the disassembler of memory read accesses as beinginstruction fetches or data reads is not subject to any uncertainty; the Uncached Area fields and DataArea fields are ignored (refer to Sections 3.4.15 through 3.4.22), and no cycle marking facility isprovided (refer to Section 3.5, Marking Samples).

The RM7000 w/o RdType selection is used when probing RM7000 systems where the processor’sRdType signal is not available to be probed. In this case the interpretation by the disassembler ofmemory read accesses as being instruction fetches or data reads will be subject to some ambiguity; theUncached Area fields and Data Area fields (refer to Sections 3.4.15 through 3.4.22) influence theinstruction/data interpretation process, and the cycle marking facility is operative (refer toSection 3.5, Marking Samples).

The RM527x selection is used when probing RM527x systems. Again in this case the interpretationby the disassembler of memory read accesses as being instruction fetches or data reads will be subjectto some ambiguity; the Uncached Area fields and Data Area fields (refer to Sections 3.4.15 through3.4.22) influence the instruction/data interpretation process, and the cycle marking facility isoperative (refer to Section 3.5, Marking Samples).

3.4.15 Uncached Area1 Begin Field

This field is utilized when the Processor field is set to RM7000 w/o RdType or RM527x (seeSection 3.4.14, Processor Field). Refer to Section 3.4.16, Uncached Area1 Size Field, below.

3.4.16 Uncached Area1 Size Field

This field is utilized when the Processor field is set to RM7000 w/o RdType or RM527x (seeSection 3.4.14, Processor Field).

The Uncached Area1 Begin (default value 1FC00000 (hex)) and Uncached Area1 Size (defaultvalue 00100000 (hex)) fields define a region within which all non-block word (4 byte) reads that areword aligned are assumed to be instruction fetches and are decoded as such. Note that block reads inthe uncached area which would otherwise be assumed to be instruction block fetches are interpretedas data reads, not as instruction fetches.

The uncached area extends from Uncached Area1 Begin to (Uncached Area1 Begin +(Uncached Area1 Size - 1)). Only 32 bits are retained in the address computation (without carry orwraparound); address bits beyond the low 32 are computed as zero.

A value of zero for the Uncached Area1 Size field results in no Uncached Area1 being defined.

See also Section 3.4.18, Uncached Area2 Size Field.

3.4.17 Uncached Area2 Begin Field

This field is utilized when the Processor field is set to RM7000 w/o RdType or RM527x (seeSection 3.4.14, Processor Field). Refer to Section 3.4.18, Uncached Area2 Size Field, below



3.4.18 Uncached Area2 Size Field


The Uncached Area2 Begin (default value 0) and Uncached Area2 Size (default value 0) fields definea second region, similar to that defined by the Uncached Area1 Begin and Uncached Area1 Sizefields (refer to Section 3.4.16, Uncached Area1 Size Field).

The definitions of the two regions are independent; either or both (or neither) may define uncachedinstruction fetch regions. If two regions are defined, they may be independent or partially overlap (orcompletely overlap).

Note that in order for there to be no uncached areas defined, both Uncached Area1 Size andUncached Area2 Size must be set to zero.

3.4.19 Data Area1 Begin Field

This field is utilized when the Processor field is set to RM7000 w/o RdType or RM527x (seeSection 3.4.14, Processor Field). Refer to Section 3.4.20, Data Area1 Size Field, below.

3.4.20 Data Area1 Size Field


The Data Area1 Begin (default value 0) and Data Area1 Size (default value 0) fields define a regionwithin which all block reads are interpreted as data reads, not as instruction fetches.

The data area extends from Data Area1 Begin to (Data Area1 Begin + (Data Area1 Size - 1)). Only32 bits are retained in the address computation (without carry or wraparound); address bits beyondthe low 32 are computed as zero.

A value of zero for the Data Area1 Size field results in no Data Area1 being defined.

See also Section 3.4.22, Data Area2 Size Field.

3.4.21 Data Area2 Begin Field

This field is utilized when the Processor field is set to RM7000 w/o RdType or RM527x (seeSection 3.4.14, Processor Field). Refer to Section 3.4.22, Data Area2 Size Field, below.

3.4.22 Data Area2 Size Field


The Data Area2 Begin (default value 0) and Data Area2 Size (default value 0) fields define a secondregion, similar to that defined by the Data Area1 Begin and Data Area1 Size fields (refer toSection 3.4.20, Data Area1 Size Field).

The definitions of the two regions are independent; either or both (or neither) may define block dataread regions. If two regions are defined, they may be independent or partially overlap (or completelyoverlap).

Note that in order for there to be no data areas defined, both Data Area1 Size and Data Area2 Sizemust be set to zero.



3.5 MARKING SAMPLES

The sample-marking facility described in this section is provided (only) when the Processor field ofthe disassembly format definition overlay (properties page) is set to RM7000 w/o RdType or RM527x(see Section 3.4.14, Processor Field). The facility is provided (when provided) to manually mark readinformation cycles to change the manner in which the disassembler interprets them, as nowdescribed.

The disassembler usually disassembles information read during a block read which matches theinstruction cache line size, unless the read occurs in either of the data area ranges (refer toSections 3.4.19 through 3.4.22). The disassembler by default disassembles information read during aword-aligned 4-byte read in either of the uncached address ranges (refer to Sections 3.4.15 through3.4.18). The disassembler considers all other reads as data reads.

The disassembly display can be incorrect when the disassembler does not have proper information toaccurately disassemble bus cycles. This can occur at the start or end of an acquisition or when atrigger program is used which prevents certain bus cycles from being acquired. Disassembly forprocessors for which the data cache line size is the same as the instruction cache line size will haveblock data reads incorrectly disassembled as instructions. By marking bus cycles the disassemblercan be instructed to treat an assumed-instruction as data, or an assumed-data item as an instruction.

With the cursor selecting a read information (instruction or read data) bus cycle sample in thedisassembly display, selecting Mark Opcode in the data window causes display of a marking list. Ifthe sample was part of a block read, selections of Fetch Block, Read Block and Undo Mark arepresented. If the sample was part of a single datum read, selections of Fetch, Read and Undo Markare presented.

Selecting Fetch Block or Fetch forces the disassembler to interpret the information read sample as aninstruction(s). Selecting Read Block or Read forces the disassembler to interpret the information readsample as data. The display line shows ">>" when a Fetch (Block) or Read (Block) mark has beenplaced there. A sample marked with ">>" can have the mark removed by selecting Undo Mark.

When a block read information sample is marked with Fetch Block or Read Block, the disassemblerattempts to modify the disassembly of all information samples of that block read. If other informationsamples of the block read have been marked, the disassembler uses the mark on the earliest (lowestsequence number) sample for the block and ignores all other marks.



3.6 ALTERNATIVE DATA DISPLAYS

Bus cycle information that has been acquired using the Custom clocking selection (refer to Section 2.3,Clocking Choices) can be viewed not only using a disassembly display but also a state or even a timingdisplay.

3.6.1 State Display

A state display is simply a variety of disassembly display in which only raw (non-synthesized) groupvalues are selected for display

Recall, as explained in Section 3.3, Understanding The Disassembly Display, that the valuesdisplayed under the R7000D/E SysAD-Hi, R7000D/E A, R7000D/E Address and R7000D/EData-Mnemonics groups' columns are software-synthesized for the disassembly display (andthat the disassembly software may change the display order of instruction (orassumed-instruction) block read information). Refer also to Section A.2, Channel Groupings.

A state display is most helpful in presenting the actual cycle-by-cycle values which occurred on thebus, since no data translation is performed.

3.6.2 Timing Display

The timing display, like the state display, presents the actual cycle-by-cycle values which occurred onthe bus; no disassembly-like data translation is performed.

Use of the timing display may be helpful when the cycle-by-cycle behavior of particular individualchannels (for example, ResetB) needs to be observed.

Generally, with information acquired using the Custom clocking selection, the timing display is onlytruly useful when the Acquire All Cycles selection of the Acquisition field has been chosen (refer toSection 2.3.2, Acquisition Field). Since such an acquisition is a record of all bus cycles (not just theprincipal cycles in which memory transaction request and data information are communicated, aswould be the case with a Normal Acquisition field setting), the timing display can be used to see agraphical cycle-by-cycle presentation of the behavior of the bus. See for example Figure 3.5, whichshows an acquisition file displayed as a timing display.

It is important to remember that a display such as shown in Figure 3.5 is the result of synchronouslysampling the bus signals; the display never shows signals changing except around the start of eachbus cycle. In order to obtain a display which reveals the actual (intra-cycle) timing behavior of thesignals, an asynchronous acquisition must be performed; refer to Section 4.3, Internal Clocking.



Figure 3.5 - Timing Display Of An Acquire-All-Cycles Custom Clocking Acquisition



Besides the Custom clocking selection in the LA module Setup window which is utilized whenacquiring data for disassembly display, other clocking selections are possible. Presented here is adiscussion of the choices available and their uses.

4.1 CUSTOM CLOCKING

Acquisition of processor bus cycle information is usually done using the Custom clocking selection ofthe LA module Setup window. This is a form of synchronous acquisition in which a clock signal(SysClk) obtained from the system under test (SUT) is used to clock the acquisition module.

Custom clocking is an LA module Setup window choice when the R7000D/E support has beenloaded. Custom clocking implements a clocking state machine (CSM) which tracks the behavior ofimportant bus control signals (termed clock qualifiers) and controls which bus samples are acted uponby the acquisition module's trigger program and are possibly stored in acquisition memory. Customclocking also provides a set of clocking options (accessed via “More”) in the LA module Setupwindow (refer to Figure 2.2, LA Module Setup Window Clocking Options (R7000D Support)); these areinputs to the CSM which control its mode of operation.

Besides Normal Custom clocking acquisition, a Blocks Mode of acquisition is also available whichmight be used to advantage in some situations in conjunction with a user-specified trigger program.In Blocks Mode each sample which is chosen for storage by the trigger program has a set of 31additional samples stored preceding and following the sample (a total block of 63 samples is stored).

Note that all such block-stored samples are samples which the CSM has qualified (or willqualify) to be passed on to the trigger program based on the settings of the Custom clockingoptions. The block-store samples are not taken from the raw (each cycle) behavior as seen onthe bus and as input to the logic analyzer front end.

Use of Blocks Mode should be considered carefully; unless utilized properly, it may tend toconfuse the bus activity analysis when employed in conjunction with disassembly acquisitionand display.

4.2 EXTERNAL CLOCKING

The LA module setup window provides an External clocking selection. This may be thought of as asimplified version of Custom clocking. Like Custom clocking, External clocking involvessynchronous acquisition. However, rather than a software-configured CSM, a graphical userinterface is provided which allows entry of a set of clocking equations involving the clock channels andclock qualifiers (no state machine capability is available).

Under External clocking a further choice of Advanced is possible in which the settings of additionalhardware capabilities (multiple clocks, multiplexing, pipeline delay and setup times) can be specified.External clocking also provides a Blocks Mode of acquisition.

Note that no CSM qualification of the block-store samples occurs, since under Externalclocking no CSM exists.

Generally, with the support software loaded there is little utility in employing External clocking.

4. ACQUISITION CLOCKING CHOICES


4.3 INTERNAL CLOCKING

The LA module Setup window provides an Internal clocking selection. Internal clocking involvesasynchronous acquisition; a free-running clock in the acquisition module times data acquisition. TheLA module Setup window provides a field with which the internal clock rate can be set. UnderInternal clocking, no set of clocking equations or CSM exists to control the acquisition process.

The timing display is most usually used to view processor bus activity which has been acquired usingInternal clocking.

Probably the easiest way to get ready to perform an Internal clocking acquisition to be viewed as atiming display is to load an already-available system setup file: select Load System from the Filemenu, and then select the setup file (.tla file extension) desired. For example, the timing.tla filesupplied with the disassembly support can be loaded (found in theC:\Program Files\TLA700\Supports\R7000D (or R7000E) folder). The display will show signalslisted in an appropriate ordering (which can be changed as desired). An acquisition then performedwill display in the same data waveform window, retaining the already-defined signal ordering.

Figure 4.1 shows an acquisition file (Internal clocking acquisition) as a timing display (compare thisto the timing display of the Custom clocking acquisition timing display shown in Figure 3.5).

Internal clocking, like Custom and External clocking, also provides a Blocks Mode of acquisition. Asdescribed in Section 4.1, Custom Clocking, 62 additional samples are stored when the trigger programdecides to store a sample in acquisition memory.

Note that no CSM qualification of the block-store samples occurs, since under Internalclocking no CSM exists.

Acquisition Clocking Choices


Figure 4.1 - Example Timing Display Of An Internal Clocking Acquisition



A.1 CONNECTION TO SYSTEM UNDER TEST

It is the responsibility of the user to provide the means in the system under test (SUT) to achieveproper attachment of the logic analyzer probes.

A.1.1 Acquisition Module Electrical Characteristics

Loading of the SUT by the logic analyzer connections must be taken into consideration, especially inthe case of processors such as the RM7000 and RM527x which can operate with a very short bus cycleperiod and whose relatively small window of data stability may be significantly affected byadditional loading on the SUT signals.

The equivalent load produced by a connection to a TLA7xx acquisition module (per publishedspecifications) is approximately 20K Ohms resistance pulled up to 2.1 Volts, paralleled by 2 pF.

In addition to the loading produced by the acquisition module connection, the timing requirements ofthe module must also be considered. Relative to the rising edge of the SysClk clock input, allacquisition module inputs require 2 ns setup time and 0 ns hold time (typical).

Direct connection of the acquisition module inputs to the signals of the SUT is appropriate in mostsituations. Some configurations may benefit by the use of buffers and/or registers (i.e., designed intothe SUT).

A.1.2 Unused Signals

When processor signals are unused but are part of a channel group required by the disassembler, it isrecommended that the probes for those signals be connected to a constant electrical level.

For example, when probing systems without external caches, there may be no TcTCEB, TcTDEB,TcCWE0B and TcClrB signals. Since such external cache control signals are part of the requiredControl group (refer to Section A.2.5, Control Group), the probes for the four signals should be held ata constant electrical level if there are in fact no corresponding system signals to attach to. Because thecontrol signals are asserted low, the recommended level is an electrical high (also achievable bykeeping the probes disconnected).

As another example, RM527x systems with external caches have only 16 ScLine signals. Therefore,when probing such systems the probes for the two upper bits of the TcLine group (refer to SectionA.2.6, TcLine Group) should be held constant; an electrical low level is recommended for suchnon-control signals.

A. CHANNEL ASSIGNMENTS

R7000D/E Disassembler Manual A-1

The channel assignment information presented here in table form reflects the default state of the LAmodule Setup window once the support software is loaded. The channels of each group are listed inorder from most-significant bit (MSB) to least-significant bit (LSB).

All channels are defined by the support software to have 1.5 V thresholds. Channels marked in thetables with "*" are utilized as clock qualifiers by the acquisition module clocking state machine (CSM)and are required for proper Custom clocking acquisition.

Depending upon the version of support software being used (CHS151 R7000D support requiring asingle acquisition module having 136 channels or CHS152 R7000E support requiring a master modulehaving 136-channels and a slave module having at least 102 channels), the channels and theirgroupings will differ somewhat, as is described herein. In the case of R7000E support, the channelslisted in the tables below are associated with the master module except where noted; all channels ofthe R7000E slave module are unused (including CK and Q channels) except the channels indicated.

Note that the R7000D version of support makes no provision for probing the JTDI, JTDO,JTMS, JTCK, BigEndian, SysCmdP, PRqstB, PackB and RspSwapB RM7000 signals, while theR7000E version probes all signals of the RM7000.

A.2.1 SysAD-Hi Group

The default radix of the group is HEX. The default radix for disassembly display is OFF.

The group and all channels as listed are required for use by the disassembler. The disassemblersynthesizes the values displayed under the R7000D/E SysAD-Hi group column (independent of thechannels' actual values); displayed are the values of the SysAD63..32 signals as emitted during thememory transaction's access request bus cycle.

Refer to Table A.1.

A.2 CHANNEL GROUPINGS

Channel Assignments

A-2 R7000D/E Disassembler Manual

SysAD32D2:00

SysAD33D2:11

SysAD34D2:22

SysAD35D2:33

SysAD36D2:44

SysAD37D2:55

SysAD38D2:66

SysAD39D2:77

SysAD40D3:08

SysAD41D3:19

SysAD42D3:210

SysAD43D3:311

SysAD44D3:412

SysAD45D3:513

SysAD46D3:614

SysAD47D3:715

SysAD48A2:016

SysAD49A2:117

SysAD50A2:218

SysAD51A2:319

SysAD52A2:420

SysAD53A2:521

SysAD54A2:622

SysAD55A2:723

SysAD56A3:024

SysAD57A3:125

SysAD58A3:226

SysAD59A3:327

SysAD60A3:428

SysAD61A3:529

SysAD62A3:630

SysAD63A3:731

Signal NameChannelBit Position

Table A.1 - SysAD-Hi Group Channel Assignments

Channel Assignments


A.2.2 A Group

The default radix of the group is OFF. The default radix for disassembly display is OFF.

The disassembler requires that a group with the name "A" exists, and the group is required to have atleast one channel in it. Any channel(s) can be used to make up the group, with the exception that theWrRdyB signal must be the LSB (bit #0) of the group. Usually the group will be composed of theprocessor control signals shown below.

During disassembly display the disassembler synthesizes the values displayed under the R7000D/E Agroup column (independent of the channels' actual values); displayed (when disassembly display ofthe group is enabled) are the upper physical address bits issued during the memory access requestcycle (which are interpreted in conjunction with the low 32 address bits displayed under theR7000D/E Address group column).

Refer to Table A.2.

WrRdyBQ0* 0

RdRdyBC1:71

ReleaseBC1:62

ExtRqstBC0:33


Table A.2 - A Group Channel Assignments

A.2.3 Address Group

The default radix of the group is HEX. The default radix for disassembly display is HEX.

The group and all channels as listed are required for use by the disassembler to produce adisassembly display.

The disassembler synthesizes the values displayed under the R7000D/E Address group column,independent of the channels' actual values.

Refer to Table A.3.

A.2.4 SysAD Group


This 64-channel group is composed of the 32 channels of the SysAD-Hi group together with the 32channels of the Address group. The group’s value is not synthesized by the disassembler; its value isthat of the acquired signals.

The group is defined to facilitate trigger program range matching on the entire set of the SysADsignals.

The group is not required for use by the disassembler.

Channel Assignments


SysAD0D0:00

SysAD1D0:11

SysAD2D0:22

SysAD3D0:33

SysAD4D0:44

SysAD5D0:55

SysAD6D0:66

SysAD7D0:77

SysAD8D1:08

SysAD9D1:19

SysAD10D1:210

SysAD11D1:311

SysAD12D1:412

SysAD13D1:513

SysAD14D1:614

SysAD15D1:715

SysAD16A0:016

SysAD17A0:117

SysAD18A0:218

SysAD19A0:319

SysAD20A0:420

SysAD21A0:521

SysAD22A0:622

SysAD23A0:723

SysAD24A1:024

SysAD25A1:125

SysAD26A1:226

SysAD27A1:327

SysAD28A1:428

SysAD29A1:529

SysAD30A1:630

SysAD31A1:731


Table A.3 - Address Group Channel Assignments

Channel Assignments


A.2.5 Control Group

The default radix of the group is SYM (symbolic); the associated symbol table is R7000D_Ctrl (orR7000E_Ctrl) (refer to Table 2.1). The default radix for disassembly display is OFF. The group andall channels as listed are required for use by the disassembler to produce a disassembly display.

The disassembler synthesizes the values displayed under the R7000D/E Control group column(independent of the channels' actual values) when subblock reordering is performed during displayof instruction block read data cycles (refer to Section 3.2.3, Subblock Data Transfer Order).

When no RdType signal is available (as when probing an RM7000 system with RdType unavailable,or when probing an RM527x system; refer to Section 3.4.14, Processor Field), the probe providing theMSB of the Control group should be connected to a constant level (electrially high is recommended,also achievable by keeping the probe disconnected).

Refer to Table A.4.

SysCmd0C0:5 0

SysCmd1C0:6 1

SysCmd2C0:7 2

SysCmd3C1:0 3

SysCmd4C1:1 4

SysCmd5C1:2 5

SysCmd6C2:0*6

SysCmd7C1:3 7

SysCmd8C2:1*8

TcClrBCK0*9

TcCWE0BC1:5 10

TcTDEBC3:4 11

TcTCEBQ2*12

ValidOutBQ1*13

ValidInBC2:2*14

ResetBC0:1 15

RdTypeCK2*16


Table A.4 - Control Group Channel Assignments

Channel Assignments


A.2.6 TcLine Group

The default radix of the group in the Channel setup menu is HEX (hexadecimal). The default radixfor disassembly display is OFF.

The disassembler requires that a group with the name "TcLine" exists, and the group is required tohave at least one channel in it; any channel(s) can be used to make up the group. Usually the groupwill be composed of the TcLine15..0 signals of the processor as shown below.

The disassembler synthesizes the values displayed under the R7000D/E TcLine group column (inde-pendent of the channels' actual values) when subblock reordering is performed during display ofinstruction cached block read data cycles (refer to Section 3.2.3, Subblock Data Transfer Order).

Refer to Table A.5.

TcLine0E0:20

TcLine1E0:31

TcLine2E0:42

TcLine3E0:53

TcLine4E0:64

TcLine5E0:75

TcLine6E1:06

TcLine7E1:17

TcLine8E1:28

TcLine9E1:39

TcLine10E1:410

TcLine11E1:511

TcLine12E1:712

TcLine13E3:113

TcLine14E3:214

TcLine15E3:315

TcLine16E3:416

TcLine17E3:517


Table A.5 - TcLine Group Channel Assignments

Channel Assignments


A.2.7 TcWord Group

The default radix of the group in the Channel setup menu is HEX (hexadecimal). The default radixfor disassembly display is OFF.

The disassembler requires that a group with the name "TcWord" exists, and the group is required tohave at least one channel in it; any channel(s) can be used to make up the group. Usually the groupwill be composed of the TcWord1..0 signals of the processor as shown below.

The disassembler synthesizes the values displayed under the R7000E TcWord group column (inde-pendent of the channels' actual values) when subblock reordering is performed during display ofinstruction cached block read data cycles (refer to Section 3.2.3, Subblock Data Transfer Order).

Refer to Table A.6.

TcWord0E0:00

TcWord1E0:11


Table A.6 - TcWord Group Channel Assignments

A.2.8 TcVM Group

The default radix of the group in the Channel setup menu is BIN (binary). The default radix fordisassembly display is OFF.

The group and all channels as listed are required for use by the disassembler to produce a disassem-bly display.

Note that the disassembler does not synthesize the values displayed under the TcVM group. Bearthis in mind when viewing other related groups (such as R7000E TcLine and R7000E TcWord) whosedisplay is or may be synthesized, as explained above.

Refer to Table A.7.

TcMatchQ3* 0

TcValidE2:41


Table A.7 - TcVM Group Channel Assignments

Channel Assignments


A.2.9 Intr Group

The default radix of the group is SYM (symbolic); the associated symbol table is R7000E_Intr (orR7000E_Intr) (refer to Table 2.2). The same holds for the default radix for disassembly display.

Neither the group itself nor the channels listed are required for use by the disassembler.

Refer to Table A.8.

IntB0C0:40

IntB1C2:41

IntB2C2:52

IntB3C2:63

IntB4C2:74

IntB5C3:05

IntB6E2:06

IntB7E2:17

IntB8E2:28

IntB9E2:39

NMIBC3:110


Table A.8 - Intr Group Channel Assignments

A.2.10 Chk Group



Refer to Table A.9.

Note that the SysCmdP signal is defined and present in this group only for R7000E support.

SysADC0E2:50

SysADC1E2:61

SysADC2E2:72

SysADC3E3:03

SysADC4C3:54

SysADC5C3:65

SysADC6C3:76

SysADC7CK1 7

SysCmdP[Slave]C1:08


Table A.9 - Chk Group Channel Assignments

Channel Assignments


A.2.11 TcCtrl Group

The default radix of the group is BIN (binary). The default radix for disassembly display is OFF.


Refer to Table A.10.

TcDOEBC3:30

TcDCE0BC1:41

TcTOEBC3:22


Table A.10 - TcCtrl Group Channel Assignments

A.2.12 TcCtrl2 Group




In the table the first channel listed applies in the case of R7000D support; the second channel appliesin the case of R7000E support.

TcDCE1BE3:6 / [Slave]C0:60

TcCWE1BE3:7 / [Slave]C0:71


Table A.11 - TcCtrl2 Group Channel Assignments

A.2.13 Misc Group




Note that the BigEndian signal is defined and present in this group only for R7000E support.

VccOkC0:20

ColdResetBC0:01

BigEndian[Slave]C1:12


Table A.12 - Misc Group Channel Assignments

Channel Assignments


A.2.14 Mode group




In the table the first channel listed applies in the case of R7000D support; the second channel appliesin the case of R7000E support.

ModeClkC2:3 / [Slave]C0:50

ModeInE1:6 / [Slave]C0:41


Table A.13 - Mode Group Channel Assignments

A.2.15 XRAS Group (R7000E Support Only)




Note that the signals, defined for compatibility with R7000F and R7000G probing products (whichsupport RM7000 systems which utilize multiple outstanding reads (MORs)), are defined only forR7000E support. As is the case for other channels not required for use by the disassembler, all of thechannels listed in the table are available for probing other signals in the user’s system.

RspSwapBC2:30

PAckBE3:71

PRqstBE3:62

PRqstBXE1:63


Table A.14 - XRAS Group Channel Assignments

A.2.16 Clk Group


Neither the group itself nor the channels listed are required for use by the disassembler (except as aclock for the acquisition module).


SysClkCK30


Table A.15 - Clk Group Channel Assignment

Channel Assignments


A.2.17 JTAG Group (R7000E Support Only)




Note that the signals are defined only for R7000E support.

JTCK[Slave]C0:00

JTMS[Slave]C0:11

JTDO[Slave]C0:22

JTDI[Slave]C0:33


Table A.16 - JTAG Group Channel Assignments

Channel Assignments


This software product has a warranty against defects in the media for a period of one year. Duringthis warranty period, Crescent Heart Software will replace products that are defective. Please refer tothe software licensing agreement printed on the envelop in which the floppy disk(s) were packagedfor further information.

If a defect is suspected with the software product, contact Crescent Heart Software or the distributorfrom whom this product was purchased for information on obtaining service.

For items returned for warranty service, the buyer shall be responsible for all shipping and handlingcharges.

For more information on probe adapters, SMT adapters, other disassemblers and other availableitems, please contact Crescent Heart Software or the distributor from whom this product waspurchased.

Also contact Crescent Heart Software concerning any requirements you may have for custommodifications to this software product or for information concerning development of custom supportsoftware or hardware for probing other processors or related support devices.

B. SOFTWARE WARRANTY AND SERVICE

R7000D/E Disassembler Manual B-1


Software Warranty And Service

B-2 R7000D/E Disassembler Manual

C. HISTORY OF REVISIONS

C.1 MANUAL REVISION HISTORY

Rev 4.0 Software version change only (August, 1999)

Rev 3.2 Corrections and changes to Sections 2.3.3 and 2.3.4, and Table A.4. (June, 1999)

Rev 3.1 Minor typographical changes (January, 1999)

Rev 3.0 Documenting changes to software Rev 3.0 (Section 3.4.7) (December, 1998)

Rev 2.0 Documented changes relating to Rev 2.0 software (October, 1998)

Ver 1.0 Initial release (September, 1998)

C.2 SOFTWARE REVISION HISTORY

Rev 4.0 Changes to ensure proper optional marking of read accesses; changes to ensure proper handling ofRM7000 disassembly display when RdType is unavailable (August, 1999)

Rev 3.0 Addition of a No Requests selection to the H/W Cycles Displayed field of the disassemblyproperties page (December, 1998)

Rev 2.0 Changes to acquisition clocking state machine; changes to disassembly properties modes to allowspecification of processor (RM7000 or RM527x), with addition of uncached area, data area and cyclemarking facility in support of probing the RM527x and RM7000 where RdType is unavailable(October, 1998)

Ver 1.0 Initial release (September, 1998)

R7000D/E Disassembler Manual C-1


History Of Revisions

C-2 R7000D/E Disassembler Manual


R7000D/E Disassembler Manual

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