cpci 307 solated it...cpci 307 – rev. a – edition 1 – 23/25 5 chapter a presentation the cpci...

CONTACT: Email: [email protected]

Tel.: 33.1.41.87.30.00 www.adas.fr

APPLICATIONS

♦ 4 isolated 32-bit counter channels

♦ 4 differential inputs RS422 per channel: channels A ; B ; strobe ; RAZ

♦ Count up to 5 MHz in any mode

♦ Programmable filtering for noisy environments

♦ Direct interface with incremental encoders (X1, X4)

♦ 2 time bases and 1 program. clock

♦ Power supply 5 V/0.8 A, galvanically isolated

♦ Several operating modes, fully program.

♦ 18 programmable interrupt sources

♦ PCI interface 32 bits

♦ Support and supply of drivers (option)

Designed for counting applications, CPCI 307 board provides 4 stand-alone 32-bit counters for performing:

− Frequency and period measurements,

− Counting and counting down events,

− Conditioning incremental (circular or linear) encoders.

Designed to operate in noisy environments, CPCI 307 board uses differential optocoupled inputs and anti-bounce circuits.

It is fully programmable using easy-to-use and powerful software. It includes:

− Advanced interrupt management (18 sources),

− Programmable management of counters loading and Reset-to-zero.

4 ISOLATED, 32 BIT COUNTER CHANNEL CPCI 307

SPECIFICATIONS*

INPUTS

Per channel Channel "A", channel "B", strobe, clear

Type Optocoupled, regulated low input current

Inputs level + 5 V, ; + 12 V ; + 15 V ; +24 V

Galvanic isolation Up to 2500 V (1 mn) to PCI

Filtering Anti-bounce on counter inputs (A + B) software switchable adjustable frequencies of 125 kHz, 1 MHz, 10 MHz

Max. input frequencies (Link to emit device)

5 MHz in direct mode (10 meters max cf. RS422 distance)

5 MHz in quadruple discriminator mode (X4)

ACCURACY

Frequency measurement 10 -4 at 1 kHz

Period measurement 10 -4 at 1 KHz

MEANS

Internal clock Programmable from 100Hz to 10 MHz in decades

Time bases 2 (programmable from 0.01 s to 10 s in decades)

OPERATING MODES

Quadruple, double, single impulse per cycle for increment coders. Counting up or down of events, measurement of impulse width and frequencies with prepositionable count-up or countdown. Direct recognition of count-up or countdown modes and possibilities: Hysteresis, inhibition, counting, and preloading. External possibilities and loading and reset software. Possibility of interrupt after external loading, external clear, overflow, direction loading or end of time base.

Specifications are subject to change. Please, verify the latest specifications prior order. Version : 2.0— Edi�on : June 2016

CPCI 307 - 4 ISOLATED, 32 BIT COUNTER CHANNEL

INTERFACE PCI

Decoding 32 bits in memory space

Interrupts 18 sources available

POWER SUPPLY

Consumption + 5 V ± 0.25 V / 1.2 A max. + DC/DC

DC/DC converter Isolated, + 5V / 0.8 A (available for STB or BCI terminal blocks)

Protection Two 1 A fuses on fuse-holders

CONNECTORS

Front panel connectors 1 x μD 68 pins Female

PHYSICAL CHARACTERISTICS

Format 3U/4Te – CPCI FORM FACTOR

ENVIRONMENT

Operating temperature - 20°C to + 70°C

Storage temperature - 25°C to + 85°C

Relative humidity 90 % non condensing

EUROPEAN STANDARD

CE Compliance (EMC - EN 61326 - EN 55011 Class A) ROHS - 2002/95/EC

SP

EC

IF

IC

AT

IO

NS

*

ORDERING INFORMATION

CPCI 307 4 Isolated, 32 Bit counter channel

STB Terminal blocks STB 546

BCI Terminal blocks BCI 146

Cables WR 368

ACCESSORIES

*Specifications given for 25°C

CPCI 307 – Rev. A – Edition 1 – 23/25

1

TRACEABILITY FORM

DOCUMENT FOLLOW-UP

Title : Titre : CPCI 307

English documentation Edition : 1 (Document creation - Création du document)

Revised

Approved

Written

by

by

by B. THOUËNON

M. ROCHE

D. PIMONT

on

on

on

23/25

23/25

23/25

Visa

Visa

Visa

Warning : Unless otherwise stated, this revision overwrites the previous one which must be destroyed, along with any copies given to your collaborators.

Avertissement : En l’absence d’indication contraire, cette nouvelle édition annule et remplace l’édition précédente qui doit être détruite, ainsi que les copies faites à vos collaborateurs.

Edition Edition

Nature of the modifications (key words) Nature des évolutions (mots clés)

Written Rédigé

Revised/ApprovedRevu/Approuvé

2

on

Visa

by

on

Visa

by

3

on

Visa

by

on

Visa

by

4

on

Visa

by

on

Visa

by

5

on

Visa

by

on

Visa

by

6

on

Visa

by

on

Visa

by

DOCUMENT ARCHIVEDDOCUMENT ARCHIVE No Yes on

Δ ed. .. [ ] = Document input/output (Entrée/sortie modification de la documentation) # ed. .. [ ] = Board new function input/output (Entrée/sortie nouvelle fonctionnalité du produit)

DSQ - 4.5.a - Indice F - 98/41 T.S.V.P.


2

NOTES :


3

CPCI 307

SUMMARY

Chapter A Presentation .........................................5

A.1. Wiring and interconnection....................................................5

Chapter B PCI Interface.........................................6

B.1. Warnings ..................................................................................6

B.2. Literature ..................................................................................6

B.3. PCI configuration registers ....................................................7

B.4. PCI operational registers ......................................................10

B.5. PCI user registers..................................................................11

Chapter C Functional Analysis ...........................12

C.1. Counter Signals Interface.....................................................12

C.1.1. Signals from external insulated differential inputs...................12

C.1.2. Electrical characteristics of insulated photocoupled inputs.....16

C.1.3. Insulated power supply ...........................................................16

C.1.4. Internal counter signals...........................................................17

C.1.5. General-purpose signals.........................................................17

C.2. Channel Operating Modes....................................................18

C.2.1. Discrimator modes operation ..................................................19 C.2.1.1. Channel in quadruple mode..................................................................... 19 C.2.1.2. Channel in dual mode.............................................................................. 19 C.2.1.3. Channel in single mode ........................................................................... 20 C.2.1.4. Channel in discriminator mode with BT2 timebase .................................. 20 C.2.1.5. Hysteresis function .................................................................................. 21 C.2.2. Direct modes functions ...........................................................22

C.2.2.1. Channel in single mode (event count/down-count) .................................. 22 C.2.2.2. Channel in frequency measurement mode .............................................. 22


4

C.2.2.3. Repetitive frequency measurement mode ............................................... 23 C.2.2.4. Channel in width and pulse measurement mode ..................................... 23 C.2.2.5. Channel in period measurement mode.................................................... 23 C.2.3. Frequencymeter or periodmeter .............................................25

C.3. Detailed mapping of the CPCI 307 .......................................26

C.3.1. Channel configuration registers ..............................................26 C.3.1.1. Modes configuration registers (16 bits) .................................................... 26 C.3.1.2. Strobe, Clear and Status control register ................................................. 30

C.4. Timebase and interrupt masks registers ............................34

C.5. 32-bit counter register (0H at PU) ........................................36

Chapter D Getting started ..................................37

D.1. DELs .......................................................................................37

D.2. Input levels.............................................................................38

D.3. Wiring .....................................................................................39

D.4. Couplings ...............................................................................40

D.5. Terminal blocks .....................................................................41

Appendix .............................................................42

CONFIGURATION DRAWING..................................................................42

EQUIPMENT DRAWING .........................................................................42

PcI CONFIGURATION REGISTERS..........................................................42


5

Chapter A Presentation

The CPCI 307 board is a Compact PCI 3U 32-bit board with 4 counter channels. It plugs into a PC type machine.

>>>It includes: o A 32-bit PCI interface bus, o 4 channels (from 0 to 3), o an internal « Clock/Timebase » module, o an interrupt-handling module.

>>>Each channel has:

o One 32-bit counter/count-down counter, o 2 insulated counter inputs, o 2 insulated control inputs, o 1 anti-bounce module, o 1 configuration module, o 4 interrupt sources.

>>>Each of the four channels is a 32-bit channel for:

o frequency measurement, o period measurement, o event count/count-down, o (circular or linear) incremental encoder conditioning o incremental encoder speed measurement

The CPCI 307 board is fully compatible with the PCI 32-bit bus.

A.1. Wiring and interconnection

Please consult this heading on our web site or on our CD Rom.


6

Chapter B PCI Interface B.1. Warnings

The CPCI 307 board plugs into a PC with PCI 32-bit connectors. Therefore, it features all the characteristics related to this environment (PCI 2.1.). The PCI interface is provided by a custom device: AMCC S5933

B.2. Literature

We strongly advise the reader to obtain the following literature:

PCI HARDWARE and SOFTWARE

Architecture et Design Written by Edward SOLARI et George WILLSE

Edit. : ANNA BOOKS

ET

AMCC PCI CONTROLLERS

S5933 DATA BOOK


7

B.3. PCI configuration registers


8

For the CPCI 307 board, registers are configured as follows at power-up:

03 02 01 00

8849 10E8

0 0

0 0A

FFFFFFC0H

FFFFFFE0H

00

FFFF0001H

00 00 01 0B

00

00

00

00

00

00

00

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

14H

10H

08H

04H

00H

D31 D0

0CH

STATE AT THE POWER-UP

00

FF 0


9

8849 10E8

0 0

FF 0 00 0A

FFFFFFC0H

FFFFFFE0H

00

00

00

00

00

00

FFFFF0001H

00

00

00 00 01 0B

D31 D0

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

14H

10H

0CH

08H

04H

00H

64K octets

BOOT EPROM

AMCC at PU

8D wordsPCI USER REGISTER

CONF01 00H

CONF23 04H

STATUS 08H

BASE 0CH

COMP0 10H

COMP1 14H

COMP2 18H

COMP3 1CH

Channels 01 configuration

Channels 23 configuration

Status and command register

Interrupts and timebase

Channel 0 counter

Channel 1 counter

Channel 3 counter

Channel 2 counter

16D words

PCI OPERATION REGISTER

00H

Abreviations

04H

08H

0CH

10H

14H

18H

1CH

20H

24H

28H

2CH

30H

34H

38H

3CH

NU CPCI 307

NU CPCI 307

NU CPCI 307

NU CPCI 307

Incoming Mailbox Register 1

NU CPCI 307

NU CPCI 307

NU CPCI 307

NU CPCI 307

NU CPCI 307

NU CPCI 307

NU CPCI 307

NU CPCI 307

Mailbox Empty/Full status

Interrupt Control/Status Register

Bus Master Control/Status Register

IMB1

MBEF

INTCSR

MCSR

CPCI 307 CONFIGURATION


10

B.4. PCI operational registers

16 x 32-bit registers accessible via the address 10H in the configuration space (see Chapter B.3. PCI CONFIGURATION REGISTERS).

10H FF FF FF C0

The CPCI 307 board does not use all of these registers but only the following:

OFFSET ADDRESS ABREVIATION REGISTER NAME

10H IMB1 Incoming MailBox register 1 34H MBEF MailBox Empty / Full status 38H INTCSR INTerrupt Control / Status Register 3CH MCSR Bus Master Control / Status Register

These registers are relevant to the board in Slave operation mode. For informative purpose, the contents of those 16 registers as seen from the PCI are given in chapter B.3.


11

B.5. PCI user registers

8 x 32-bit registers accessible via the address 14H in the configuration space.

14H FF FF FF E0

CHANNEL 1 configuration CHANNEL 0 configuration R/W 00 00 00 00 Base + 0HCHANNEL 3 Configuration CHANNEL 2 configuration R/W 00 00 00 00 + 4H

STATUS CDE STATUS CDE STATUS CDE STATUS CDE R/W CHANNEL 3 0F CHANNEL

1 0F CHANNEL 2 0F CHANNEL 0 0F

+ 8H Mask, Time base Interruption R/W FF 00 FF 00 + CH

CHANNEL 0 32 bits counter R/W 00 00 00 00 + 10H CHANNEL 1 32 bits counter R/W 00 00 00 00 + 14H CHANNEL 2 32 bits counter R/W 00 00 00 00 + 18H CHANNEL 3 32 bits counter R/W 00 00 00 00 + 1CH

D31 D24 D23 D16 D15 D8 D7 D0 The italic value is the Hexadecimal value at power-up: R/W : Read / Write


12

Chapter C Functional Analysis C.1. Counter Signals Interface

Each channel has 4 photocoupled inputs insulated from the computer. All four channels are available through a 68-point microstrip connector that connects the board to the external world. Each channel has two internal status signals : Carry and Up/down. The CPCI 307 board can issue 4 interrupts per channel: = upon each up/down signal switchover = upon the active edge of CARRY, STROBE and CLEAR-ISO signals

C.1.1. Signals from external insulated differential inputs

A_I/O B_ISO STROBE_ISO CLEAR_ISO Note: Non-wired inputs are seen at logic level 1.

>>>A-ISO and B-ISO inputs Differential inputs are used in different ways depending on the modes selected. The CPCI 307 board features 2 main groups of operating modes:

o discriminator modes o direct modes


13

>>>Discriminator mode inputs

Inputs A and B provide discriminator inputs for the 32-bit counters when incremental encoders are used. o A_ISO signal switchover prior to B_ISO signal indicates the

counter is on o B_ISO signal switchover prior to A_ISO signal indicates the down-

count counter is on ROTATION DIRECTION UP/DOWN SWITCHOVER

Counting Down - count ing U/D

B

A

In this mode, signals are allocated as follows:

INTERNALLY PROVIDED INPUTS:

CLK 10MHz clock

INPUTS INSULATED FROM THE CONNECTOR

A_ISO B_ISO CLEAR_ISO STROBE_ISO

Discriminator input (signal A) ⎤ Max. count Discriminator input (signal B) ⎦ 5MHz CLEAR input (programmable level) STROBE input (programmable level)


14

>>>Direct mode inputs

o for frequency measurements, the signal is connected to A_ISO channel, the gate being generated by the CPCI 307 board

o for period measurements, the signal is connected to B_ISO channel, the clock being generated by the CPCI 307 board

o in direct counting mode, events to be counted are connected to A_ISO channel, the gate being on B_ISO.

ROTATION DIRECTION UP/DOWN SWITCHOVER

A_ISO

B_ISO

Count ing

In this mode, signals are allocated as follows:

CONNECTOR ISOLATED INPUTS

A_ISO B_ISO CLEAR_ISO STROBE_ISO

CLK input (signal A) GATE input (signal B) CLEAR input (programmable level) STROBE input (programmable level)


15

>>>STROBE_ISO input (external acquisition)

This insulated differential input is used to transfer counters data into the buffer registers and set a flag in the status register for the relevant channel. All 32 bits are transferred by this signal using the counter clock, which prevents the generation of erroneous codes. The triggering and disabling of this input are software-programmable. The CPCI 307 board makes it possible to generate an interrupt upon the active edge of this signal. Counters data acquisition can also be done under software control via the PCI bus, by writing into the relevant STROBE control register.

>>>CLEAR_ISO input (external clear)

This insulated differential input sets the counter to zero. The triggering and disabling of this input are software-programmable. The CPCI 307 board makes it possible to generate an interrupt upon the active edge of this signal. Counters data acquisition can also be done under software control via the PCI bus, by writing into the relevant CLEAR control register.

The duration of the STROBE_ISO and CLEAR_ISO input signals must be 300 ns above the active level.


16

C.1.2. Electrical characteristics of insulated photocoupled

inputs INPUT CELL DIAGRAM

+

-

C.1.3. Insulated power supply The CPCI 307 board features a DC/DC converter providing a + 5V insulated power supply to the differential inputs. This + 5V insulated power supply is available through the FRONT panel connector to power the photocouplers when highly insulated STB 546 terminal blocks (EMC Level 4) are used. This power-supply is fuse-protected (max 0.6A).


17

C.1.4. Internal counter signals The UP/DOWN internal signal. This signal is used to know the rotation direction of the angular encoders.

1 : Counting. 0 : Down-counting.

Its status, for each channel, can be accessed through the status register. CARRY internal signal This signal triggered when set to 1 indicates either an overflow in counting mode, or zero crossing in down-counting mode. Its status, for each channel, is accessible through the status register. The CPCI 307 board makes it possible to generate an interrupt upon the leading edge of this signal. C.1.5. General-purpose signals Internal clock The CPCI 307 board includes a 10MHz clock. It is used to synchronise the discriminator inputs in quadratic mode. In this mode, input signals frequency must not exceed five times the clock frequency. The CPCI 307 uses a 10MHz clock, then the maximum input frequency will be around 2MHz. Initialization At power-up, the PC issues a reset. It sets all registers to 00H, that is: = masked interrupts, = counter (A, B and CLK inputs), = quadruple mode, = without hysteresis nor anti-rebound = STROBE_ISO and CLEAR_ISO are off.


18

C.2. Channel Operating Modes

Each channel has several fully software-programmable operating modes. These modes fall into two main groups: • Discriminator modes • Discrete modes ⇒ Discriminator modes They are used by angular and incremental encoders.

3 main modes: o quadruple discriminator mode o dual discriminateur mode o single discriminator mode

For each mode, there are additional functions:

o Hysteresis functions Removal of a pulse each time the rotation direction changes

o Angular encoders speed measurement function BT2 timebase is used in Gate mode

⇒ Direct modes

4 main modes: o Event count/count-down o Pulse width measurement o Period measurement o Frequency measurement


19

C.2.1. Discrimator modes operation

C.2.1.1. Channel in quadruple mode

In quadruple mode, the clock selection circuit generates counting pulses on each edge of both discriminator signals. A and B signals are acquired by the CLK clock and their frequency will not exceed 5MHz. The clock selection circuit recognises the rotation direction by analysing the relative position of A and B signals.

S ynchroni z ation CLK

A_ISO input

B_ISO input

Co unting

U/D

C.2.1.2. Channel in dual mode

The dual mode is similar to the quadruple mode but only two edges by period are used.

A_ISO input

U/D


B_ISO input

Co unting

Quadruple and dual modes increase the resolution of incremental angular encoders.


20

C.2.1.3. Channel in single mode

The single mode is similair to quadruple mode but only one edge by period is acknowledged by the counter. The resolution is that of the encoder used.


A_ISO input

B_ISO input

Counting

U/D

C.2.1.4. Channel in discriminator mode with BT2 timebase

Speed measurement function. This mode is used to calculate the rotation speed of the angular encoders. Quadruple mode example In quadruple mode, the clock selection circuit generates counter pulses on each front of both discriminator signals. A and B signals are acquired by the CLK clock and their frequency will not exceed 5MHz. The BT2 timebase will be used as the counter gate. S ynchroni z ation CLK

A_ISO input

B_ISO input

I ntern al coun ting

BT2 Internal timebase

The counter then contains the point count acquired during the duration of BT2 timebase.


21

C.2.1.5. Hysteresis function

The HYSTERESIS function is available for the quadruple, dual and single modes. This function removes the first counter pulse after a direction change detected by the discriminator. S ynchroni z ation CLK

A_ISO Input

B_ISO Input

Co unting

U/D

Pulse removing after a direction change


22

C.2.2. Direct modes functions

C.2.2.1. Channel in single mode (event count/down-count)

A_ISO and B_ISO inputs are used respectively as the counter clock and gate. A_ISO input

B_ISO input

Co unting

C.2.2.2. Channel in frequency measurement mode

The signal to be measured is connected to A_ISO input. B_ISO input is left free and the board generates the timebase selected (see general configuration register).

A_ISO input

BTx

Co unting

1 ms synchronization max

Start BTx


23

C.2.2.3. Repetitive frequency measurement mode

The signal to be measured is connected to A_ISO input. The CPCI 307 generates the BT2 timebase which must be armed in repetitive mode (see timebase register). Only BT2 timebase can be used in this mode. The CPCI 307 continously measures the input frequency at the rate defined by BT2 timebase. The last measurement can be known by reading the counter.

Internal CLK

B_ISO

C o unting

C.2.2.4. Channel in width and pulse measurement mode The signal to be measured is connected to B_ISO input. A_ISO input is left free. The board generates the internal clock selected (see general configuration register to program it).

Internal CLK

B_ISO

Co unting

C.2.2.5. Channel in period measurement mode

Two period measurement methods are available: o measuring one period out of 2 on each channel o measuring all periods with 2 channels


24

>>>Measuring one period out of two

The signal to be measured is connected to B_ISO input. A_ISO input is left free (see general configuration register to program it).

Internal CLK

B_ISO

Counting

1st measure Gate

Clear

Load

2 nd mesure

>>>Measuring all periods Channels are coupled by pairs of two: channels 0 and 1; channels 2 and 3 The first measurement is done on channels 0 and 2, then in an alternate way. The signal to be measured is connected to B_ISO inputs (the relevant B_ISO inputs must be linked together).

Internal CLK

B_ISO

Channel 0 counting

1st measure Channel 0 gate 2nd measure

Channel 1 gate

Channel 1 counting


25

C.2.3. Frequencymeter or periodmeter

10-7

Periodmeter accuracy ≥ 10-4

Area with less accuracy

Area with less accuracy

Signals frequency to be measured

10-6

10-5

10-4

10-3

1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz

Frequencymeter accuracy ≥ 10-4 Accuracy

(Time base 10s)


26

C.3. Detailed mapping of the CPCI 307

The CPCI 307 user registers fall into 3 categories:

o channel configuration registers o 32-bit counter registers

C.3.1. Channel configuration registers

STATUS C3 CDE

C3

MSK BT2 MSK

BT1 HORLOGE STATUS

C1 CDEC1

BT2 BT1

STATUSC2

CDEC2

STATUS C0 CDE

C0

ARM BT2 ARM

BT1 BT2 REP IT IT IT

BT2 BT1 C

CONFIGURATION C3 MO DE CONFIGURATION C2 MODE CONFIGURATION C1 MODE CONFIGURATION C0 MODE

D31 D16 D15 D0

CH

8H

4H

0H

C.3.1.1. Modes configuration registers (16 bits)

0000H PU STATE Each channel has its own operation mode configuration register. Channel 0 Basis address + 0 Reading/writing access Channel 1 Basis address + 2 Channel 2 Basis address + 4 Channel 3 Basis address + 6

MSQ CRY

MSQ UPD MSQ CLR

MSQ STR

CLR1 CLR0 STR1 STR0 DEB1 DEB0 DIR M4 M3 M2 M1 M0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

IT Mask Clear Strobe Anti-rebound

Discriminator/direct

Modes

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16Channel 1, 3 Channel 0, 2

The idle state is 0000H ; this value must be writen in the configuration register prior to changing to another operation mode, to prevent erroneous counts.


27

>>>CONFIGURATIONS

Each group of modes is chosen by using the D21 and D5 (DIR) bits: D21, D5 = 0 Discriminator modes D21, D5 = 1 Direct modes The 00H code is the idle mode. Discriminator modes DIR = 0

BITS D19, D3 D18, D2 D17, D1 D16, D0

MODES HEX M3 M2 M1 M0 Simple mode Quad Double Simple

1 2 3

0 0 0

0 0 0

0 1 1

1 0 1

Hysteresis Quad Double Simple

5 6 7

0 0 0

1 1 1

0 1 1

1 0 1

Speed measurement with Quad Timebase 2 Double Simple

9 A B

1 1 1

0 0 0

0 1 1

1 0 1

Speed measurement with Quad Hysteresis and timebase 2 Double Simple

D E F

1 1 1

1 1 1

0 1 1

1 0 1

The M4 bit is a non significant bit in discriminator mode. Direct modes DIR = 1 The M4 bit (direction) is used to specify the counting direction: M4 = 0 Count-down M4 = 1 Count

BITS HEX D19, D3 D18, D2 D17, D1 D16, D0 Source Source MODES M3 M2 M1 M0 A (CLK) B (Gate)

Direct Simple

0 1

0 0

0 0

0 0

0 1

A_ISO A_ISO

B_ISO B_ISO inversed

Measure Frequency

2 3

0 0

0 0

1 1

0 1

A_ISO A_ISO

BT1 BT2

Measure Repetitive Frequency

B

1 0 1 1 A_ISO BT2 repetitive

Measure Impulsion

4 5

0 0

1 1

0 0

0 1

HORLOGE HORLOGE


Measure Impulsion

6 7

0 0

1 1

1 1

0 1

10MHz 10MHz


Measure Period

C D

1 1

1 1

0 0

0 1

HORLOGE HORLOGE


Measure Period

E F

1 1

1 1

1 1

0 1

10MHz 10MHz



28

>>>CONTROLS

Control of Strobes

D25, D9 D24, D8 STROBEs MODE

STR1 STR0 STROBE Mode 0 0 1 1

0 1 0 1

Strobe under software control Automatic Strobe Strobe on signal STROBE-ISO actif at 0 Strobe on signal STROBE-ISO actif at 1

A STROBE is always possible under software control. The automatic STROBE function transfers the contents of the counters into the buffer registers upon the leading edge of B_ISO signal or BT2 timebase in discriminator mode (D19, D3 = 1: mode register) and in repetitive frequency measurement mode. Control of Clears

D27, D11 D26, D10 MODES DES CLEARs

CLR1 CLR0 Mode CLEAR 0 0 1 1

0 1 0 1

Clear under software control Automatic Clear Clear on signal CLEAR-ISO actif at 0 Clear on signal CLEAR-ISO actif at 1

A CLEAR is always possible under software control. An automatic CLEAR resets the counters to zero. (cumulative measurements could be done if the counters are not reset to zero).


29

Anti-rebound Both insulated inputs (A_ISO, B_ISO) have an anti-rebound circuit. An anti-rebound circuit is used to remove spurious pulses. The maximum allowed frequency when using the anti-rebound circuit is the sampling frequency divided by 4. Available sampling frequencies (can be changed under software control):

Sampling frequencies Filtred pulses Max. frequency 10MHz < 400ns 2,5MHz 1MHz < 4μs 250KHz

100KHz < 40μs 25KHz

D23, D7 and D22, D6 bits are used to set the sampling frequency to counter signals.

D23, D7 D22, D6 Sampling frequency

0 0 Inhibited anti-rebound 0 1 Sampling frequency : 100KHz 1 0 Sampling frequency: 1MHz 1 1 Sampling frequency: 10MHz

>>>CONTROL OF INTERRUPT MASKS

MSQCRY MSQUPD MSQCLR MSQSTR

D15 D14 D13 D12

Mask IT carry

Mask IT Up/Down

Mask IT Strobe

Mask IT Clear

D31 D30 D29 D28

One bit set to 1 enables the interrupt One bit set to 0 disables the interrupt


30

C.3.1.2. Strobe, Clear and Status control register

OFH PU STATE Base address + 8H, + 9H, AH, BH

D15 D14 D13 D12 D11 D10 D9 D8 D3 D2 D1 D0D7 D6 D5 D4

Address 09H (channel 2) Address 08H (channel 0)

STATUS C2 CLR2 ST1 STATUS C0

Clear command

Strobe command

Cear command

Strobe command

CLR2 ST1

D31 D30 D29 D28 D27 D26 D25 D24 D19 D18 D17 D16D23 D22 D21 D20

Address 0BH (channel 3) Address 0AH (channel 1)

STATUS C3 CLR2 ST1 STATUS C1

Clear command

Strobe command

Clear command

Strobe command

ST1CLR2


31

>>>STROBE COMMANDS

These bits are used to control software Strobes (write access only).

One or more bits set to « 1 » transfer the contents of relevant counter(s) into the buffer registers and set (to 1) a status that will be read at the status address on the relevant bits when the transfer is completed. These status are reset to « 0 » upon reading the counter.

>>>CLEAR COMMANDS These bits are used to control the software CLEARs for each counter (write access only).

A write with one or more bits set to « 1 » resets the counter(s) to zero.

Channel 3

Channel 1

Channel 2

Channel 0

D16 D8 D24 D0

Channel 3

Channel 1

Channel 2

Channel 0

D17 D9 D25 D1


32

>>>STATUS READING (32 bits only)

Read (0H at PU) By reading the status bits, it is possible to know what actions were performed on the CPCI 307 board and the interrupt source (unmasked). Reading this register causes the interrupt to be automatically acknowledged and resets the status register. Therefore it shoud be read as 32 bits only.

CRY UPD CLR STR CRY UPD CLR STR CRY UPD CLR STR CRY UPD CLR STR

D31 D28 D23 D20 D15 D12 D7 D4

Channel 3 Channe l 1 Channe l 2 C hanne l 0

D30 D29 D22 D13 D21 D14 D6 D5

STROBE (STR) status These status (set to 1) can be used to know whether the contents of the relevant channel was transferred into the buffer register under software control or through a STROBE_ISO signal.


33

CLEAR (CLR) status These status (set to 1) can be used to know whether the contents of the relevant channel was transferred into the buffer register under software control or through a CLEAR_ISO signal. UP/DOWN (UPD) status These status can be used to know the rotation direction of angular encoders:

1 : count direction 0 : count-down direction

CARRY (CRY) status These status (set to 1) indicate either an overflow in counter mode or zero crossing in count-down counter mode.

>>>INTERRUPT SOURCES The PCI 307 can generate 18 interrupts. 4 sources per channel and 1 source per timebase. Sources per channel

o STROBE_ISO channel (active edge) in software STROBE o CLEAR_ISO signal (active edge) o CARRY signal on (leading edge) o UP/DOWN signal switchover

Timebase sources One interrupt can be generated at the end of Timebase 1 ou Timebase 2.

BTx

ITBTx

These are maskable interrupts (see general configuration register).


34

C.4. Timebase and interrupt masks registers

>>>INTERRUPTS REGISTER

Base address + 0CH in read access only (00H at PU)

0 0 0 0 0 IT BT2

IT BT1

IT C1

IT Timebase 2 = 1

IT Timebase 1 = 1

IT canaux = 1 Sources sum

D7 D6 D5 D4 D3 D2 D1 D0

These 3 interrupts are « OR-wired » to generate an interrupt on the PCI (INTA). The IT channels bit is reset to zero upon reading the status register. The IT Timebase bits are also used as status bits and are reset to zero upon reading the interrupts register.

>>>GENERAL CONFIGURATION REGISTER

Base address + 0EH in read/write access mode (00H at PU) The CPCI 307 board internally provides one clock and two programmable timebases. This register is used to program the clock frequency (when used for period measurements), BT1 and BT2 timebases, and to mask the interrupts of the said timebases.

MSKBT MSKBT CLOC BT2 BT1

BT2 inhibited = 0 BT2 autorised = 1 BT1 inhibited = 0 BT1 autorised = 1

D23 D22 D21 D20 D19 D18 D17 D16


35

Bits D16 to D19 are used to set the value of BT1 and BT2, as follows:

D17 D16 BT1 D19 D18 BT2

0 0 1

0 1 X

0,1s 1s 10s

0 0 1 1

0 1 0 1

0,01s 0,1s

1s 10s

Timebases 1 and 2 are armed through a write access into the Timebases commands register. Bits D20 and D21 are used to set the frequency of the CLOCK signal.

D21 D20 CLOCK 0 0 1 1

0 1 0 1

1MHz 100KHz 10KHz 1KHz

>>>TIMEBASE ARMING REGISTER

Address + 0CH in write access only

BT2 REP

D7 D6 D5 D4 D3 D2 D1 D0

BT2 BT1 A RM ARM

BT1 or BT2 timebase in single mode. Writing to OCH address with the D6 bit to « 1 » arms the BT1 timebase. Writing to OCH address with the D7 bit to « 1 » arms the BT2 timebase. Both timebases can be armed simultaneously.


36

Timebase 2 in repetitive mode Writing to OCH address with the D4 bit set to « 1 » arms the BT2 timebase in repetitive mode for continuous frequency measurements (see modes register). The BT2 timebase is rearmed automatically 1 ms after the last measurement. Writing to OCH address with the D4 bit set to « 0 » disables the BT2 repetitive timebase.

C.5. 32-bit counter register (0H at PU)

Each channel features a 32-bit counter/count-down counter in read/write access.

CHANNEL 3

CHANNEL 2

CHANNEL 1

CHANNEL 0

+ 1CH

+ 18H

+ 14H

BASE + 10H

D31 D0

The value of the counters is « 0 » at power-up. To read the counters, it is necessary to hold its contents by sending a write command to the channel STROBE address or through an external action via STROBE_ISO. Counter data can be transferred at any time. A dual buffer avoids any erroneous reading.


37

Chapter D Getting started

The CPCI 307 board is a Compact PCI 3U board that plugs into a PC. Mind static discharges when unpacking the board. Always plug and remove the board with the PC power off to avoid any potential problem. The user will also take care to read the following document:

GENERAL INSTRUCTIONS FOR IMPLEMENTING ADAS PRODUCTS

INSTRUCTIONS GENERALES DE MISE EN OEUVRE DES PRODUITS ADAS

Always plug the board into a frame with the power off.

D.1. DELs The CPCI 307 board features 3 DELs: DS3 Access to the CPCI 307 board from the PC DS2 Displays the activity of BT2 timebase DS1 Displays the activity of BT1 timebase


38

D.2. Input levels

Each level can be set on the corresponding channel. A SX00 switch on each channel is available to select an input level between 5V and 24V. The switches can be moved by groups of 4 (1 to 4 and 5 to 8).

COUNTERx

1246 57 38

ON

A B

I NA

I NB

S TR

OB

EC

LEA

RI N

AI N

BS T

RO

BE

CLE

AR

A B NOMINAL LEVEL MIN MAX OFF OFF 24V 17V 32V ON OFF 15V 10V 20V OFF ON 12V 9V 16V ON ON 5V 3,5V 5,5V


39

D.3. Wiring

µD 68S

PIN SIGNAL PIN SIGNAL 1 NC 35 NC 2 IN A 0 (-) 36 IN A 0 (+) 3 + 5V - V0 37 0V - V0 4 IN B 0 (-) 38 IN B 0 (+) 5 + 5V - V0 39 0V - V0 6 CLEAR 0 (-) 40 CLEAR 0 (+) 7 + 5V - V0 41 0V - V0 8 STROBE 0 (-) 42 STROBE 0 (+) 9 + 5V - V0 43 0V - V0 10 IN A 1 (-) 44 IN A 1 (+) 11 + 5V - V1 45 0V - V1 12 IN B 1 (-) 46 IN B 1 (+) 13 + 5V - V1 47 0V - V1 14 CLEAR 1 (-) 48 CLEAR 1 (+) 15 + 5V - V1 49 0V - V1 16 STROBE 1 (-) 50 STROBE 1 (+) 17 + 5V - V1 51 0V - V1 18 IN A 2 (-) 52 IN A 2 (+) 19 + 5V - V2 53 0V - V2 20 IN B 2 (-) 54 IN B 2 (+) 21 + 5V - V2 55 0V - V2 22 CLEAR 2 (-) 56 CLEAR 2 (+) 23 + 5V - V2 57 0V - V2 24 STROBE 2 (-) 58 STROBE 2 (+) 25 + 5V - V2 59 0V - V2 26 IN A 3 (-) 60 IN A 3 (+) 27 + 5V - V3 61 0V - V3 28 IN B 3 (-) 62 IN B 3 (+) 29 + 5V - V3 63 0V - V3 30 CLEAR 3 (-) 64 CLEAR 3 (+) 31 + 5V - V3 65 0V - V3 32 STROBE 3 (-) 66 STROBE 3 (+) 33 + 5V - V3 67 0V - V3 34 0V ISO 68 + 5 V ISO


40

D.4. Couplings

The CPCI 307 board features 4 identical counter channels. Each channel uses the A, B, CLEAR and STROBE inputs. These inputs are photocoupled IN (+) and IN (-) inputs. Coupling examples:

DATA (+)

(-)

IN 5V

PCI 307 Differential transmitter

(+)

(-)

Non differential « TTL » transmitter

DATA TTL

GND

FM2

(+)

(-)

Résistance de terminaison optionnelle sur plots R = f(Zc)

FM2

TTL

IN 5V

For EMC immunity, the shield is grounded using the transmitter’s ground.

CPCI 307


41

D.5. Terminal blocks

Two terminal blocks are available for the CPCI 307:

o STB 546 o BCI 146

The WR 368 cable allows a direct connection to these products.


42

Appendix

CONFIGURATION DRAWING

EQUIPMENT DRAWING

PcI CONFIGURATION REGISTERS

CPCI 307

43

Configuration Abbreviation Register NameAddress Offset

00h–01h VID Vendor Identification02h–03h DID Device Identification04h–05h PCICMD PCI Command Register06h–07h PCISTS PCI Status Register08h RID Revision Identification Register09h–0Bh CLCD Class Code Register0Ch CALN Cache Line Size Register0Dh LAT Master Latency Timer0Eh HDR Header Type0Fh BIST Built-in Self-test10h–27h BADR0-BADR5 Base Address Registers (0-5)28h–2Fh — Reserved30h EXROM Expansion ROM Base Address34h–3Bh — Reserved3Ch INTLN Interrupt Line3Dh INTPIN Interrupt Pin3Eh MINGNT Minimum Grant3Fh MAXLAT Maximum Latency40h–FFh — Not used

PCI CONFIGURATION REGISTERSEach PCI bus device contains a unique 256-byte region called its configuration header space. Portions of thisconfiguration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification.This section describes each of the configuration space fields—its address, default values, initialization options,and bit definitions—and also provides an explanation of its intended usage.

CPCI 307

44

VENDOR IDENTIFICATION REGISTER (VID)Register Name: Vendor IdentificationAddress Offset: 00h-01hPower-up value: 10E8h (AMCC, Applied Micro

Circuits Corp.)Boot-load: External nvRAM offset

040h-41hAttribute: Read Only (RO)Size: 16 bits

The VID register contains the vendor identificationnumber. This number is assigned by the PCI SpecialInterest Group and is intended to uniquely identifyany PCI device. Write operations from the PCI inter-face have no effect on this register. After reset isremoved, this field can be boot-loaded from the ex-ternal non-volatile device (if present and valid) so thatother legitimate PCI SIG members can substitute theirvendor identification number for this field.

Bit Description

15 010E8h

Vendor Identification Register (RO)

15:0 Vendor Identification Number: This is a 16 bit-value assigned to AMCC.

CPCI 307

45

PCI CONFIGURATION REGISTERS

DEVICE IDENTIFICATION REGISTER (DID) Register Name: Device Identification Address Offset: 02h-03h Power-up value: 4750h (ASCII hex for ‘GP’,

General Purpose) Boot-load: External nvRAM offset

042h-43hAttribute: Read OnlySize: 16 bits

15 0

Device Identification Register (RO)

82F9

Bit Description

15:0 Device Identification Number: This is a 16-bit value initially assigned by AMCC to ADAS applications for PCI 102 card.

The DID register contains the vendor-assigned deviseidentification number. This number is generated by AMCCin compliance with the conditions of the PCI specification.Write operations from the PCI interface have no effect onthis register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present andvalid) so that other legitimate PCI SIG members cansubstitute their own device identification number for thisfield.

CPCI 307

46

PCI COMMAND REGISTERRegister Name: PCI CommandAddress Offset: 04h-05hPower-up value: 0000hBoot-load: not usedAttribute: Read/Write (R/W on 6 bits,

Only for all others)Size: 16 bits

This 16-bit register contains the PCI Command. Thefunction of this register is defined by the PCI specifi-cation and its implementation is required of all PCIdevices. Only six of the ten fields are used by thisdevice; those which are not used are hardwired to 0.The definitions for all fields are provided here forcompleteness.

15 0

Reserved = 00's

Fast Back-to-BackSERREWait Cycle EnableParity Error EnablePalette SnoopMemory Write and InvalidateSpecial Cycle EnableBus Master EnableMemory AccessI/O Access Enable

X 00 X 0 0 0 XXX

123456789

CPCI 307

47

15:10 Reserved. Equals all 0’s.

9 Fast Back-to-Back Enable. The S5933 does not support this function. This bit must be set to zero.This bit is cleared to a 0 upon RESET#.

8 System Error Enable. When this bit is set to 1, it permits the S5933 controller to drive the open drainoutput pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normallysignifies a parity error on the address/control bus.

7 Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5933controller never uses stepping, it is hardwired to 0.

6 Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. Whena parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testingdisabled) upon the assertion of RESET#.

5 Palette Snoop Enable. This bit is not supported by the S5933 controller and is hardwired to 0. Thisfeature is used solely for PCI-based VGA devices.

4 Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the MemoryWrite and Invalidate PCI bus command when set to 1. When set to 0, masters must use the MemoryWrite command instead. The S5933 controller does not support this command when operated as amaster and therefore it is hardwired to 0.

3 Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when thisbit is set to 1. The S5933 controller does not monitor (or generate) special cycles and this bit ishardwired to 0.

2 Bus Master Enable. This bit, when set to a one, allows the S5933 controller to function as a bus master.This bit is initialized to 0 upon the assertion of signal pin RESET#.

1 Memory Space Enable. This bit allows the S5933 controller to decode and respond as a target formemory regions that may be defined in one of the five base address registers. This bit is initializedto 0 upon the assertion of signal pin RESET#.

0 I/O Space Enable. This bit allows the S5933 controller to decode and respond as a target to I/O cycleswhich are to regions defined by any one of the five base address registers. This bit is initialized to 0upon the assertion of signal pin RESET#.

Bit Description

CPCI 307

48

PCI STATUS REGISTER (PCISTS)

Register Name: PCI Status

Address Offset: 06h-07h

Power-up value: 0080hBoot-load: not usedAttribute: Read Only (RO), Read/Write

Clear (R/WC)Size: 16 bits

7 0

X00XXX

6

XX

Reserved (RO)

Signaled Target Abort (R/WC)Received Target Abort (R/WC)Received Master Abort (R/WC)Signaled System Error (R/WC)Detected Parity Error (R/WC)

0

15 14 13 12 11 10 9 8

Reserved (RO) = 00's

Fast Back-to-Back (RO)Data Parity Reported (R/WC)

DEVSEL# Timing Status (RO) 0 0 = Fast (S5933) 0 1 = Medium 1 0 = Slow 1 1 = Reserved

This 16-bit register contains the PCI status informa-tion. The function of this register is defined by thePCI specification and its implementation is requiredof all PCI devices. Only some of the bits are used bythis device; those which are not used are hardwiredto 0. Most status bits within this register are desig-nated as “write clear,” meaning that in order to cleara given bit, the bit must be written as a 1. All bitswritten with a 0 are left unchanged. These bits areidentified in Figure 4 as (R/WC). Those which areRead Only are shown as (RO) in Figure 4.

CPCI 307

49

Bit Description

15 Detected Parity Error. This bit is set whenever a parity error is detected. It functions independentlyfrom the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location.

14 Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can bereset by writing a 1 to this location.

13 Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset bywriting a 1 to this location.

12 Received Target Abort. This bit is set whenever this device has one of its own initiated cyclesterminated by the currently addressed target. This bit can be reset by writing a 1 to this location.

11 Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target.This bit can be reset by writing a 1 to this location.

10:9 Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from thisdevice when accessed as a target.

8 Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involvingthe S5933 device as the master. The Parity Error Enable bit (D6 of the Command Register) must beset in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this locationor by the assertion of the signal RESET#.

7 Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a target.

6:0 Reserved. Equal all 0’s.

CPCI 307

50

REVISION IDENTIFICATION REGISTER (RID)Register Name: Revision IdentificationAddress Offset: 08hPower-up value: 00hBoot-load: External nvRAM/EPROM offset

048hAttribute: Read OnlySize: 8 bits

The RID register contains the revision identificationnumber. This field is initially cleared. Write operationsfrom the PCI interface have no effect on this register.After reset is removed, this field can be boot-loadedfrom the external non-volatile device (if present andvalid) so that another value may be used.

Bit Description

7:0 Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h.

7 000h

Revision Identification Number (RO)

CPCI 307

51

CLASS CODE REGISTER (CLCD)Register Name: Class CodeAddress Offset: 09h-0BhPower-up value: FF0000hBoot-load: External nvRAM offset

049h-4BhAttribute: Read OnlySize: 24 bits

This 24-bit, read-only register is divided into threeone-byte fields: the base class resides at location0Bh, the sub-class at 0Ah, and the programming in-terface at 09h. The default setting for the base classis all ones (FFh), which indicates that the devicedoes not fit into the thirteen base classes defined inthe PCI Local Bus Specification. It is possible, how-ever, through use of the external non-volatilememory, to implement one of the defined class codesdescribed in Table 7 below.

For devices that fall within the seven defined classcodes, sub-classes are also assigned. Tables 8through 20 describe each of the sub-class codes forbase codes 00h through 0Ch, respectively.

7 0Sub-Class

7070Base Class Prog I/F

(Bit)(Offset)@09h@0Ah@0Bh

Base-Class Description

00h Early, pre-2.0 PCI specification devices

01h Mass storage controller

02h Network controller

03h Display controller

04h Multimedia device

05h Memory controller

06h Bridge device

07h Simple communication controller

08h Base system peripherals

09h Input devices

0Ah Docking stations

0Bh Processors

0Ch Serial bus controllers

0D-FEh Reserved

FFh Device does not fit defined class codes (default)

Sub-Class Prog I/F Description

00h 00h All devices other than VGA

01h 00h VGA-compatible device

CPCI 307

52


00h 00h RAM memory controller

01h 00h Flash memory controller

80h 00h Other memory controller


00h 00h SCSI controller

01h xxh IDE controller

02h 00h Floppy disk controller

03h 00h IPI controller

04h 00h RAID controller

80h 00h Other mass storage controller


00h 00h Ethernet controller

01h 00h Token ring controller

02h 00h FDDI controller

03h 00h ATM controller

80h 00h Other network controller


00h 00h VGA-compatible controller

00h 01h 8514 compatible controller

01h 00h XGA controller

80h 00h Other display controller


00h 00h Video device

01h 00h Audio device

80h 00h Other multimedia device

CPCI 307

53


00h 00h Host/PCI bridge

01h 00h PCI/ISA bridge

02h 00h PCI/EISA bridge

03h 00h PCI/Micro Channel bridge

04h 00h PCI/PCI bridge

05h 00h PCI/PCMCIA bridge

06h 00h NuBus bridge

07h 00h CardBus bridge

80h 00h Other bridge type


00h 00h Generic XT compatible serial controller

01h 16450 compatible serial controller

02h 16550 compatible serial controller

01h 00h Parallel port

01h Bidirectional parallel port

02h ECP 1.X compliant parallel port

80h 00h Other communications device


00h 00h Generic 8259 PIC

01h ISA PIC

02h EISA PIC

01h 00h Generic 8237 DMA controller

01h ISA DMA controller

02h EISA DMA controller

02h 00h Generic 8254 system timer

01h ISA system timer

02h EISA system timers (2 timers)

03h 00h Generic RTC controller

01h ISA RTC controller

80h 00h Other system peripheral

CPCI 307

54


00h 00h Keyboard controller

01h 00h Digitizer (Pen)

02h 00h Mouse controller

80h 00h Other input controller


00h 00h Generic docking station

80h 00h Other type of docking station


00h 00h Intel386™

01h 00h Intel486™

02h 00h Pentium™

10h 00h Alpha™

40h 00h Co-processor


00 00h FireWire™ (IEEE 1394)

01h 00h ACCESS.bus

02h 00h SSA

CPCI 307

55

CACHE LINE SIZE REGISTER (CALN)Register Name: Cache Line SizeAddress Offset: 0ChPower-up value: 00h, hardwiredBoot-load: not usedAttribute: Read OnlySize: 8 bits

This register is hardwired to 0. The cache line con-figuration register is used by the system to define thecache line size in doubleword (64-bit) increments.This controller does not use the “Memory Write andInvalidate” PCI bus cycle commands when operatingin the bus master mode, and therefore does not inter-nally require this register. When operating in the tar-get mode, this controller does not have theconnections necessary to “snoop” the PCI bus andaccordingly cannot employ this register in the detec-tion of burst transfers that cross a line boundary.

7 000h

Cache Line Size (RO)

LATENCY TIMER REGISTER (LAT)Register Name: Latency TimerAddress Offset: 0DhPower-up value: 00hBoot-load: External nvRAM offset

04DhAttribute: Read/Write, bits 7:3;

Read Only bits 2:0Size: 8 bits

The latency timer register has meaning only whenthis controller is used as a bus master and pertains tothe number of PCI bus clocks that this master will beguaranteed. The nonzero value for this register isinternally decremented after this device has beengranted the bus and has begun to assert FRAME#.Prior to this latency timer count reaching zero, thisdevice can ignore the removal of the bus grant andmay continue the use of the bus for data transfers.

7 0

Latency Timer value (R/W)# of clocks x 8

0

1

0

2

0

3

X

4

X

5

X

6

XX

Bit

Value

CPCI 307

56

HEADER TYPE REGISTER (HDR)Register Name: Header TypeAddress Offset: 0EhPower-up value: 00hBoot-load: External nvRAM offset

04EhAttribute: Read OnlySize: 8 bits

This register consists of two fields: Bits 6:0 define theformat for bytes 10h through 3Fh of the device con-figuration header, and bit 7 establishes whether thisdevice represents a single function (bit 7 = 0) or amultifunction (bit 7 = 1) PCI bus agent. The S5933 isa single function PCI device.

7 0

Single/Multi-function device (Read Only)0 = single function1 = multi-function

123456

X

Bit

Value00h

Format field (Read Only)

CPCI 307

57

BUILT-IN SELF-TEST REGISTER (BIST)Register Name: Built-in Self-TestAddress Offset: 0FhPower-up value: 00hBoot-load: External nvRAM/EPROM

offset 04FhAttribute: D7, D5-0 Read Only, D6 as

PCI bus write onlySize: 8 bits

The Built-In Self-Test (BIST) register permits theimplementation of custom, user-specific diagnostics.This register has four fields as depicted in Figure 10.Bit 7, when set signifies that this device supports abuilt-in self test. When bit 7 is set, writing a 1 to bit 6will commence the self test. In actuality, writing a 1 tobit 6 produces an interrupt to the Add-On interface.Bit 6 will remain set until cleared by a write operationto this register from the Add-On bus interface. Whenbit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value forthe completion code (bits 3:0).

Bit Description

7 BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one isreturned. A zero should be returned if this self test feature is not desired. This field is read onlyfrom the PCI interface.

6 Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only bewritten when bit 7 is a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Otherthan through the reset pin, Bit 6 can only be cleared by a write to this element from the Add-On businterface as outlined in Section 6.5. The PCI bus specification requires that this bit be cleared within2 seconds after being set, or the device will be failed.

5:4 Reserved. These bits are reserved. This field will always return zeros.

3:0 Completion Code. This field provides a method for detailing a device-specific error. It is consideredvalid when the Start BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion codeindicates successful completion.

7 0

X

1

X

2

X

3

X

4

0

5

0

6

0X

Bit

Value

User definedCompletion Code (RO)

Reserved (RO)

Start BIST (WO)

BIST Capable (RO)

CPCI 307

58

BASE ADDRESS REGISTERS (BADR)Register Name: Base AddressAddress Offset: 10h, 14h, 18h, 1Ch, 20h, 24hPower-up value: FFFFFFC1h for offset 10h;

00000000h for all othersBoot-load: External nvRAM offset

050h, 54h, 58h, 5Ch, 60h(BADR0-4)

Attribute: high bits Read/Write; low bitsRead Only

Size: 32 bits

The base address registers provide a mechanism forassigning memory or I/O space for the Add-On func-tion. The actual location(s) the Add-On function is torespond to is determined by first interrogating theseregisters to ascertain the size or space desired, andthen writing the high-order field of each register toplace it physically in the system’s address space. Bitzero of each field is used to select whether the spacerequired is to be decoded as memory (bit 0 = 0) or I/O(bit 0 = 1). Since this PCI controller has 16 DWORDsof internal operating registers, the Base AddressRegister at offset 10h is assigned to them. The re-maining five base address registers can only be usedby boot-loading them from the external nvRAM inter-face. BADR5 register is not implemented and will re-turn all 0’s.

Determining Base Address SizeThe address space defined by a given base addressregister is determined by writing all 1s to a givenbase address register from the PCI bus and thenreading that register back. The number of 0s returnedstarting from D4 for memory space and D2 for I/Ospace toward the high-order bits reveals the amountof address space desired. Tables 23 and 24 list thepossible returned values and their corresponding sizefor both memory and I/O, respectively. Included inthe table are the nvRAM/EPROM boot values whichcorrespond to a given assigned size. A register re-turning all zeros is disabled.

Assigning the Base Address

After a base address has been sized as described inthe preceding paragraph, the region associated withthat base address register (the high order one bits)can physically locate it in memory (or I/O) space. Forexample, the first base address register returnsFFFFFFC1h indicating an I/O space (D0=1) and isthen written with the value 00000300h. This meansthat the controller’s internal registers can be selectedfor I/O addresses between 00000300h through0000033Fh, in this example. The base address valuemust be on a natural binary boundary for the requiredsize (example 300h, 340h, 380h etc.; 338h would notbe allowable).

31 0

X

1

0

2 Bit

Value

I/O Space Indicator (RO)Reserved (RO)

Programmable (R/W)

31 0

X

1

X

2

X

3

X

4 Bit

Value

Memory Space Indicator (RO)Type (RO) 00-locate anywhere (32) 01-below 1 MB 10-locate anywhere (64) 11-reserved

Programmable (R/W)

Prefetchable (RO)

CPCI 307

59

31:4 Base Address Location. These bits are used to position the decoded region in memory space. Onlybits which return a 1 after being written as 1 are usable for this purpose. Except for Base AddressRegister 0, these bits are individually enabled by the contents sourced from the external boot memory.

3 Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachableregions can only be located within the region altered through PCI bus memory writes. This bit, whenset, also implies that all read operations will return the data associated for all bytes regardless of theByte Enables. Memory space which cannot support this behavior should leave this bit in the zerostate. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by theexternal boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is readonly from the PCI interface.

2:1 Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the spacelocation is restricted to be within the first megabyte of memory space. The table below describes theencoding:

Bits Description2 10 0 Region is 32 bits wide and can be located anywhere in 32 bit memory space.

0 1 Region is 32 bits wide and must be mapped below the first MByte of memory space.

1 0 Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.(Not supported by this controller.)

1 1 Reserved. (Not supported by this controller.)

1 The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The onlymeaningful option is whether it is desired to position memory space anywhere within 32-bit memoryspace or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the resetpin and later initialized by the external boot memory (if present).

0 Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space andthe remaining bits in the base address register are defined as shown in Table 22a.

Bit Description

Bit Description

31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bitswhich return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,these bits are individually enabled by the contents sourced from the external boot memory (EPROMor nvRAM).

1 Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for theentire register location, bits 31 through 0).

0 Space Indicator = 1. When one this bit identifies a base address region as an I/O space and theremaining bits in the base address register have the definition as shown in Table 11b.

CPCI 307

60

Response Size in bytes [EPROM boot value] 1

00000000h none - disabled 00000000h orBIOS missing 2,3

FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFF0h

FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFE0h

FFFFFFC0h 64 bytes (16 DWORDs) FFFFFFC0h

FFFFFF80h 128 bytes (32 DWORDs) FFFFFF80h


FFFFFE00h 512 bytes (128 DWORDs) FFFFFE00h

FFFFFC00h 1K bytes (256 DWORDs) FFFFFC00h

FFFFF800h 2K bytes (512 DWORDs) FFFFF800h

FFFFF000h 4K bytes (1K DWORDs) FFFFF000h

FFFFE000h 8K bytes (2K DWORDs) FFFFE000h

FFFFC000h 16K bytes (4K DWORDs) FFFFC000h

FFFF8000h 32K bytes (8K DWORDs) FFFF8000h


FFFE0000h 128K bytes (32K DWORDs) FFFE0000h

FFFC0000h 256K bytes (64K DWORDs) FFFC0000h

FFF80000h 512K bytes (128K DWORDs) FFF80000h

FFF00000h 1M bytes (256K DWORDs) FFF00000h

FFE00000h 2M bytes (512K DWORDs) FFE00000h

FFC00000h 4M bytes (1M DWORDs) FFC00000h

FF800000h 8M bytes (2M DWORDs) FF800000h

FF000000h 16M bytes (4M DWORDs) FF000000h

FE000000h 32M bytes (8M DWORDs) FE000000h

FC000000h 64M bytes (16M DWORDs) FC000000h

F8000000h 128M bytes (32M DWORDs) F8000000h

F0000000h 256M bytes (64M DWORDs) F0000000h

E0000000h 512M bytes (128M DWORDs) E0000000h

1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.3. BADR5 register is not implemented and will return all 0’s.

CPCI 307

61

Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing 3

FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFFDh



FFFFFFE1h 32 bytes (8 DWORDs) FFFFFFE1h

FFFFFFC1h 64 bytes (16 DWORDs) FFFFFFC1h 4



4. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external bootmemory. Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h orFFFFFFC2h).

CPCI 307

62

EXPANSION ROM BASE ADDRESSREGISTER (XROM)

Register Name: Expansion ROM Base AddressAddress Offset: 30hPower-up value: 00000000hBoot-load: External nvRAM offset

70hAttribute: bits 31:11, bit 0 Read/Write; bits

10:1 Read OnlySize: 32 bits

31 0

00

110 Bit

Value

Address Decode Enable (RW) 0=Disabled 1=EnabledReserved (RO)Programmable (R/W)

11

The expansion base address ROM register providesa mechanism for assigning a space within physicalmemory for an expansion ROM. Access from the PCIbus to the memory space defined by this register willcause one or more accesses to the S5933 control-lers’ external BIOS ROM (or nvRAM) interface. SincePCI bus accesses to the ROM may be 32 bits wide,repeated operations to the ROM are generated bythe S5933 and the wider data is assembled internalto the S5933 controller and then transferred to thePCI bus by the S5933.

Bit Description

31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region inmemory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Thesebits are individually enabled by the contents sourced from the external boot memory (EPROM ornvRAM). The desired size for the ROM memory is determined by writing all ones to this register andthen reading back the contents. The number of bits returned as zeros, in order from least significantto most significant bit, indicates the size of the expansion ROM. This controller limits the expansionROM area to 64K bytes. The allowable returned values after all ones are written to this register areshown in Table 26.

10:1 Reserved. All zeros.

0 Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit.When this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is requiredthat the PCI command register also have the memory decode enabled for this bit to have an effect.

Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing

FFFFF801h 2K bytes (512 DWORDs) FFFFF801h

FFFFF001h 4K bytes (1K DWORDs) FFFFF001h

FFFFE001h 8K bytes (2K DWORDs) FFFFE001h

FFFFC001h 16K bytes (4K DWORDs) FFFFC001h



CPCI 307

63

INTERRUPT LINE REGISTER (INTLN)Register Name: Interrupt LineAddress Offset: 3ChPower-up value: FFhBoot-load: External nvRAM offset

7ChAttribute: Read/WriteSize: 8 bit

This register indicates the interrupt routing for theS5933 controller. The ultimate value for this registeris system-architecture specific. For x86 based PCs,the values in this register correspond with the estab-lished interrupt numbers associated with the dual8259 controllers used in those machines. In x86-based PC systems, the values of 0 to 15 correspondwith the IRQ numbers 0 through 15, and the valuesfrom 16 to 254 are reserved. The value of 255 (thecontroller’s default power-up value) signifies either“unknown” or “no connection” for the system inter-rupt. This register is boot-loaded from the externalboot memory, if present, and may be written by thePCI interface.

7 01

FFh

5 Bit

Value

6 4 23

INTERRUPT PIN REGISTER (INTPIN)Register Name: Interrupt PinAddress Offset: 3DhPower-up value: 01hBoot-load: External nvRAM offset

7DhAttribute: Read OnlySize: 8 bits

7 015 Bit

Value

6 4 23

0 0000 XXX

Reserved (all zeroes-RO)

Pin Number 0 0 0 None0 0 1 INTA#0 1 0 INTB#0 1 1 INTC#1 0 0 INTD# 1 0 1 Reserved1 1 X Reserved

This register identifies which PCI interrupt, if any, isconnected to the controller’s PCI interrupt pins. Theallowable values are 0 (no interrupts), 1 (INTA#), 2(INTB#), 3 (INTC#), and 4 (INTD#). The defaultpower-up value assumes INTA#.

CPCI 307

64

MINIMUM GRANT REGISTER (MINGNT)Register Name: Minimum Grant

Address Offset: 3EhPower-up value: 00hBoot-load: External nvRAM offset

7EhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how long a burst period the device needs.A value of zero indicates that the bus master has nostringent requirement. The units defined by the leastsignificant bit are in 250-ns increments. This registeris treated as “information only” and has no furtherimplementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

MAXIMUM LATENCY REGISTER (MAXLAT)

Register Name: Maximum LatencyAddress Offset: 3FhPower-up value: 00hBoot-load: External nvRAM offset

7FhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how often this device needs PCI bus ac-cess. A value of zero indicates that the bus masterhas no stringent requirement. The units defined bythe least significant bit are in 250-ns increments. Thisregister is treated as “information only” and has nofurther implementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

CPCI 307

65

PCI BUS OPERATION REGISTERS

Address Offset Abbreviation Register Name

00h OMB1 Outgoing Mailbox Register 1



0Ch OMB4 Outgoing Mailbox Register 4

10h IMB1 Incoming Mailbox Register 1



1Ch IMB4 Incoming Mailbox Register 4

20h FIFO FIFO Register port (bidirectional)

24h MWAR Master Write Address Register

28h MWTC Master Write Transfer Count Register

2Ch MRAR Master Read Address Register

30h MRTC Master Read Transfer Count Register

34h MBEF Mailbox Empty/Full Status

38h INTCSR Interrupt Control/Status Register

3Ch MCSR Bus Master Control/Status Register

PCI BUS OPERATION REGISTERSThe PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space(I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communi-cation between the PCI and Add-On buses. Data, software-defined commands and command parameters can beeither exchanged through the mailboxes, transferred through the FIFO in blocks under program control, ortransferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.

CPCI 307

66

OUTGOING MAILBOX REGISTERS (OMB)Register Names: Outgoing Mailboxes 1-4

PCI Address Offset: 00h, 04h, 08h, 0Ch

Power-up value: XXXXXXXXh

Attribute: Read/Write

Size: 32 bits

These four DWORD registers provide a method forsending command or parameter data to the Add-Onsystem. PCI bus operations to these registers maybe in any width (byte, word, or DWORD). Writing tothese registers can be a source for Add-On bus inter-rupts (if desired) by enabling their interrupt genera-tion through the use of the Add-On’s interrupt control/status register.

INCOMING MAILBOX REGISTERS (IMB)Register Names: Incoming Mailboxes 1-4

PCI Address Offset: 10h, 14h, 18h, 1Ch


Attribute: Read Only

Size: 32 bits

These four DWORD registers provide a method forreceiving user defined data from the Add-On system.PCI bus read operations to these registers may be inany width (byte, word, or DWORD). Only read opera-tions are supported. Reading from these registers canoptionally cause an Add-On bus interrupt (if desired)by enabling their interrupt generation through the useof the Add-On’s interrupt control/status register.

Mailbox 4, byte 3 only exists as device pins on theS5933 devices when used with a serial nonvolatilememory.

This location provides access to the bidirectionalFIFO. Separate registers are used when readingfrom or writing to the FIFO. Accordingly, it is not pos-sible to read what was written to this location. TheFIFO registers are implicitly involved in all bus masteroperations and, as such, should not be accessedduring active bus master transfers. When operatingupon the FIFOs with software program transfers in-volving word or byte operations, the sequenceof the FIFO should be established as described un-der FIFO Endian Conversion Management in order topreserve the internal FIFO data ordering and flagmanagement. The FIFO’s fullness may be observedby reading the master control- status registerorMCSR register.

FIFO REGISTER PORT (FIFO)

Register Name: FIFO Port

PCI Address Offset: 20h


Attribute: Read/Write

Size: 32 bits

CPCI 307

67

PCI CONTROLLED BUS MASTER WRITEADDRESS REGISTER (MWAR)Register Name: Master Write AddressPCI Address Offset: 24hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving from the Add-On bus to the PCI busduring PCI bus memory write operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MWTC, and must begin on a DWORD boundary.This DWORD boundary starting constraint is placedupon this controller’s PCI bus master transfers sothat byte lane alignment can be maintained betweenthe S5933 controller’s internal FIFO data path, theAdd-On interface, and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Write Address Register is continually up-dated during the transfer process and will always bepointing to the next unwritten location. Reading ofthis register during a transfer process (done when theS5933 controller is functioning as a target, i.e. not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master write transfers, the two leastsignificant bits presented on the PCI bus pinsAD[31:0] will always be zero. This identifies to thetarget memory that the burst address sequence willbe in a linear order rather than in an Intel 486 orPentium™ cache line fill sequence. Also, the PCI busaddress bit A1 will always be zero when this control-ler is the bus master. This signifies to the target thatthe S5933 controller is burst capable and that thetarget should not arbitrarily disconnect after the firstdata phase of this operation.

Under certain circumstances, MWAR can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Write Transfer Address (R/W)

CPCI 307

68

PCI CONTROLLED BUS MASTER WRITETRANSFER COUNT REGISTER (MWTC)Register Name: Master Write Transfer CountPCI Address Offset: 28hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master write transfer count register is used toconvey to the S5933 controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIwrite operation until the transfer count reaches zero.

Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MWTC can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = O's (RO)

26

00

CPCI 307

69

PCI CONTROLLED BUS MASTER READADDRESS REGISTER (MRAR)Register Name: Master Read AddressPCI Address Offset: 2ChPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving to the Add-On bus from the PCI busduring PCI bus memory read operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MRTC (Section 5.7) and must begin on a DWORDboundary. This DWORD boundary starting constraintis placed upon this controller’s PCI bus master trans-fers so that byte lane alignment can be maintainedbetween the S5933 controller’s internal FIFO datapath, the Add-On interface and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Read Address Register is continually up-dated during the transfer process and will always bepointing to the next unread location. Reading of thisregister during a transfer process (done when theS5933 controller is functioning as a target—i.e., not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master read transfers, the two leastsignificant bits presented on the PCI bus AD[31:0]will always be zero. This identifies to the targetmemory that the burst address sequence will be in alinear order rather than in an Intel 486 or Pentium™cache line fill sequence. Also, the PCI bus addressbit A1 will always be zero when this controller is thebus master. This signifies to the target that the con-troller is burst capable and that the target should notarbitrarily disconnect after the first data phase of thisoperation.

Under certain circumstances, MRAR can be ac-cessed from the Add-On bus instead of the PCI bus.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Read Transfer Address (R/W)

CPCI 307

70

PCI CONTROLLED BUS MASTER READTRANSFER COUNT REGISTER (MRTC)

Register Name: Master Read Transfer CountPCI Address Offset: 30hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master read transfer count register is used toconvey to the PCI controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIread operation until the transfer count reaches zero.Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MRTC can be ac-cessed from the Add-On bus instead of the PCI bus.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = 0's (RO)

26

00

CPCI 307

71

MAILBOX EMPTY FULL/STATUSREGISTER (MBEF)

Register Name: Mailbox Empty/Full Status

PCI Address Offset: 34h

Power-up value: 00000000h

Attribute: Read Only

Size: 32 bits

This register provides empty/full visibility of each bytewithin the mailboxes. The empty/full status for theOutgoing mailboxes is displayed on the low-order 16bits and the empty/full status for the Incoming mail-boxes is presented on the high-order 16 bits. A valueof 1 signifies that a given mailbox has been written byone bus interface but has not yet been read by thecorresponding destination interface. A PCI bus in-coming mailbox is defined as one in which data trav-els from the Add-On bus into the PCI bus, and anoutgoing mailbox is defined as one where data trav-els out from the PCI bus to the Add-On interface.

31 015 Bit

Value

Outgoing MailboxStatus (RO)Incoming Mailbox Status (RO)

16

CPCI 307

72

Bit Description

31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been writtenby the Add-On interface but have not yet been read by the PCI bus. Each bit location corre-sponds to a specific byte within one of the four incoming mailboxes. A value of one for each bitsignifies that the specified mailbox byte is full, and a value of zero signifies empty. The mappingof these status bits to bytes within each mailbox is as follows:

Bit 31 = Incoming mailbox 4 byte 3Bit 30 = Incoming mailbox 4 byte 2Bit 29 = Incoming mailbox 4 byte 1Bit 28 = Incoming mailbox 4 byte 0Bit 27 = Incoming mailbox 3 byte 3Bit 26 = Incoming mailbox 3 byte 2Bit 25 = Incoming mailbox 3 byte 1Bit 24 = Incoming mailbox 3 byte 0Bit 23 = Incoming mailbox 2 byte 3Bit 22 = Incoming mailbox 2 byte 2Bit 21 = Incoming mailbox 2 byte 1Bit 20 = Incoming mailbox 2 byte 0Bit 19 = Incoming mailbox 1 byte 3Bit 18 = Incoming mailbox 1 byte 2Bit 17 = Incoming mailbox 1 byte 1Bit 16 = Incoming mailbox 1 byte 0

15:00 Outgoing Mailbox Status. This field indicates which out going mail box registers have been writtenby the PCI bus interface but have not yet been read by the Add-On bus. Each bit location correspondsto a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies thatthe specified mailbox byte is full, and a value of zero signifies empty. The mapping of these statusbits to bytes within each mailbox is as follows:

Bit 15 = Outgoing mailbox 4 byte 3Bit 14 = Outgoing mailbox 4 byte 2Bit 13 = Outgoing mailbox 4 byte 1Bit 12 = Outgoing mailbox 4 byte 0Bit 11 = Outgoing mailbox 3 byte 3Bit 10 = Outgoing mailbox 3 byte 2Bit 09 = Outgoing mailbox 3 byte 1Bit 08 = Outgoing mailbox 3 byte 0Bit 07 = Outgoing mailbox 2 byte 3Bit 06 = Outgoing mailbox 2 byte 2Bit 05 = Outgoing mailbox 2 byte 1Bit 04 = Outgoing Mailbox 2 byte 0Bit 03 = Outgoing Mailbox 1 byte 3Bit 02 = Outgoing Mailbox 1 byte 2Bit 01 = Outgoing Mailbox 1 byte 1Bit 00 = Outgoing Mailbox 1 byte 0

CPCI 307

73

INTERRUPT CONTROL/STATUSREGISTER (INTCSR)

Register Name: Interrupt Control and StatusPCI Address Offset: 38hPower-up value: 00000000hAttribute: Read/Write (R/W),

Read/Write_One_Clear (R/WC)Size: 32 bits

This register provides the method for choosing whichconditions are to produce an interrupt on the PCI businterface, a method for viewing the cause of the inter-rupt, and a method for acknowledging (removing) theinterrupt’s assertion.

Interrupt sources:

• Write Transfer Terminal Count = zero

• Read Transfer Terminal Count = zero

• One of the Outgoing mailboxes (1,2,3 or 4)becomes empty

• One of the Incoming mailboxes (1,2,3 or 4)becomes full.

• Target Abort

• Master Abort

31 015 14 12 8 4 Bit

Value16212324

FIFO and Endian Control 0

Read TransferComplete (R/WC)

Write Transfer Complete (R/WC)

Incoming Mailbox Interrupt (R/WC)

Outgoing Mailbox Interrupt (R/WC)

Interrupt Asserted (RO)

Target Abort (R/WC)

Master Abort (R/WC)

0 0 0 0

D4-D0 Outgoing Mailbox (Goes empty)

D4=Enable Interrrupt

D3-D2=Mailbox #

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D1-D0=Byte #

0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

D12-D8 Incoming Mailbox (R/W)(Becomes full)

D12=Enable Interrupt

D11-D10=Mailbox

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D9-D8=Byte #0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

Interrupt on WriteTransfer Complete

Interrupt on ReadTransfer Complete

Interrupt Source (R/W)Enable & Selection

Actual Interrupt Interrupt Selection

CPCI 307

74

0011

0 NO CONVERSION (DEFAULT)1 16 BIT ENDIAN CONV.0 32 BIT ENDIAN CONV.1 64 BIT ENDIAN CONV

FIFO ADVANCE CONTROLPCI INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

FIFO ADVANCE CONTROLADD-ON INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7 (NOTE1)

INBOUND FIFO ADD-ON PCI DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7

NOTE 1: D24 and D25 MUST BE ALSO "1"

31 30 29 28 27 26 25 24

1

CPCI 307

75

Bit Description

31:24 FIFO and Endian Control.

23 Interrupt asserted. This read only status bit indicates that one or more of the four possible interruptconditions is present. This bit is nothing more than the ORing of the interrupt conditions describedby bits 19 through 16 of this register.

22 Reserved. Always zero.

21 Target Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa target abort during a PCI bus cycle while the S5933 was the current bus master. This bit operatesas read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a writeto this bit with the data of “zero” will not change the state of this bit.

20 Master Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI buscycle. This bit operates as read or write one clear. A write to this bit with the data of “one” will causethis bit be reset, a write to this bit with the data of “zero” will not change the state of this bit.

19 Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. Thisinterrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

18 Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. Thisinterrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

17 Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of thisregister are written by the Add-On interface. This bit operates as read or write one clear. A write tothis bit with the data of “one” will cause this bit to be reset; a write to this bit with the data as “zero”will not change the state of this bit.

16 Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this registeris read by the Add-On interface. This bit operates as read or write one clear. A write to this bit withthe data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not changethe state of this bit.

15 Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the readtransfer count reaches zero. This bit is read/write.

14 Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the writetransfer count reaches zero. This bit is read/write.


12 Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identifiedby bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write.

11:10 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to bethe source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

CPCI 307

76

9:8 Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]bselects byte 2, and [11]b selects byte 3. This field is read/write.

7:5 Reserved, Always zero.

4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailboxregister identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write.

3:2 Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be thesource for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2,[10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

1:0 Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selectsbyte 2, and [11]b selects byte 3. This field is read/write.

Bit Description

CPCI 307

77

MASTER CONTROL/STATUSREGISTER (MCSR)

Register Name: Master Control/StatusPCI Address Offset: 3ChPower-up value: 000000E6hAttribute: Read/Write, Read Only,

Write OnlySize: 32 bits

This register provides for overall control of this de-vice. It is used to enable bus mastering for both datadirections as well as providing a method to performsoftware resets.

The following PCI bus controls are available:

• Write Priority over Read

• Read Priority over Write

• Write Transfer Enable

• Write master requests on 4 or more FIFO wordsavailable (full)

• Read transfer enable

• Read master requests on 4 or more FIFOavailable (empty)

• Assert reset to Add-On

• Reset Add-On to PCI FIFO flags

• Reset PCI to Add-On FIFO flags

• Reset mailbox empty full status flags

• Write external non-volatile memory

The following PCI interface status flags are provided:

• PCI to Add-On FIFO FULL

• PCI to Add-On FIFO has four or more emptylocations

• PCI to Add-On FIFO EMPTY

• Add-On to PCI FIFO FULL

• Add-On to PCI FIFO has four or more wordsloaded

• Add-On to PCI FIFO EMPTY

• PCI to Add-On Transfer Count = Zero

• Add-On to PCI Transfer Count = Zero

31 29 27 24 23 014 12 10 8 7 6 515 Bit

Value

FIFO STATUS (RO)D5=Add-on to PCI FIFO EmptyD4=Add-on to PCI FIFO 4+ WordsD3=Add-on to PCI FIFO FullD2=PCI to Add-on FIFO EmptyD1=PCI to Add-on FIFO 4+SpacesD0=PCI to Add-on FIFO Full

D7=Add-on to PCI Transfer Countequals zero (R0)

D6=PCI to Add-on Transfer Countequals zero (R0)

160

Write Transfer Control (R/W)(PCI memory writes)

D10=Write Transfer EnableD9=FIFO Management SchemeD8=Write vs Read Priority

Reset Controls (R/WC)D27=Mailbox Flags ResetD26=Add-on to PCI FIFO Status Flags ResetD25=PCI to Add-on FIFO Status Flags ResetD24=Add-On Reset nv operation address/data

Memory Read MultipleEnable = 1Disable = 0

Read Transfer Control (R/W) (PCI memory reads)

D14=Read Transfer EnableD13=FIFO Management SchemeD12=Read vs. Write Priority

nvRAM Access Ctrl

0 0

Control Status

CPCI 307

78

Bit Description

31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatilememory. Write operations are achieved by a sequence of byte operations involving these bits and the8-bit field of bits 23 through 16. The sequence requires that the low-order address, high order address,and then a data byte are loaded in order. Bit 31 of this field acts as a combined enable and ready forthe access to the external memory. D31 must be written to a 1 before an access can begin, andsubsequent accesses must wait for bit D31 to become zero (ready).

D31 D30 D29 W/R

0 X X W Inactive

1 0 0 W Load low address byte

1 0 1 W Load high address byte

1 1 0 W Begin write

1 1 1 W Begin read

0 X X R Ready

1 X X R Busy

Cautionary note: The nonvolatile memory interface is also available for access by the Add-Oninterface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supportedby the S5933 device. Software must be designed to prevent the simultaneous access of nvmemory to prevent data corruption within the memory and provide for accurate data retrieval.

28 FIFO loop back mode.

27 Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY).It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Sincereading of this bit will always produce zeros, this bit is write only.

26 Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus mastermemory writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFOFour Plus word flag to reset. It is not necessary to write this bit as zero because it is used internallyto produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only.

25 PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Busmaster memory reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to resetand the FIFO Four Plus words available flag to set. It is not necessary to write this bit as zerobecause it is used internally to produce a reset pulse. Since reading of this bit will always producezeros, this bit is write only.

24 Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing azero to this pin is necessary to remove the assertion of reset. This register bit is read/write.

23:16 Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and29 of this register to access the external non-volatile memory. The contents written are either lowaddress, high address, or data as defined by bits 30 and 29. This register will contain the externalnon-volatile memory data when the proper read sequence for bits 31 through 29 is performed.

CPCI 307

79

Bit Description

15 Enable memory read multiple during S5933 bus mastering mode.

14 Read Transfer Enable. This bit must be set to a one for S5933 PCI bus master read transfers totake place. Writing a zero to this location will suspend an active transfer. An active transfer is onein which the transfer count is not zero.

13 Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevacant FIFO word.

12 Read versus Write priority. This bit controls the priority of read transfers over write transfers.When set to a 1 with bit D8 as zero this indicates that read transfers always have priority overwrite transfers; when set to a one with D8 as one, this indicates that transfer priorities willalternate equally between read and writes.


10 Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to takeplace. Writing a zero to this location will suspend an active transfer. An active transfer is one inwhich the transfer count is not zero.

9 Write FIFO management scheme. When set to a one this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more FIFO locations filled. Once the S5933 controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevalid FIFO word.

8 Write versus Read priority. This bit controls the priority of write transfers over read transfers.When set to a one with bit D12 as zero this indicates that write transfers always have priority overread transfers; when set to a one with D12 as one, this indicates that transfer priorities willalternate equally between writes and reads.

7 Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfercount is all zeros.

6 PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfercount is all zeros.

5 Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completelyempty.

4 Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid withinthe Add-On to PCI bus FIFO.

3 Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.

2 PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completelyempty.

1 PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words withinthe PCI to Add-On FIFO.

0 PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.

cpci 307 solated it...cpci 307 – rev. a – edition 1 – 23/25 5 chapter a presentation the cpci...

Documents