counters
DESCRIPTION
Lec 14TRANSCRIPT
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EET 3350 Digital Systems Design
Textbook: John WakerlyChapter 8: 8.4
Counters
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Counters• Counters
– Definition– Types– Characteristics
• Asynchronous Counters
- 7490, 7492, 7493• Synchronous Counters• MSI Counters
– Especially the 74LS163
• Counters in VHDL• Other Counter Types
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Clock Count
optional inputs
Counter
Sm
S1 S2S3
S4S5
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Counters
• A counter is a circuit that produces a numeric count each time an input clock pulse makes an active transition
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Clock Count
optional inputs
Counter
Load an initial value, reset Load an initial value, reset to starting count, etc.to starting count, etc.
May also enable count, May also enable count, select direction, etc.select direction, etc.
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Counter• From another viewpoint, a counter is any sequential
circuit whose state diagram is a single cycle– in other words, counters are a special case of a finite state
machine
• Output is usually the state value, Moore machine
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Sm
S1 S2S3
S4
S5
EN EN
EN
ENEN
EN
RESET
EN
EN
EN EN
EN
ENEN
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Counters
Characteristic Description
Modulus Length of sequence
Coding Count sequence
Direction Up or down
Resetable Reset to zero
Loadable Load a specific value
• Counters differ by a number of basic characteristics, including:
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Counters
• Applications include:– system clock– timer, delays– watches, clocks, alarms– counting events– memory addressing – frequency division – sequence control– cycle control– protocols
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Present State Next State A B A B
0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
00 01
1011
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Counter Types
• Asynchronous– Ripple
• Synchronous– Clocked
• Modulus – Binary– Decade – etc.
• Ring • Johnson
– Twisted ring
• Up/Down• Linear Feedback Shift-
Register Counter (LFSR)
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001
010
011
100
101
000
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Counters
• Some examples of modulus and coding sequence for counters
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Counters
• Modulus– number of states in a counter’s cycle
• Given m states– modulo-m counter or divide-by-m counter
• Power-of-2 counters use all states• Non-power-of-2 counters have extra, unused
states
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Sm
S1 S2S3
S4
S5
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Example 4-bit Counters
• 4-bit Binary / Hex / Mod-16 Counter– 0000, 0001, 0010, … 1110, 1111, 0000, 0001, …
• 4-bit BCD / Decade / Mod-10 Counter– 0000, 0001, 0010, … 1000, 1001, 0000, 0001, …
• 4-bit Ring Counter– 1000, 0100, 0010, 0001, 1000, 0100, …
all states used
six unused states
twelve unused states
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Counters
• Ripple counters– asynchronous– an n-state counter that is formed from n cascaded
flip-flops – the clock input to each of the individual flip-flops,
with the exception of the first, is taken from the output of the preceding one
– the count thus ripples along the counter's length due to the propagation delay associated with each stage of counting
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Asynchronous Ripple Counter
Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
Q0
Q1
Q2
Q3
...
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Ripple Counter Timing• The ideal count sequence for the ripple counter
yields the timing diagram below
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Q0
Q1
Q2
Q3
Q0 Q1 Q2 Q3
CLOCK
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Ripple Counter Timing
CLK
Q0
0 1 2 3 4
1
2
3Q2
Q1
• But there is delay ( ) as shown below:
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Asynchronous Ripple Counter
Q0
Q1
Q2
Q3
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divide-by-2
divide-by-4
divide-by-8
divide-by-16
a T flip-flop is a a T flip-flop is a natural frequency natural frequency divider …divider …
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Decade and Binary Counters
• The monolithic counter contains four masterslave flip-flops • Gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five.• The counter has a gated zero reset and also has gated set-to-nine inputs for use in BCD nine’s complement applications.• To use the maximum count length (decade), the B input is connected to the QA output. • The input count pulses are applied to input A and the outputs are as described in the appropriate Function Table. • A symmetrical divide-by-ten count can be obtained from the counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.
DM7490A
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Connection Diagram
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Function Tables
BCD Count Sequence (Note 1) BCD Bi-Quinary (Note 2)
H = HIGH LevelL = LOW LevelX = Don’t CareNote 1: Output QA is connected to input B for BCD count.Note 2: Output QD is connected to input A for bi-quinary count
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CLK
QA
QB
QC
QD
0 1 2 3 4 8 9 10 11 12 0
BCD Bi-Quinary sequence
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Reset/Count Function Table
H = HIGH LevelL = LOW LevelX = Don’t Care
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Logic Diagram
The J and K inputs shown without connection are for reference only andare functionally at a HIGH level.
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SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
Logic Symbols
The three-stage binary counter has the count cycle length of divide-by-five for the ’90, divide-by-six for the ’92, and divide-by-eight for the ’93.
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Function TablesCount Sequence for ’92
H = HIGH Level, L = LOW Level, X = Don’t CareNote: Output QA is connected to input CKB.
Count Sequence for ’93
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Reset/Count Function Table
H = HIGH LevelL = LOW LevelX = Don’t Care
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Logic Diagrams
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CLK A
CLK B
R0(1)
R0(2)
QA
QB
QC
QD
Clock
7493
Mod 11 counter using 7493
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Synchronous Counters
• Asynchronous counters are easy to understand, but avoid their use– slow, limited by propagation delays– error prone
• Characteristics of synchronous counters– use a common clock pulse to trigger all flip-flops
simultaneously– have a higher clock speed– hardware is more complex but more reliable
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LSB
MSB
Synchronous counter
serial enable logic
4-Bit Counter
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Synchronous counter
LSB
MSB
parallel enable logic
4-Bit Counter
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MSI Counters
• Counters can be built from individual SSI Flip-Flops, e.g.,– 7470– 7474– 7479
• Counters may also be built using MSI components– 74x90, 74x92, 74x93– 74x160, 74x161, 74x162, 74x163– 74x168, 74x169– 74x190, 74x191– 74x196, 74x197
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and many others …
74x163
we’ll look at this onewe’ll look at this one
D1 D2
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MSI Counter
• 4-bit synchronous counter– edge-triggered– synchronously
presettable– cascadable
• Typical Count Rate of 35 MHz
• ‘160 and ‘162, Mod-10• ‘161 and ‘163, Mod-16
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MSI Counter
• 74LS163 4-bit synchronous counter
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16-pin DIP16-pin DIP
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MSI Counter
• 74LS163 characteristics– edge-triggered– synchronously presettable– cascadable– count modulo 16 (binary)
• Synchronous Reset (Clear) input that overrides all other control inputs– active only during the rising
clock edge
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74x163
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MSI Counter
• 74LS163 logic symbols
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74x163texttext
datasheetdatasheet
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MSI Counter
• 74LS163 state diagram and logic equations
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MSI Counter
• 74LS163 mode select table• All signals must be high ( H ) to enable the
count sequence to begin
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MSI Counter• 74x163 is a synchronous
4-bit binary counter• RCO=1 when all count
bits are 1 and ENT is asserted
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MSI Counter
• The control inputs for the 74x163 have the following effects:
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clear
loadhold
hold
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74x163 Internal Logic
Diagram