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ECE261 CMOS VLSI Design Final Project Report

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December 3, 2009

©Copyright reserved

Duke University


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Table of content 1 Introduction ................................................................................................................................... 4

1.1 Project Function .................................................................................................................... 4

1.2 Performance Estimation ....................................................................................................... 6

1.3 System Power Consumption ................................................................................................ 7

2 Sub- circuit Design ........................................................................................................................ 7

2.1 D-flipflop ................................................................................................................................ 7

2.2 JK-flipflop .............................................................................................................................. 9

2.3 JK-flipflop with reset function .............................................................................................. 11

2.4 0-5 counter .......................................................................................................................... 13

2.5 0-9 counter .......................................................................................................................... 15

2.6 0-9 counter with reset function ........................................................................................... 18

2.7 4-7 segment decoder .......................................................................................................... 20

3 Full system design ...................................................................................................................... 23

3.1 Logic implementation .......................................................................................................... 23

3.2 Layout ................................................................................................................................. 26

3.3 Simulation ........................................................................................................................... 27

4 References ............................................................................................................................. 3030


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List of Figures Figure 1-1 system block diagram ......................................................................................................... 5

Figure 1-2 System Layout Floor Plan ................................................................................................... 6

Figure 2-1 schematic of D-flipflop ......................................................................................................... 8

Figure 2-2 layout of D-flipflop ............................................................................................................... 8

Figure 2-3 ELDO simulation of D-flipflop .............................................................................................. 9

Figure 2-4 schematic of JK-flipflop ..................................................................................................... 10

Figure 2-5 layout of JK-flipflop ............................................................................................................ 10

Figure 2-6 ELDO simulation of JK-flipflop .......................................................................................... 11

Figure 2-7 schematic of JK-flipflop with reset function ....................................................................... 12

Figure 2-8 layout of JK-flipflop with reset function .............................................................................. 12

Figure 2-9 ELDO simulation of JK-flipflop with reset function ............................................................ 13

Figure 2-10 schematic of 0-5 counter ................................................................................................. 14

Figure 2-11 layout of 0-5 counter ....................................................................................................... 14

Figure 2-12 ELDO simulation of 0-5 counter ...................................................................................... 15

Figure 2-13 schematic of 0-9 counter ................................................................................................. 16

Figure 2-14 layout of 0-9 counter ....................................................................................................... 17

Figure 2-15 ELDO simulation of 0-9 counter ...................................................................................... 18

Figure 2-16 schematic of 0-9 counter with reset function................................................................... 19

Figure 2-17 layout of 0-9 counter with reset function ......................................................................... 19

Figure 2-18 ELDO simulation of 0-9 counter with reset function ........................................................ 20

Figure 2-19numerical designation and display ................................................................................... 20

Figure 2-20 7 segment identification .................................................................................................. 20

Figure 2-21 schematic of 4-7 segment decoder ................................................................................. 22

Figure 2-22 layout of 4-7 segment decoder ....................................................................................... 22

Figure 2-23 ModelSIM simulation of 4-7 segment decoder ............................................................... 23

Figure 3-1 flow chart of full system ..................................................................................................... 24

Figure 3-2 top view schematic ............................................................................................................ 25

Figure 3-3 top view layout .................................................................................................................. 26

Figure 3-4 topview layout DRC clean ................................................................................................. 27

Figure 3-5 topview layout LVS clean .................................................................................................. 27

Figure 3-6 top view simulation (part I) ................................................................................................ 28

Figure 3-7 top view simulation (part II) ............................................................................................... 29

Figure 3-8 top view simulation (part III) .............................................................................................. 30


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1 Introduction

1.1 Project Function

In this project, we have built a digital clock with 12 hour count time. The clock runs from 00:00 to 11:59 and then back to 00:00. Our display has four digits, two digits for minutes and two for hour. The specialty of this clock is that it has very low power consumption and condensed layout.

We have used a simple 0-9 counter for the unit’s digit of minutes display and a 0-5 counter for the ten’s digit of minute. For the unit’s digit of hour, a resettable 0-9 counter has been used, and for the ten’s digit of hour a resettable JK-flipflop has been used. Other than this, a few NAND gates and D-flipflops have been used to ensure proper functioning of the clock.

There is only one input for the entire system: the clock input into the 0-9 counter used for the unit’s digit of minute. The clock inputs for the other blocks are derived from the output of the previous blocks as shown in the block diagram for the system. We have a total of 12 outputs: 4 outputs for unit’s digit of minute, 3 outputs for ten’s digit of minute, 4 outputs for unit’s digit of hour and 1 output for the ten’s digit of hour.

Besides, we have also designed a 4-7 segment decoder which can be used for the actual display of digits as we see on a real digital clock. We have kept the decoder separate from the top view of the schematic because it makes it difficult to view the output in binary form using the 4-7 segment display. However, if we do the actual hardware implementation, then we can use 4 such decoders, and connect the outputs of each of the four blocks (0-9 counter, 0-5 counter, resettable 0-9 counter and resettable JK-flipflop) to the inputs of the respective decoder and display time. The outputs of the decoders would be connected to LEDs and would make the LED glow for a high output and vice-versa for a low output.

Every 10 minutes, we add one on the ten’s digit of minute. After every 6 such cycles, we add one on the unit’s digit of hour, and every 10 hours, we add one on tens digit of hour. As soon as it reaches 1 on the ten’s digit of hour and 2 on unit’s digit of hour, both the ten’s and the unit’s digit of hour are reset to 0. So, in practice, we do not see 12:00 displayed. We rather see a transition from 11:59 to 00:00.

The block diagram of the system is shown in Figure 1-1 and the layout floor plan has been shown in Figure 1-2.


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Figure 1-1 system block diagram


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Figure 1-2 System Layout Floor Plan

1.2 Performance Estimation

An estimate of the total number of transistors used in our sub-blocks and the whole system is shown in Table 1.

Blocks in Top view No. of transistors in sub-block

No. of sub-block needed in top-view

Area of sub-block (µm2)

Inverter 2 3 262.5

NAND2 4 4 350

D flipflop 18 2 2450

Resettable JK flipflop 42 1 6750

0-5 Counter 132 1 14700

0-9 Counter 178 1 19240

Resettable 0-9 Counter 188 1 44000

4-7 Decoder 160 4 15600 Table 1: Summary of transistor number and area


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From this, we have calculated the total number of transistors and total area as-

Total number of transistors: 1238

Total area: 195650 µm2

1.3 System Power Consumption

Dynamic power consumption

Frequency used for simulation: 1Hz

Power consumption at 1Hz frequency: 11.3764 nW

Actual clock frequency required: 1/60 Hz

Scaled Power Consumption at 1/60 Hz: 0.1896 nW

Static power consumption

Usually static power consumption is one tenth of dynamic power consumption,

Thus, Static power consumption: 0.02nW

2 Sub- circuit Design

2.1 D-flipflop

We use D-flipflops in the main digital block connection, in order to create a delay to match the time flow. While D-flipflop is a common block in design, we briefly introduce the function of D-flipflop.

The Q output always takes on the state of the D input at the moment of a rising clock edge (or falling edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.

Clock D Q Qprev

Rising edge 0 0 X

Rising edge 1 1 X

Non-Rising X Qprev Table 2 D-flipflop truth table

The schematic and layout of D-flipflop are shown in Figure 2-1 schematic of D-flipflop and Figure 2-2, in this design, we used 5 inverters and 4 transmission gates. The ELDO analog simulation result can be seen in Figure 2-3.


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Figure 2-1 schematic of D-flipflop[1]

Figure 2-2 layout of D-flipflop

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Figure 2-4 schematic of JK-flipflop

Figure 2-5 layout of JK-flipflop


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Figure 2-6 ELDO simulation of JK-flipflop

2.3 JK-flipflop with reset function

In the design of HOUR part of our digital clock, we use JK-flipflop with reset function, to reset the output to 0 when the time reaches 12, while we just use JK-flipflop without reset function in MINUTE part.

The basic function of JK-flipflop with reset function is the same as JK-flipflop, except we add the clear function. But in order to implement this function, we designed another schematic. Reset input is independent from J and K and clock, so this is an asynchronous reset JK-flipflop. This JK-flipflop is substantially based on a D-flipflop, and in the input stage, we change the input for reset function.

The schematic and layout of JK-flipflop with reset function are shown in Figure 2-4 and Figure 2-5, in this design, we used 7 inverter, 5 NAND2 gates and 4 transmission gates. After all, the ELDO analog simulation result can be seen in Figure 2-6.


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Figure 2-7 schematic of JK-flipflop with reset function

Figure 2-8 layout of JK-flipflop with reset function


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Figure 2-9 ELDO simulation of JK-flipflop with reset function

2.4 0-5 counter

Here, a 0-5 counter acts as a digital output for ten’s digit of minute. The basic idea of implementation of 0-5 counter is based on JK-flipflop to ripple the digits. Digits start from 000, when they reach 101(5 in decimal) and then return to 000. The truth table of 0-5 counter is shown below

OUTPUT COUNT

C B A

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

1 0 1 5

The schematic and layout of 0-5 counter are shown in Figure 2-10and Figure 2-11, in this design, we used 3 JK flipflops, 3 inverters, and 3 NAND2 gates. In layout, in order to fit the floor plan, we designed it not in a rectangular shape.


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Figure 2-10 schematic of 0-5 counter

Figure 2-11 layout of 0-5 counter

The ELDO analog simulation result can be seen in Figure 2-12. We can see that the counter starts from 000 to 101 and returns to 000.


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Figure 2-12 ELDO simulation of 0-5 counter

2.5 0-9 counter

0-9 counter is a larger version of 0-5 counter. Here, 0-9 counter acts as a digital output for units of minute. The basic idea of implementation of 0-9 counter is also based on JK-flipflop to ripple the digits. Digits start from 0000, when they reach 1001(9 in decimal) and then return to 0000. The truth table of 0-9 counter is shown below < Reference used for schematic was http://www.play-hookey.com/digital/decimal_counter.html>

OUTPUT COUNT

D C B A

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9


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Table 3 0-9 counter truth table

The schematic and layout of 0-9counter are shown in Figure 2-13and Figure 2-14, in this design, we used 4 JK flipflops, 1 inverter, 3 NAND2 gates and 1 NAN3 gate.

Figure 2-13 schematic of 0-9 counter


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Figure 2-14 layout of 0-9 counter

ELDO analog simulation result can be seen in Figure 2-15. We can see that the counter starts from 0000 to 1001 and returns to 0000.


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Figure 2-15 ELDO simulation of 0-9 counter

2.6 0-9 counter with reset function

Implementation of 0-9 counter is also based on JK-flipflop with reset function to ripple the digits. Digits start from 0000, when they reach 1001(9 in decimal) and then return to 0000 normal. But it will be reset when input a reset signal, which is usually in the second round of counting and reset at 0010. The truth table of 0-9 counter with reset function is the same as the truth table of 0-9 counter.

Here is a concern that the reset function is asynchrony, so we design the reset signal at the edge of 11-12, thus there is a transient spike during the process. But the delay time of this spike is in the order of nanosecond level, and this signal is trigger in HOUR level. So we can neglect this spike in the operation of our project.

The schematic and layout of 0-9counter with reset function are shown in Figure 2-16Error! Reference source not found.Figure 2-4 and Figure 2-17. In this design, we used 4 JK-flipflops with reset function, 1 inverter, 3 NAND2 gates and 1 NAN3 gate.


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Figure 2-16 schematic of 0-9 counter with reset function

Figure 2-17 layout of 0-9 counter with reset function

ELDO analog simulation result can be seen in Figure 2-18. We can see that the counter starts from 0000 to 1001 and returns to 0000. We gave a reset signal during the operation, all digits are set to 0 immediately.


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Figure 2-18 ELDO simulation of 0-9 counter with reset function

2.7 4-7 segment decoder

Here, a 4-7 segment decoder is used for output binary digits of MUNITEs and HOURs in LEDs display. Normally, LEDs display has the function as follows, and we usually use the previous 10 output from 0 to 9.

Figure 2-19numerical designation and display

Figure 2-20 7 segment identification

To implement this function, we generate the truth table for a 4-7 segment decoder as below and get its corresponding 7 segment output and annotate them in decimal.


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DECIMAL OR

FUNCTION

INPUTS OUTPUTS

D C B A ~BI a b c d e f g

0 L L L L H 0 H H H H H H L 63

1 L L L H H 1 L H H L L L L 6

2 L L H L H 2 H H L H H H H 91

3 L L H H H 3 H H H H L L H 79

4 L H L L H 4 L H H L L H H 102

5 L H L H H 5 H L H L H H H 109

6 L H H L H 6 L L H H H H H 124

7 L H H H H 7 H H H L L L L 7

8 H L L L H 8 H H H H H H H 127

9 H L L H H 9 H H H L L H H 103

10 H L H L H 10 L L L H H L H 88

11 H L H H H 11 L L H H L L H 76

12 H H L L H 12 L H L L L H H 98

13 H H L H H 13 H L L H L H H 105

14 H H H L H 14 L L L H H H H 120

15 H H H H H 15 L L L L L L L 0

BI X X X X L X L L L L L L L 0 Table 4 4-7 segment decoder truth table

The schematic and layout of a 4-7 segment decoder are shown in Figure 2-20Error! Reference source not found.Figure 2-4 and Figure 2-22. In this design, we used 12 inverters, 14 NAND2 gates, 13 NAN3 gates and 1 NAND4 gate.


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Figure 2-21 schematic of 4-7 segment decoder

Figure 2-22 layout of 4-7 segment decoder

ModelSIM digital simulation result can be seen in Figure 2-23. We can see that the different input from 0000 to 1111 correspond to different output according to the truth table in Table 1, thus verifying our design.


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Figure 2-23 ModelSIM simulation of 4-7 segment decoder

3 Full system design

3.1 Logic implementation

The input to the system is the clock input into the 0-9 counter used for the unit’s digit of minute. Every 10 minutes, one is added to the ten’s digit of minute. After every 6 such cycles, i.e. every 60 minutes, one is added to the unit’s digit of hour, and every 10 hours, one is added to the ten’s digit of hour. As soon as it reaches 1 on the ten’s digit of hour and 2 on unit’s digit of hour, both the ten’s and the unit’s digit of hour are reset to 0. The flowchart for this is shown below.


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Figure 3-1 flow chart of full system

We implemented the function shown in Figure 3-1, and include all the sub-blocks we set up before, draw the top view schematic as below, and then top view layout Figure 3-3.


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Figure 3-2 top view schematic


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3.2 Layout

Figure 3-3 top view layout

Here is our DRC and LVS check result


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Figure 3-4 topview layout DRC clean

Figure 3-5 topview layout LVS clean

3.3 Simulation

In the top view simulation, we can simultaneously look at all the 12 outputs. These have been shown in the three following figures. In the first figure, we can see all the four bits of


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the unit digit of minute, and two of the three bits of ten’s digit of minute. If we look at MU1, MU2, MU3 and MU4, counting starts from 0, goes up till 9, and then again goes back to 0 and so on. At every transition from 9 to 0, a clock pulse is sent to the ten’s digit of minute, i.e., to the 0-5 counter. So, as soon as MU4 transitions from high to low, we can see a transition in MT1 as well. MT1, MT2 and MT3 form the three bits of the ten’s digit of minute. These start counting from 0, go up till 5, and then again go back to zero. This counting from o to 5 and back to zero can be clearly seen in the second figure.

Figure 3-6 top view simulation (part I)

In this figure, we can clearly see the ten’s digit of minute and the transition on the unit digit of hour after sixty minutes elapse. As long as both MT3 and MT1 are high, the time that is displayed on the minute part of the clock varies from 50 to 59. After this, all the bits in the minute display become zero, and a clock pulse is sent to the 0-9 counter which is used for the unit digit of hour. So, every time MT3 transitions from high to low, there is a transition in HU1.


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Figure 3-7 top view simulation (part II)

In this figure, we can see the both the unit and the ten’s digit of hour. HU1, HU2, HU3 and HU4 together make up the unit digit of hour, and HT1 is for the ten’s digit. HU1, HU2, HU3 and HU4 count from 0 to 9 and then go back to 0 again. As soon as the transition from 9 to 0 takes place, a clock pulse is sent to the resettable JK-flipflop used for the ten’s digit display of hour. This stays high for one complete clock period on HU1, and then all the bits in HOUR display become zero (except for a spike in HU2 which is too short to be noticed in practice). A high pulse on HT1 and a simultaneous low and then high on HU1, while HU2 and HU3 stay low, implies display ‘10’ and ‘11’ on the hour digits. After 11, the hour display shows 00 since all of the bits, HU1, HU2, HU3 and HU4 become 0. For as long as there is a zero on HU1 or a 1 on HU1, the minutes digit would count from 00 to 59. Thus, overall the clock would display from00:00 to 11:59 and back to 00:00.


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Figure 3-8 top view simulation (part III)

4 References [1] N. H. E. Weste and D. Harris, CMOS VLSI design : a circuits and systems perspective:

Boston : Pearson/Addison-Wesley, c2005.

[2] TI, system on chip: sn74ls47, BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS,1998

[3] ST, system on chip: M74HC107, DUAL J-K FLIP FLOP WITH CLEAR,2000

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