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September 2013 Doc ID 024080 Rev 3 1/38
RM0345Reference manual
SPC563M64CAL144calibration adapter board for SPC563M64xx devices
IntroductionThe SPC563M64CAL144 (rev.B) system is designed to enable the use of new enhanced automotive calibration and debug tools on the SPC563M64xx family of automotive microcontrollers.
The SPC563M64CAL144 (rev.B) can be fitted onto the application printed circuit board (PCB) in place of the standard SPC563M64xx family microcontroller in LQFP144 package. SPC563M64CAL144 (rev.B) hardware is designed to support two standardized tool connectors, allowing a variety of calibration and debug hardware to be connected and reused
Figure 1. SPC563M64CAL144 (rev.B)
Table 1. Board summary
Order code On board device Target footprint
SPC563M64CAL144 SPC563M64xx QFP144
www.st.com
Contents RM0345
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Contents
1 Calibration system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Reset and configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Calibration bus interface and External Memory . . . . . . . . . . . . . . . . . . 12
4.1 External memory specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 SRAM supply and data retention function . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Calibration bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Development connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Calibration connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Tool IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9 Calibration software compatibility and configuration . . . . . . . . . . . . . 22
9.1 Calibration bus sw configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.1 Cal Bus PCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.2 Cal Bus ECCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1.3 Cal Bus EBI Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2 Example Configuration CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Appendix A Calibration base footprints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Appendix B Mechanical constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Appendix C Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Appendix D Options placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RM0345 Contents
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of tables RM0345
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List of tables
Table 1. Board summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Table 2. J15, J2 and J14 option cut traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 3. Reset and configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 4. J11 configuration of SRAM supply for retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 5. J3, J5 and J10 option cut traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 6. Nexus signals on AMP 38 Mictor connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 7. Nexus signals on AMP 38 Mictor connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 8. J12, J13 FlexCAN interface selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 9. J6, J17 and J7 FlexCAN interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 10. CAN transceiver operating voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 11. Calibration bus signals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 12. EBDF field definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 13. EBI_MCR register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 14. EBI_CAL_BRx register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 15. EBI_CAL_BOx register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RM0345 List of figures
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List of figures
Figure 1. SPC563M64CAL144 (rev.B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2. Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 3. Supply signals from the QFP144 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 4. Test points on J4 connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 5. Supply signals on SPC563M64xx CSP496 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 6. SRAM supply circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 7. SRAM schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 8. JP1 development connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 9. AMP 38 Mictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 10. J9 Calibration connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 11. Calibration triggers TOOL_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 12. CAN schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 13. TQPACK144SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 14. Top and side view drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 15. Side and bottom view drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 16. Complete system side view drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 17. SPC563M64xx in CSP package schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 18. Polypod-TQ144 connector schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 19. Memory, CAN and connectors schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 20. Options placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Calibration system overview RM0345
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1 Calibration system overview
The Calibration Adapter board features 2 Mbytes of SRAM in order to substitute to the SPC563M64xx internal Flash during calibration.
A voltage regulator is also integrated upon the board to generate, from selectable 5 V source, the 3.3 V voltage for the RAM and the calibration bus interface.
Development connector (Mictor AMP38) is providing the interface for the debug and trace tools.
A calibration connector (ERNI 154819) is providing an interface optimized for calibration usage.
A high speed CAN transceiver is connected to the FlexCAN of the mcu device.
The components chosen in the design of this board are automotive qualified to allow system evaluation over the full automotive evaluation range (-40 °C to 125 °C).
1.1 Features overview calibration systems include these distinctive features:
● Use 100% production silicon, ensuring full hardware and software compatibility between production and calibration systems;
● Support LQFP144 MCU production package allowing calibration systems to be built without requiring modifications to the standard production system housing;
● 2MByte static RAM organized as 1024K words by 16 bits;
● On-board latch providing a 16-bit de-multiplexed bus interface from the SPC563M64xx 16-bit multiplexed calibration interface;
● Support for Nexus-based debug tools even if application PCB does not include Nexus connector;
● Nexus functionality with 12 Message Data Out (MDO) signals;
● Support for full-feature calibration tools, via availability of comprehensive set of device signals available on the connectors;
● ERNI 154819 connector optimized for calibration;
● High speed CAN transceiver with signals protection;
● Allows system calibration without impacting standard MCU I/O resources;
● Allows system calibration regardless of availability of standard MCU external bus;
● Uses tried and tested technology.
RM0345 Power supply
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2 Power supply
The Calibration boards requires a +5 V to supply the on board CAN transceiver and a +3.3 V to supply the SPC563M64xx calibration bus interface and for the external RAM.
The 3.3 V supply is generated on the SPC563M64CAL144 (rev.B) via the very low drop voltage regulator by using the +5V. A LED (D1) will light when the board is powered.
Figure 2. Power supply
By default the 5V is taken from the target application through the VDDREG supply level (supply input for the internal voltage regulators of the SPC563M64xx). Gauge J14 enables the powering from the application board. Table 2 shows its option configuration.
In case that no additional power loading could be applied to the application system during calibration, the +5V can be supplied externally via J4 connector (+5V test point, see Figure 4) and the gauge J14 (see Figure 3) must be open.
Power supply RM0345
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Figure 3. Supply signals from the QFP144 footprint
Figure 4. Test points on J4 connector
All power signals and voltage references of the SPC563M64xx QFP144 footprint from the application board are directly connected to the respective calibration device signals.
The VDDE12 supply used to power the dedicated SPC563M64xx calibration bus interface is connected to the upon board +3.3 V voltage regulator.
VSSAVSSSYN
GND
VRCCTL
VDDREG
VSTBY
C46
1uF
GND
VDDEH1.A 24
VDDEH1B 34
VDDEH1C 46
VDDEH4 61
VDDEH6A 78
VDDEH6B 93
VDDEH7 102
VDDEH7 113
VDDPLL 74
VDDREG 10
VRC33 13
VRCCTL 11
VSSPLL 77
VSSA0 7
VSTBY 12
VDDA0 6
VSUP 79 VDDA0
VDDSYNDefault = CL
J15
J14Default = CLOSE
+5V
VDDE H1BVDDE H 6A
VDDEH7
VDDEH6A
VDDEH1AVDDEH1B
VDDEH6B
QF
P14
4 fo
otpr
int
GAPGRI00341
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Figure 5. Supply signals on SPC563M64xx CSP496
The VRC33 signal of the CSP496 is connected to its respective signal of the QFP144 target application via the J15 cut trace option.
The VRC33 can be also connected to the on board +3.3V by closing the J2 gauge. In this case the gauge J15 must be open (Table 2).
Power supply RM0345
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Table 2. J15, J2 and J14 option cut traces(1)
1. Refer to Chapter Appendix D: Options placement for layout Jumper placement
Option name
Function Value Note
J15 VRC33
openVRC33 signal is disconnected from the target application board
close(default)
VRC33 signal is connected to the target application board
J2 VRC33
open(default)
VRC33 signal is disconnected from the on board +3.3V signal
closeVRC33 signal is connected to the on board +3.3V signal
J14 +5V supply
open +5V is powered from J4 connector
close(default)
+5V is powered from target application via VDDREG pin of the QFP144 target footprint
RM0345 Reset and configuration signals
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3 Reset and configuration signals
Calibration and debug tools may use the reset signals included in the connectors to have visibility of when the SPC563M64xx device has been reset. Debug tools may also require the ability to force device reset.
All signals of the SPC563M64xx QFP144 footprint from the application board are directly connected to the respective calibration device signals. This includes the following signals on the Table 3.
Table 3. Reset and configuration signals
Signal name Function Notes
Reset / Configuration (5)
/RESET External reset input
The /RESET pin is an active low input. The RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the device is in reset causes the reset cycle to start over.
/RSTOUT External reset output
The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the RSTOUT pin.
BOOTCFG[1] Boot configuration input
The BOOTCFG field holds the value of the BOOTCFG[1] pin that was latched on the last negation of the RSTOUT pin. The BOOTCFG field is used by the BAM program to determine the location of the Reset Configuration Word.
PLLREF FMPLL Mode Selection
PLLREF is used to select whether the oscillator operates in xtal mode or external reference mode from reset.
If RSTCFG is 0, External reference clock selected.
If RSTCFG is 1, Xtal oscillator mode is selected
WKPCFG Weak Pull Configuration
The signal on the WKPCFG pin determines whether weak pull up or pull down devices are enabled after reset on the eTPU and eMIOS pins.0: Weak pulldown applied to eTPU and eMIOS pins at reset1: Weak pullup applied to eTPU and eMIOS pins at reset.
Calibration bus interface and External Memory RM0345
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4 Calibration bus interface and External Memory
The SPC563M64xx features a 16-bit de-multiplexed calibration bus interface that is connected to an external 2Mbyte SRAM thanks to an on board latch.
4.1 External memory specificationThe calibration board provides a SRAM with the following characteristics:
– 2Mbyte static RAMs organized as 1024K words by 16 bits;
– 16-bit data width;
– Fully static operation: no clock or refresh required;
– 3.3V input supply;
– /CE power-down;
– High-speed access time (10ns);
– Full automotive temperature range;
– Lead-free.
When /CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.
4.2 SRAM supply and data retention functionThe circuitry in Figure 6 has been implemented on the calibration board to protect the memory and to guarantee that the Working Page is valid after a power fail of the target application by putting the SRAM in standby powered.
The 3.3 V supply of the SRAM (Vmem) is gated by the RESET and RSTOUT signals of the SPC563M64xx.
The memory enable is driven via the SPC563M64xx chip select C_CS0 “and” the RESETs signals combination.
RM0345 Calibration bus interface and External Memory
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Figure 6. SRAM supply circuitry
The jumper J11 (see Figure 6) allows to select the standby operation of the SRAM.
The standby voltage can be selected between:
● SPC563M64xx Vstby pin: same standby voltage as the internal RAM;
● the 3.3V generated on the calibration board;
● ECU_Stby supplied by the calibration connector J9 (see Figure 10).
Table 4. J11 configuration of SRAM supply for retention mode
J11 SRAM standby supply source
all open ECU_Stby: standby voltage on J9 calibration connector
1-2 closed Upon the board +3.3V generated
2-3 closed VSTBY input pin of the SPC563M64xx from the target application
+5V +3.3VR1
330D1LED
C35
100n
C34
4.7uF
C37
100n
C36
2.2uF
GND
IN1
GN
D2
OUT 3U2 LF33CDT-TRY
VSTBY
+3.3V
C31
1uF
GND
/RESET
Vmem
GND
Vmem
GND
53
1
24
U7
74V1G00CTR
53
1
24
U8
74V1G32CTR
ECU_Vstby
/RSOUT
/CE_RAM/CS0
Vmem
D220CJQ060
Q1
STT5PF20V
13
2J11
GAPGRI00344
Calibration bus interface and External Memory RM0345
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4.3 Calibration bus interfaceThe calibration bus is made up of address bus, data bus, and bus control signals, and is used on the calibration board to access the upon board memory.
The calibration board supports a 16-bit de-mulitplexed calibration bus. This is derived from the multiplexed bus on the SPC563M64xx, where the majority of address lines are derived from the data lines (CAL_DATA on SPC563M64 device), by using an onboard external latch controlled by the C_TS signal. The ALE functionality of this signal indicates to the external latch when to capture the address signals
Figure 7. SRAM schematic diagram
The Section 9: Calibration software compatibility and configuration shows the necessary software configuration of the SPC563M64xx calibration interface.
RM0345 Development connector
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5 Development connector
The JTAG signals and Nexus functionality with 12 Message Data Out (MDO) signals are available on the JP1 development connector (Nexus connector).
A hardware control bit in the SPC563M64xx Nexus port controller, is used to control whether the added signals for full width trace port are routed to the MDO[4:11] signals, or the CAL_MDO[4:11] signals. This control bit is set by the cut trace J1 (default close) on the NEXUSCFG pin of the SPC563M64xx device, as on the calibration board the CAL_MDO[4:11] signals are routed to the JP1 development connector.
Figure 8. JP1 development connector
The option cut trace J3, J5 and J10 are listed on Figure 5.
Table 5. J3, J5 and J10 option cut traces
option name
Function Value Note
J3 CLKOUT
openCLKOUT signal is disconnected to the Nexus JP1 connector
close(default)
CLKOUT signal is connected to the Nexus JP1 connector
J5 VSTBY
openVSTBY signal is disconnected to the Nexus JP1 connector
close(default)
VSTBY signal is connected to the Nexus JP1 connector
J10 BOOTCFG1
openBOOTCFG1 signal is disconnected to the Nexus JP1 connector
close
(default)BOOTCFG1 signal is connected to the Nexus JP1 connector
Development connector RM0345
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Figure 6 shows the mapping of the development connector that provides Debug, Nexus trace and calibration signals. The port connector is an AMP 38 pin Mictor style.
Figure 9. AMP 38 Mictor
*) signal is connected via cut trace option
Table 6. Nexus signals on AMP 38 Mictor connector
Pin Description Pin Descriptio
1 nc 2 nc
3 nc 4 nc
5 C_MDO9 6 CLKOUT*
7 BOOTCFG1* 8 C_MDO8
9 /RESET 10 C_EVTI
11 TDO 12 +3.3V
13 C_MDO10 14 RDY
15 TCK 16 C_MDO7
17 TMS 18 C_MDO6
19 TDI 20 C_MDO5
21 JCOMP 22 C_MDO4
23 C_MDO11 24 C_MDO3
25 nc 26 C_MDO2
27 10K pull down resistor 28 C_MDO1
29 TOOL_IO1 30 C_MDO0
31 VDDEH1A 32 C_EVTO
33 VDDEH1A 34 C_MCKO
35 TOOL_IO0 36 C_MSEO1
37 VSTBY* 38 C_MSEO0
RM0345 Calibration connector
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6 Calibration connector
The board is equipped with an ERNI connector to give a more robust solution in terms of physical connectivity for Calibration purpose.
Figure 10. J9 Calibration connector
The Table 7 shows the mapping of the calibration connector that provides Debug and calibration signals. The port connector is an ERNI 154819 style.
Table 7. Nexus signals on AMP 38 Mictor connector
PinSPC563M64xx
routing standard function
PinSPC563M64xx
routingstandard function
B1 nc nc A1 nc nc
B2 nc nc A2 JCOMP JTAG interface
B3 /RSOUT /RSOUT A3 CAL Wakeup12V output for Wakeup
functionality
B4 GND GND A4 C_EVTI JTAG interface
B5 GND GND A5 TDO JTAG interface
B6 GND GND A6 TMS JTAG interface
B7 GND GND A7 TCK JTAG interface
B8 GND GND A8 TDI JTAG interface
B9 GND GND A9 VmemVDDSBRAM (Backup
Voltage of ECU Standby RAM)
B10 /RESET /RESET A10 nc nc
B11GPIO[207] (@3.3V)
GPIO Pins for startup handshake and
triggeringA11 RSVDx
reserved Input, connect pin to a solder
pad
Calibration connector RM0345
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B12GPIO[207] (@3.3V)
GPIO Pins for startup handshake and
triggeringA12 MDO 0
Detect that the PLL is locked
B13 ECU_VsbyVDDSBRAM Supply
(Backup Voltage of ECU Standby RAM)
A13 +5V
VDDP Comparator Input (Supply of microcontroller Interface Pins)
Table 7. Nexus signals on AMP 38 Mictor connector (continued)
PinSPC563M64xx
routing standard function
PinSPC563M64xx
routingstandard function
RM0345 Tool IO
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7 Tool IO
The SPC563M64xx in CSP496 package provides 2 signals, GPIO[206] & GPIO[207], that are not available in the QFP144 standard production package. They can be used by the calibration tools to implement triggers and handshakes. On the calibration board, these signals are available on the JP1 development connector and J9 calibration connector.
By default GPIO[206] & GPIO[207] are powered by VDDEH at 5V. A level shifter (see Figure 11) does the translation between the 5v and the 3.3V. This is because the calibration tools operates at 3.3V that is the voltage level of the JTAG and Nexus interfaces.
Figure 11. Calibration triggers TOOL_IO
CAN interface RM0345
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8 CAN interface
The calibration board is equipped with one ST L9616 High-Speed Transceiver. It provides the Controller Area Network (CAN) communication interface through the SPC563M64xx CAN interface for calibration via CAN. This serial communication can reach speeds up to 1Mbps.
Figure 12. CAN schematic diagram
Two jumpers (J12 and J13), allow to select between the two FlexCAN interfaces of the SPC563M64xx mcu.
The CAN channel is terminated with a 120 ohms resistor. Moreover, a protection circuitry has been designed to protect the CAN transceiver in high-speed and fault tolerant networks from ESD and other harmful transient voltage events (see Figure 12).
The L9616 CAN transceiver has an Adjustable Slope Control (ASC) feature that sets the slope speed using its ASC pin. This feature select the modes of operation:
● low speed (CAN baud rate up to 250kBaud)
● high speed (CAN baud rate from 250kBaud to 1000kBaud)
This pin can be put to high or to low by the cut trace options J6, J17 & J7 as described in Table 9.
Table 8. J12, J13 FlexCAN interface selection
FlexCAN interfaceJ12 pin configuration
TX select
J13 pin configuration
RX select
FlexCAN A 2 - 3 2 - 3
FlexCAN C 2 - 1 2 - 1
RM0345 CAN interface
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The cut trace options J6, J17, J18 and J19 has been put in the design of this board to select the supply of the CAN transceiver between 5 V and 3.3 V. By this option is possible to replace the ST L9616 High-Speed Transceiver mounted on board by default, with a different transceiver that operates at 3.3 V.
Note: Refer to Section Appendix D: Options placement for layout options placement.
Table 9. J6, J17 and J7 FlexCAN interface selection
J6 (or J17 if 3.3V) J7 FlexCAN interface
closed openlow speed operation (default)
(CAN baud rate up to 250kBaud)
open closedhigh speed operation
(CAN baud rate from 250kBaud to 1000kBaud)
Table 10. CAN transceiver operating voltage selection
CAN Transceiver J6 J17 J18 J19
5V - ST L9616 High-Speed Transceiver
Adjustable Slope Control
open open close
3.3V - CAN transceiver openAdjustable
Slope Controlclose open
Calibration software compatibility and configuration RM0345
22/38 Doc ID 024080 Rev 3
9 Calibration software compatibility and configuration
The calibration board uses standard production silicon packaged in the CSP (Chip Scale Package). Therefore, all production silicon features exist and are identical on the calibration board.
The required initialization code may be as simple as the configuration of the EBI and its related pins in the SIU, and it could be integrated into standard application software.
The calibration bus and the SIU can also be configured by an external tool connected to the debug port, removing the need of specific configuration functions in the application software.
9.1 Calibration bus sw configurationA 16-bit calibration bus is implemented on the board. In multiplexed mode the CAL_DATA signals will output the address signals during the address phase by using an onboard external latch controlled by the CAL_TS signal. The CAL_ALE may be used to drive an external latch when an asynchronous memory is in use.
There are few steps to configure the SPC563M64xx Calibration Bus
– SIU PCR (Pad Configuration Register)
– SIU ECCR (External Clock Control Register)
– External Bus Interface (EBI)
9.1.1 Cal Bus PCR Settings
The SIU PCR registers used to configure the calibration bus are shown in theTable 11 The table also shows the recommended PA field setting.
Table 11. Calibration bus signals configuration
signal name SPC563M64xx
mcu signal nameFunction
P A G(1)
PCR PA
field(2)
PCR(3)
Notes
Address/Data Bus (44)
C_DATA[0:15] CAL_DATA[0:15]Calibration data bus
- - 341
C_ADDR[12:15] CAL_ADDR[12:15]Calibration address bus
- - 340
C_ADDR[16:31] CAL_ADDR[16:31]Calibration address bus
- - 345
C_CS[0] CAL_CS[0]Calibration chip select
- - 336
C_CS[1] Not Connected
C_CS[2] CAL_CS[2]
Calibration chip select
P 1338
CAL_ADDR[10]Calibration address bus
A 0
RM0345 Calibration software compatibility and configuration
Doc ID 024080 Rev 3 23/38
Note: 1 The P/A/G column indicates the position a signal occupies in the muxing order for a pin: Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001, A1 - 0b0010, A2 -0b0100, A3 - 0b1000, or G - 0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer than four bits, remove the appropriate number of leading zeroes from these values.
2 The Pad Configuration Register (PCR) PA field is used by software to select pin function.
3 Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number.
9.1.2 Cal Bus ECCR Settings
The SIU ECCR registers used to control the timing relationship between the system clock and the external clock CLKOUT.
The external bus clock (CLKOUT) divider can be programmed to divide the system clock by one, two or four based on the settings of the EBDF bit field.
C_CS[3] CAL_CS[3]
Calibration chip select
P 1339
CAL_ADDR[11]Calibration address bus
A 0
C_OE CAL_OE Calibration Output enable
- - 342
C_RD_WR CAL_RD_WR Calibration Read/write
- - 342
C_WE[0:1] CAL_WE[0:1] Calibration write/byte enable
- - 342
C_TS
CAL_TS Calibration transfer start
P 1
343CAL_ALE
Address Latch enable
A 0
Clock Synthesizer (1)
C_CLKOUT CLKOUT System clock output
P 01 229Clock output signal from MCU
Table 11. Calibration bus signals configuration (continued)
signal name SPC563M64xx
mcu signal nameFunction
P A G(1)
PCR PA
field(2)
PCR(3)
Notes
Table 12. EBDF field definition
Register EBDF field External Bus Division Factor
SIU_ECCR
00 1
01 2
10 reserved
11 4
Calibration software compatibility and configuration RM0345
24/38 Doc ID 024080 Rev 3
9.1.3 Cal Bus EBI Settings
For using the calibration bus with an external memory the user must configure the bus for multiplexed operation. These settings are located in two registers:
– EBI Module Configuration Register (EBI_MCR)
– EBI Calibration Base Register (EBI_CAL_BRx)
– EBI Calibration Option Register (EBI_CAL_ORx)
The EBI Module Configuration Register contains bits which configure various attributes associated with EBI operation. In the EBI_MCR register, the D16_31, AD_MUX and DBM fields need to be configured.
In the EBI_CAL_BRx register there are few fields that need to be configured, these are detailed in the Table 14 .
Table 13. EBI_MCR register setting
bit field
Name Description value
29D16_31
Data Bus 16_31 Select
The D16_31 bit controls whether the EBI uses the DATA[0:15] or DATA[16:31] signals, when in 16-bit Data Bus Mode (DBM=1) or for chip-select accesses to a 16-bit port (PS=1). 0b0
1 = DATA[16:31] signals are used for 16-bit port accesses
0 = DATA[0:15] signals are used for 16-bit port accesses
30AD_MUX
Address on Data Bus Multiplexing Mode
The AD_MUX bit controls whether non-chip-select accesses have the address driven on (or sampled from for external master transfers) the data bus in the address phase of a cycle. 0b11 = Address on Data Multiplexing Mode is used for non-CS accesses.0 = Only Data on data pins for non-CS accesses.
31DBM
Data Bus Mode
The DBM bit controls whether the EBI is in 32-bit or 16-bit Data Bus Mode.
0b11 = 16-bit Data Bus Mode is used0 = 32-bit Data Bus Mode is used
RM0345 Calibration software compatibility and configuration
Doc ID 024080 Rev 3 25/38
Table 14. EBI_CAL_BRx register setting
bit field
Name Description value
0-16BA
Base address
These bits are compared to the corresponding unmasked address signals among ADDR[0:16] of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus masterNote: An MCU may have some of the upper bits of the BA field tied to a fixed value internally in order to restrict the address range of the EBI for that MCU. Refer to the device-specific documentation to see which bits are tied off, if any, for a particular MCU. Tied-off bits can be read but not written. These bits are ignored by the EBI during the chip-select address comparison. However, the internal bridge of the MCU most likely requires that the chipselect banks be located in memory regions corresponding to the fixed values chosen
-
20PS
Port Size
The PS bit determines the data bus width of transactions to this chip-select bank.Note: In the case where the DBM bit in EBI_MCR is set for 16-bit Data Bus Mode, the PS bit value is ignored and is always treated as a ’1’ (16-bit port).
0b1
1 = 16-bit port0 = 32-bit port
24AD_MUX
Address on Data Bus Multiplexing
The AD_MUX bit controls whether accesses for this chip select have the address driven on the data bus in the address phase of a cycle
0b11 = Address on Data Multiplexing Mode is enabled for this chip select.0 = Address on Data Multiplexing Mode is disabled for this chip select.
26WEBS
Write Enable / Byte Select
This bit controls the functionality of the WE[0:3]/BE[0:3] signals.
0b11 = The WE[0:3]/BE[0:3] signals function as BE[0:3]0 = The WE[0:3]/BE[0:3] signals function as WE[0:3]
30BI
Burst Inhibit
This bit determines whether or not burst read accesses are allowed for this chipselect bank. The BI bit is ignored (treated as 1) for chip-select accesses with external TA (SETA=1). 0b11 = Disable burst accesses for this bank. This is the default value out of reset (or when SETA=1).0 = Enable burst accesses for this bank]
Calibration software compatibility and configuration RM0345
26/38 Doc ID 024080 Rev 3
The EBI Option Registers are used to define the address mask and other attributes for the corresponding chip select.The SCY field of the EBI_CAL_BOx register is detailed in the Table 15.
31V
Valid bit
The user writes this bit to indicate that the contents of this Base Register and Option Register pair are valid. The appropriate CS signal does not assert unless the corresponding V-bit is set. 0b1
1: This bank is valid
0: This bank is not valid
Table 15. EBI_CAL_BOx register setting
bit field
Name Description value
0-16AM
Address Mask
This field allows masking of any corresponding bits in the associated Base Register.Masking the address independently allows external devices of different size address ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be used in comparison with the address pins.Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time.
-
24-27SCY
Cycle length in clocks
This field represents the number of wait states (external cycles) inserted after the address phase in the single transfer case, or in the first beat of a burst, when the memory controller handles the external memory access. Values range from 0 to 15 and its depends on the RAM connected on top board.
This is the main parameter for determining the length of the cycle. These bits are ignored when SETA=1.
The total cycle length for the first beat (including the TS cycle) = (2+SCY) external clock cycles.
-
29-30BSCY
Burst beats length in clocks
This field determines the number of wait states (external cycles) inserted in all burst beats except the first, when the memory controller starts handling the external memory access and thus is using SCY[0:3] to determine the length of the first beat.These bits are ignored when SETA=1.The total memory access length for each beat is (1 + BSCY) external clock cycles.The total cycle length (including the TS cycle) = (2+SCY) + (#beats(h)-1) * (BSCY+1).
-
Table 14. EBI_CAL_BRx register setting
bit field
Name Description value
RM0345 Calibration software compatibility and configuration
Doc ID 024080 Rev 3 27/38
9.2 Example Configuration CODEThe following code is used to configure the calibration bus for 16bit de-multiplexed mode.
//---------------------------------------------------// SIU PCR (Pad Configuration Register) setup// (Cal BUS bommon drive strength = 20pF, DSC = 0b01)//---------------------------------------------------
SIU.PCR[336].R = 0x0040;//CAL_CS[0]DSC=20pF (0b01)
SIU.PCR[338].R = 0x0440;//CAL_CS[2] (PA=0b1),DSC=20pF (0b01)
SIU.PCR[339].R = 0x0040;//CAL_ADDR[11] (PA=0b0), DSC=20pF (0b01)
SIU.PCR[340].R = 0x0040;//CAL_ADDR[12..15], DSC=20pF (0b01)
SIU.PCR[345].R = 0x0040;//CAL_ADDR[16..30], DSC=20pF (0b01)
SIU.PCR[341].R = 0x0040;//CAL_DATA[0..15], DSC=20pF (0b01)
SIU.PCR[342].R = 0x0040;//CAL_RD/WR, CAL_WE[0-1], CAL_OE, DSC=20pF (0b01)
SIU.PCR[343].R = 0x0040;//CAL_ALE, DSC=20pF (0b01)
//--------------------------------------------------// SIU ECCR (External Clock Control Register) setup//--------------------------------------------------
SIU.ECCR.R = 0x1000//External Bus Division Factor = 1 (EBDF=0b00)
//--------------------------------------------------// EBI Registers setup//--------------------------------------------------
//-----------------------------------------------------------------// EBI MCR setup for 16-bit bus configuration:// // EARP = 01 (Equal priority);// D16_31 = 0 (DATA[0:15] signals are used for 16-bit port accesses);// AD_MUX = 1 (Addr on Data Multiplexing Mode is used for non-CS acc.);// DBM = 0 (32-bit Data Bus Mode is used);
EBI.MCR.R = 0x802;
//------------------------------------------------------// EBI Base Register setup for 16-bit bus configuration:// // Base Address = 0x20000000;// PS = 1 (16-bits port size)// AD_MUX = 1 (Address on Data Multiplexing Mode is enabled for this chip select);// WEBS = 1 (Use BE function);// BI = 1 (Disable burst accesses for this bank);// V = 1 (Valid CS Bank)
EBI.CAL_CS[0].BR.R = 0x200008A3;
Calibration software compatibility and configuration RM0345
28/38 Doc ID 024080 Rev 3
//-----------------------------------------// EBI Option Register setup://// Address mask = 0xefe00000;// Wait state = 0 (set 0 wait states);
EBI.CAL_CS[0].OR.R = 0xffe00000;
RM0345 Calibration base footprints
Doc ID 024080 Rev 3 29/38
Appendix A Calibration base footprints
SPC563M64CAL144 (rev.B) calibration board had footprint compatible with QFP144 production package version of SPC563M64xx devices, ensuring that they can be fitted to an application PCB that has been designed to accept standard QFP144 packaged SPC563M64xx devices.
Bases can be supplied with solder footprints, to allow direct and permanent soldered connection to an application PCB, or with pin adapter connectors fitted, allowing connection and removal from an application PCB that is fitted with a compatible receiver socket.
Figure 13. TQPACK144SD
all dimension are in mm
Mechanical constrains RM0345
30/38 Doc ID 024080 Rev 3
Appendix B Mechanical constrains
Figure 14. Top and side view drawing
RM0345 Mechanical constrains
Doc ID 024080 Rev 3 31/38
Figure 15. Side and bottom view drawing
Mechanical constrains RM0345
32/38 Doc ID 024080 Rev 3
Figure 16. Complete system side view drawing
RM0345 Schematic
Doc ID 024080 Rev 3 33/38
Appendix C Schematic
Figure 17. SPC563M64xx in CSP package schematic
11
TP1
PIN
TES
T
AN.2AN.3
AN.0
AN.4AN.5AN.6AN.7
AN.1
AN.9
AN.12AN.11
AN.13AN.14
AN.16AN.17AN.18
AN.15
AN.21
AN.23AN.24AN.25
AN.22
AN.27AN.28AN.30AN.31AN.32AN.33AN.34AN.35
AN.37AN.36
/CS0/CS2/CS3
C_RD_WRC_WE0C_WE1C_OEC_TSC_MCKOC_EVTO
+3.3
V
VD
D
EVTI
EVTO
MC
KO
/MSE
O1
/MSE
O0
MD
O0
MD
O1
MD
O2
MD
O3
RX
D_B
RX
D_A
TXD
_A
TXD
_B
CN
RX
_C
CN
RX
_AC
NTX
_A
CN
TX_C
PCS_
B0
PCS_
B1
PCS_
B2
PCS_
B3
PCS_
B4
PCS_
B5
SOU
T_B
SIN
_BSC
K_B
JCO
MP
TMS
TDO
TDI
TCK
FB1
EXTA
LX
TAL
CLK
OU
T
/RES
ET/R
SOU
TB
OO
TCFG
1W
KPC
FGPL
LREF
C9
10n
C11
10n
C13
10n
C10
100n
C12
100n
C14
100n
+5V
+3.3
V
GN
D
C15
10n
C17
10n
C19
10n
C16
100n
C18
100n
C20
100n
+3.3
V
GN
D
C21
10n
C23
10n
C25
10n
C22
100n
C24
100n
C26
100n
GN
D
C4
100n
C32
10n
C3
2.2u
F
C6
100n
C5
2.2u
F
C8
100n
C7
2.2u
F
C2
100n
C1
2.2u
F
VD
D
GN
D
VST
BY
VR
CC
TL
VD
DR
EG
VSS
AV
SSSY
NG
ND
C33
100n
VR
H
VR
L
REF
BY
PC
VD
DA
0
C27
10n
C28
100n
C29
10n
C30
100n
VD
DSY
NV
DD
A0
FB2
FB3
+3.3
V
J1
DEF
AU
LT=C
LOSE
EMIO
S.2
AN.39AN.38
GPIO207GPIO206GPIO99GPIO98
+3.3
V
J2V
RC
33
R3
10K
GN
D
TEST POINTS
1 2 3 4
J4 CO
N4
+5V
+3.3
VV
DD
R5
10K
R4
10K
)IBE(
eca
fret
nI s
uB l
anre
txE
CDAQe
Reset &
Configuration
Clock / Synthesizer
Jtag
Nexus
FlexCAN
SCI
DSPI
eTPU
EMIOS
ETPU
A0
M5
ETPU
A1
G8
ETPU
A2
M3
ETPU
A3
L3ET
PUA
4L2
ETPU
A5
H9
ETPU
A6
M2
ETPU
A7
K3
ETPU
A8
K2
ETPU
A9
G9
ETPU
A10
L5
ETPU
A11
J3
ETPU
A12
J2
ETPU
A13
G10
ETPU
A14
K5
ETPU
A15
H3
ETPU
A16
K1
ETPU
A17
H10
ETPU
A18
J5
ETPU
A19
G3
ETPU
A20
J1
ETPU
A21
H11
ETPU
A22
F3
ETPU
A23
H2
ETPU
A24
G2
ETPU
A25
H5
ETPU
A26
G5
ETPU
A27
E3
ETPU
A28
F1
ETPU
A29
F2ET
PUA
30E1
ETPU
A31
E2
AN0C9AN1B8
AN2G12
AN3E10
AN4C10
AN5B9
AN6G13
AN7E11
AN9C4AN11B6
AN12-SDSH15
AN13-SDOG15
AN14-SDIE16
AN15-FCKC16
AN16B7
AN17E8
AN18H12AN21E9
AN22C11
AN23B11
AN24H13
AN25E12
AN27B12
AN28A13
AN30C13
AN31B13
AN32B14
AN33E14
AN34G14
AN35A14
AN36C5
AN37B5
C_CS0AB11
C_CS2AA10
C_CS3AB10
C_ADD12AA14
C_ADD13R8
C_ADD14AA15
C_ADD15W7
C_ADD16P7
C_ADD17P8
C_ADD18U7
C_ADD19N7
C_ADD20M8
C_ADD21M7
C_ADD22V7
C_ADD23L8
C_ADD24T8C_ADD25K8
C_ADD26L7
C_ADD27U8
C_ADD28V8
C_ADD29AB13
C_ADD30AB14
C_DAT0W21
C_DAT1Y22C_DAT2V21
C_DAT3W22
C_DAT4U21
C_DAT5U22
C_DAT6T21
C_DAT7T22
C_DAT8AA17
C_DAT9AB16C_DAT10AA18
C_DAT11AB17
C_DAT12AA19
C_DAT13AB19
C_DAT14AA20
C_DAT15AB20
C_RD_WRW8C_WE0Y8
C_WE1AA7
C_OEAD16
VST
BY
B3
VR
CC
TLA
C26
VD
DA
1A
5V
DD
A0
E15
VSS
A0
A15
VSS
A0
B15
VSS
A1
A6
VR
HA
9
VR
LA
10
REF
BY
PCB
10
XTA
LA
D28
EXTA
LA
C28
CLK
OU
TA
F25
VSS A2
VSS AD5
VSS AF26
VSS AF3
VSS AG1
VSS AG2
VSS AG27
VSS AG28
VSS AH1
VSS AH2
VSS AH27
VSS AH28
VSS B1
VSS B2
VSS B27
VSS B28
VSS C26
VSS C3
VSS E24
VSS E5
VSS G22
VSS G7
VSS H21
VSS H8
VSS L11
VSS L12
VSS L13VSS L14
VSS M12
VSS M13
VSS M14
VSS M15
VSS A28
VSS AA8
VSS AB7
VSS P15
VSS N17
VSS N15
VSS M17VSS M16
VSS N14
VSS P14
VSS N16
VSS AB22
VSS AA21
VSS A27
VSS A1
MC
KO
H26
EVTO
G27
EVTI
G26
MD
O3
C23
MD
O2
B21
MD
O1
C24
MD
O0
C25
MSE
O1
H24
MSE
O0
G24
JCO
MP
F26
TMS
E26
TDO
F27
TDI
E28
TCK
E27
RX
DB
Y24
TXD
BY
27
RX
DA
U26
TXD
AV
24
CN
RX
CY
26
CN
TXC
W24
CN
RX
AA
G22
CN
TXA
AF2
2
PCSB
5M
26
PCSB
4N
27
PCSB
3M
27
PCSB
2T2
8
PCSB
1R
28
PCSB
0R
27
SOU
TBN
28
SIN
BP2
8
SCK
BT2
7
EMIO
S0A
D17
EMIO
S2P2
1
EMIO
S10
N22
EMIO
S11
AG
18
EMIO
S12
M21
EMIO
S13
AF1
8
EMIO
S23
AF2
1
EMIO
S8N
21
EMIO
S9A
D23
ETPU
A0
N5
VSS P16
VSS P17
VSS R14VSS R15
VSS R16
VSS T13
VSS T16
VSS T17
VSS U12
VSS U17
VSS U18VSS V11
VSS V18
VD
DE1
2A
A13
VD
DE1
2A
A16
VD
DE1
2A
B18
VD
DE1
2A
B21
VD
DE1
2A
E2
VD
DE1
2A
G12
VD
DE1
2A
G4
VD
DE1
2K
7
VD
DE1
2N
8
VD
DE1
2R
11
VD
DE1
2R
12
VD
DE1
2R
13
VD
DE1
2R
17
VD
DE1
2R
18
VD
DE1
2R
21
VD
DE1
2T1
1
VD
DE1
2T1
2
VD
DE1
2T1
5
VD
DE1
2T1
8V
DD
E12
U11
VD
DE1
2U
15
VD
DE1
2U
16
VD
DE1
2U
2
VD
DE1
2V
15
VD
DE1
2V
16
VD
DE1
2V
17
VD
DE1
2V
22
VD
DEH
1J7
VD
DEH
1G
11
VD
DEH
4A
D20
VD
DEH
6AV
26
VD
DY
21
VD
DA
A22
VD
DA
A9
VD
DA
B8
VD
DA
C24
VD
DA
D6
VD
DA
E26
VD
DA
F27
VD
DA
F4V
DD
AG
3
VD
DB
25
VD
DC
2
VD
DD
27
VD
DD
3
VD
DH
7
VD
DJ8
VD
DF5
VD
DPL
LA
D27
VD
DR
EGW
28
VSS
PLL
AC
27
VSU
PA
D24
VR
C33
W5
EMIO
S4A
D18
VR
C33
AE2
7
VR
C33
B26
VR
C33
D2
VD
DEH
6BK
24
VR
C33
AF9
RES
ETA
A27
RST
OU
TW
26
BO
OTC
FG1
AB
24
WK
PCFG
AA
24
PLLR
EFA
B27
VDDEH7C27
VDDEH7D26
VDDEH7H22
VDDEH7J21
VDDEH7L15
VDDEH7L16
VDDEH7L17
VDDEH7L18
VDDEH7M18
VDDEH7N18
VDDEH7P18
VDDEH7F24
NEX
USC
FGG
18
C_EVTOG19 C_MCKOH18 C_TSAA11
EMIO
S1A
D21
EMIO
S14
AH
19
EMIO
S15
M22
PCK
CFG
0A
F24
PCK
CFG
1A
G25
GPIO206 AH10
GPIO98 N26
GPIO99 N24
GPIO207 AG10
AN38B4
AN39C6
U1 SP
C563
M64
VD
DSY
N
GN
D
NEX
USC
FG
EMIO
S.23
EMIO
S.15
EMIO
S.14
EMIO
S.13
EMIO
S.12
EMIO
S.11
EMIO
S.10
EMIO
S.9
EMIO
S.8
EMIO
S.0
EMIO
S.1
EMIO
S.4
ETPU
A.3
1ET
PUA
.30
ETPU
A.2
9ET
PUA
.28
ETPU
A.2
7ET
PUA
.26
ETPU
A.2
5ET
PUA
.24
ETPU
A.2
3
ETPU
A.0
.N5
ETPU
A.0
.M5
ETPU
A.1
ETPU
A.2
ETPU
A.3
ETPU
A.4
ETPU
A.5
ETPU
A.6
ETPU
A.7
ETPU
A.8
ETPU
A.9
ETPU
A.1
0ET
PUA
.11
ETPU
A.1
2ET
PUA
.13
ETPU
A.1
4ET
PUA
.15
ETPU
A.1
6ET
PUA
.17
ETPU
A.1
8ET
PUA
.19
ETPU
A.2
0ET
PUA
.21
ETPU
A.2
2
ADDR.12ADDR.13ADDR.14ADDR.15ADDR.16ADDR.17ADDR.18ADDR.19ADDR.20ADDR.21ADDR.22ADDR.23ADDR.24ADDR.25ADDR.26ADDR.27ADDR.28ADDR.29ADDR.30DATA.0DATA.1DATA.2DATA.3DATA.4DATA.5DATA.6DATA.7DATA.8DATA.9DATA.10DATA.11DATA.12DATA.13DATA.14DATA.15
VSS
SYN
GN
DV
SSA
PCK
CFG
0PC
KC
FG1
VD
DEH
7
VD
DEH
7
Ope
n x
CUT2
.1Cl
ose
x CU
T2.0
J16
ABA BN
.C.
VD
DEH
6A
VD
DEH
1AV
DD
EH1B
VD
DEH
6BV
DD
EH6B
VD
DEH
6A
GAPGRI00355
Schematic RM0345
34/38 Doc ID 024080 Rev 3
Figure 18. Polypod-TQ144 connector schematic
Default = CLOSE
GND
VDD
/RESET/RSOUT
BOOTCFG1WKPCFG
PLLREF
VSSA VSSSYNGND
EMIOS.4EMIOS.8EMIOS.9
EMIOS.11EMIOS.12EMIOS.14
EMIOS.10
EMIOS.0EMIOS.2
EMIOS.23
/MSEO0MDO0MDO1MDO2MDO3
EVTIEVTO
MCKO
PCS_B0PCS_B1PCS_B2PCS_B3PCS_B4PCS_B5
SOUT_BSIN_B
SCK_B
VRHVRL
REFBYPC
EXTALXTAL
CNRX_C
CNRX_ACNTX_A
CNTX_C
RXD_B
RXD_ATXD_A
TXD_B
JCOMP
TMS
TDOTDITCK
VRCCTL
VDDREG
VSTBY
C46
1uF
GND
AN.0AN.1AN.2 AN1142
AN21144
AN5138
AN3140
AN7136
AN23131
AN12-SDS119
AN13-SDO118
AN4139
AN14-SDO117
AN0143
AN22132
AN95
AN6137
AN2141
AN114
AN181
AN15-FCK116
AN172 AN163
AN30126
AN32124 AN31125
AN24130
AN25129
AN28127 AN27128
AN33123
AN35121 AN34122
AN389
ETPUA052
AN398
ETPUA151
ETPUA250
ETPUA349
ETPUA447
ETPUA545
ETPUA644
ETPUA743
ETPUA842
ETPUA941
ETPUA1040
ETPUA1139
ETPUA1238
ETPUA1337
ETPUA1435
ETPUA1533
ETPUA1632
ETPUA1731
ETPUA1830
ETPUA1929
ETPUA2028
ETPUA2127
ETPUA2225
ETPUA2323
ETPUA2421
ETPUA2520
ETPUA2619
ETPUA2718
ETPUA2817
ETPUA2916
ETPUA3015
ETPUA3114
RSTOUT85
RESET80
WKPCFG71
BOOTCFG170
PLLREF68
Vss
36
Vss
59
Vss
73
Vss
22
Vss
115
Vss
91
Vss
104
Vss
48
VD
D26
VD
D53
VD
D86
VD
D12
0
EMIOS0 54
EMIOS2 55
EMIOS4 56
EMIOS8 57
EMIOS9 58
EMIOS10 60
EMIOS11 62
EMIOS12 63
EMIOS14 64
EMIOS23 65
VRL 133VRH 134
REFBYPC 135
EXTAL 75XTAL 76
CNTXA 66
CNTXC 84CNRXA 67
CNRXC 81
TXDA 83RXDA 82TXDB 72RXDB 69
JCOMP 98TDO 100TDI 107
TCK 105TMS 108
MCKO 99MSEO1 101
MSEO0 109
EVTI 103EVTO 106
MDO0 110MDO1 111MDO2 112MDO3 114
PCSB5 87PCSB4 88PCSB3 97
PCSB0 94
PCSB2 90PCSB1 92
SINB 95SOUTB 96
SCKB 89
VDDEH1A 24VDDEH1B 34
VDDEH1B 46
VDDEH6A 61
VDDEH6A 78
VDDEH6B 93
VDDEH7 102
VDDEH7 113
VDDPLL 74
VDDREG 10
VRC33 13
VRCCTL 11
VSSPLL 77
VSSA0 7
VSTBY 12
VDDA0 6
VSUP 79
U5
Polypod-TQ144
AN.3AN.4AN.5AN.6AN.7AN.9AN.11AN.12AN.13AN.14AN.15AN.16AN.17AN.18AN.21AN.22
ETPUA.5ETPUA.4ETPUA.3ETPUA.2ETPUA.1ETPUA.0.M5
AN.23AN.24AN.25AN.27AN.28
AN.39AN.38AN.35AN.34AN.33
AN.31AN.30
AN.32
ETPUA.6ETPUA.7ETPUA.8ETPUA.9ETPUA.10ETPUA.11ETPUA.12ETPUA.13ETPUA.14ETPUA.15ETPUA.16ETPUA.17ETPUA.18ETPUA.19ETPUA.20ETPUA.21ETPUA.22ETPUA.23ETPUA.24
ETPUA.26ETPUA.25
ETPUA.27ETPUA.28ETPUA.29ETPUA.30ETPUA.31
VDDA0
VDDSYN
/MSEO1
Default = CLOSEJ15
VRC33
J14
+5V
VDDEH7
VDDEH6A
VDDEH1AVDDEH1B
VDDEH6B
GAPGRI00356
RM0345 Schematic
Doc ID 024080 Rev 3 35/38
Figure 19. Memory, CAN and connectors schematic
Latc
h_Q
00
Latc
h_Q
02
Latc
h_Q
04La
tch_
Q05
Latc
h_Q
06La
tch_
Q07
Latc
h_Q
13La
tch_
Q14
C_T
S
C_T
S
GN
D
AD
DR
.17
AD
DR
.18
AD
DR
.19
AD
DR
.20
AD
DR
.23
AD
DR
.24
AD
DR
.21
AD
DR
.22
AD
DR
.29
AD
DR
.30
AD
DR
.28
AD
DR
.16
CLK
OU
T
+3.3
V
+3.3
V
GN
D
C38
2.2u
F
C41
100n
C42
2.2u
F
GN
D
C39
100n
C40
2.2u
F
GN
D
Vm
em
GN
D
AD
DR
.14
AD
DR
.13
AD
DR
.15
Latc
h_Q
00La
tch_
Q01
Latc
h_Q
03La
tch_
Q02
Latc
h_Q
04La
tch_
Q05
Latc
h_Q
06La
tch_
Q07
Latc
h_Q
08La
tch_
Q09
Latc
h_Q
11La
tch_
Q10
Latc
h_Q
12La
tch_
Q13
Latc
h_Q
14
AD
DR
.12
/CS3
/CE_
RA
M
C_M
CK
OC
_EV
TO
C_R
D_W
RC
_WE0
C_W
E1C
_OE
+5V
+3.3
VR
1
330
D1
LED
C35
100n
C34
4.7u
F
C37
100n
C36
2.2u
F
GN
D
OE
1
LE48
D1
47Q
12
D2
46Q
23
D3
44Q
35
D4
43Q
46
D5
41Q
58
D6
40Q
69
D7
38Q
711
D8
37Q
812
718
VC
C
4101521
GN
D
U4A SN
74LV
C16
373D
GG
R
OE
24
LE25
D1
36Q
113
D2
35Q
214
D3
33Q
316
D4
32Q
417
D5
30Q
519
D6
29Q
620
D7
27Q
722
D8
26Q
823
28343945
3142
VC
C
GN
D
U4B SN
74LV
C16
373 D
GG
R
GN
D
GN
D
NEX
US
IN1
GND 2
OU
T3
U2
LF33
CD
T-TR
Y
J10
J3
J5
RSV
D1
1R
SVD
22
RSV
D3
3R
SVD
44
VEN
_IO
05
CLK
OU
T6
VEN
_IO
27
VEN
_IO
38
RST
IN9
EVTI
10
TDO
11V
TREF
12V
EN_I
O4
13R
DY
14
TCK
15M
DO
0716
TMS
17M
DO
0618
TDI
19M
DO
0520
JCO
MP
21M
DO
0422
VEN
_IO
123
MD
O03
24
RST
OU
T25
MD
O02
26
TOO
L_IO
227
MD
O01
28
TOO
L_IO
129
MD
O00
30
UB
ATT
31EV
TO32
UB
ATT
33M
CK
O34
TOO
L_IO
035
MSE
O1
36
VA
LTR
EF37
MSE
O0
38
GND 0
JP1
DEF
AU
LT=C
LOSE
DEF
AU
LT=C
LOSE
DEF
AU
LT=C
LOSE
AD
DR
.26
AD
DR
.27
JCO
MP
TMS
TDO
TDI
TCK
/RES
ET
GPI
O20
7_3.
3V
GPI
O20
6_3.
3V
R8
22
R9
22
R6
22K
R7
22K
GN
D
GPI
O20
7_3.
3VG
PIO
206_
3.3V
+3.3
V
VST
BY
+3.3
V
C31 1uF
GN
D
GN
D
GN
D
J7+5
V
+5V
C44
100n
C43
2.2u
F
CA
N_H
IGH
CA
N_L
OW
DEF
AU
LT=C
LOSE
DEF
AU
LT=O
PEN
J6
CN
TX
CN
RX
CN
RX
_C
CN
RX
_AC
NTX
_A
CN
TX_C
R2
60 R10
60
C45
100n G
ND
GN
D
/RES
ET
Vm
emV
mem
Vm
em
Vm
em
GN
D
Vm
em
GN
D
/CE_
RA
M
/CE_
RA
M
Vm
em
5 3
124
U7
74V
1G00
CTR
5 3
124
U8
74V
1G32
CTR
11
TP3
PIN
TES
T
11
TP2
PIN
TES
T
BO
OTC
FG1
AD
DR
.25
Latc
h_Q
01
Latc
h_Q
03
DA
TA.0
DA
TA.1
DA
TA.2
DA
TA.3
DA
TA.4
DA
TA.5
DA
TA.6
DA
TA.7
Latc
h_Q
08La
tch_
Q09
Latc
h_Q
10La
tch_
Q11
Latc
h_Q
12
DA
TA.1
4D
ATA
.13
DA
TA.1
2D
ATA
.11
DA
TA.1
0D
ATA
.9D
ATA
.8
DA
TA.1
5D
ATA
.14
DA
TA.1
3D
ATA
.12
DA
TA.1
1D
ATA
.10
DA
TA.9
DA
TA.0
DA
TA.1
DA
TA.2
DA
TA.3
DA
TA.4
DA
TA.5
DA
TA.6
DA
TA.7
DA
TA.8
ECU
_Vstb
y
/RSO
UT
/CE_
RA
M/C
S0
Vm
em
XR
NC
X TN
C
D2
20C
JQ06
0
D3
NU
P210
5
1A2
1B3
2A5
2B6
Vcc8
/OE1
1/O
E27
GND 4
U9
74C
B3T
3306
Q1
STT5
PF20
V
VST
BY
/RSO
UT
GN
DG
ND
GN
DG
ND
GN
DG
ND
/RES
ET
ECU
_Vstb
yG
PIO
206_
3.3V
GPI
O20
7_3.
3VM
DO
0R
SVD
x
Vm
emTD
I
JCO
MP
CA
L W
akeu
p
TDO
TMS
TCK
GPI
O20
7G
PIO
206
B1
1A
12
B2
3A
24
B3
5A
36
B4
7A
48
B5
9A
510
B6
11A
612
B7
13A
714
B8
15A
816
B9
17
B10
19
B11
21
B12
23
B13
25A
1326
A9
18
A10
20
A11
22
A12
24
J9 ERN
I_15
4819
1 3
2J1
1
TX0
1G
ND
2V
s3
RX
04
RX
15
C_L
6C
_H7
ASC
8U
6
L961
6
1 2
J8 CO
N2
1 3
2J1
3JU
MPE
R
1 3
2J1
2JU
MPE
R
A0
A3
A1
A4
A2
A5
A3
B3
A4
B4
A5
C3
A6
C4
A7
D4
A8
H2
A9
H3
A10
H4
A11
H5
A12
G3
A13
G4
A14
F3A
15F4
I/O0
B6
I/O1
C5
I/O2
C6
I/O3
D5
I/O4
E5
I/O5
F5
I/O6
F6
I/O7
G6
I/O8
B1
I/O9
C1
I/O10
C2
I/O11
D2
I/O12
E2
I/O13
F2
I/O14
F1I/O
15G
1GND D1
GND E6VDDD6
VDDE1
CE
B5
WE
G5
LBA
1U
BB
2O
EA
2
A16
E4
A17
D3
NC
A6
NC
H6
NC
E3
A19
G2
A18
H1
U3
IS64
WV
1024
16B
LL
VD
DEH
1AV
DD
EH1A
VD
DEH
7
AD
DR
.30
R11
10K
+3.3
V J18
J19
J17
+3.3
V
GN
D
DEF
AU
LT=O
PEN
DEF
AU
LT=C
LOSE
DEFAULT=OPEN
GAPGRI00357
Options placement RM0345
36/38 Doc ID 024080 Rev 3
Appendix D Options placement
Figure 20. Options placement
TOP view
Bottom view
GAPGRI00358
RM0345 Revision history
Doc ID 024080 Rev 3 37/38
Revision history
Table 16. Document revision history
Date Revision Changes
18-Jan-2013 1 Initial release.
13-Feb-2013 2 Modified Figure 14.
17-Sep-2013 3 Updated Disclaimer.
RM0345
38/38 Doc ID 024080 Rev 3
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