core deep learning with hifive unleashed expansion kit...© 2018 microsemi, a wholly owned...
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© 2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. 1
Core Deep Learning with HiFive Unleashed Expansion Kit
Krishnakumar (KK)Product MarketingProgrammable Solutions BUMicrosemi Corporation
2© 2018 Microsemi
Agenda
Introduction to Mi-V Ecosystem
Mi-V HiFive Unleashed Expansion Board
• Hardware
• Tools
Deep Learning with Microsemi FPGA and RISC-V
• Setup
• Convolutional Neural Network Overview
• Microsemi FPGA Advantage
• Deep Learning Demo
3© 2018 Microsemi
The Mi-V™ RISC-V ecosystem is a continually expanding comprehensive suite of tools and design resources to fully support RISC-V designs.
Mi-V™ ecosystem aims to increase adoption of RISC-V ISA and Microsemi's soft CPU product family.
Introduced the first soft CPUs for FPGAs
Mi-V ecosystem enabled numerous RTOS
Microsemi Invests In The RISC-V Ecosystem
4© 2018 Microsemi
CPUs: Mi-V Soft CPU Roadmap
Mi_V_RV32I_AHB• Small core, with debug, 4K LE’s
Additional cores can be added based on customer demand
Core LE’s CoreMark Cache Mul/Div Floating Point Availability
CORE_RISCV_AXI4 10K 2.01 8K I and D Yes N/A Now
Mi_V_RV32IMA_L1_AHB 10K 2.01 8K I and D Yes N/A Now
Mi_V_RV32IMAF_L1_AHB 26K 2.01 8K I and D Yes Single Precision Now
Mi_V_RV32I_AHB 4K - N/A N/A N/A Q2’18
Mi_V_RV32IMA_L1_AXI 10K 2.01 8K I and D Yes N/A Q2’18
Mi_V_RV32IMAFC_L1_AHB
Mi-V = Mi-V RISC-V Ecosystem
RV32I = 32 bit integer machine
M = Multiply and Divide
A = Atomic Instructions
F = Single Precision Floating Point
D = Double Precision Floating Point
C = Compressed Instructions
L1 = Instruction and Data Cache
AHB = AHB Bus Interface
AXI = AXI Bus Interface
5© 2018 Microsemi
Mi-V Eclipse Based IDE
A single tool chain for RISC-V and ARM MCUs
• Easy migration from ARM to RISC-V
Running on Linux or Windows Hosts
Bundled with example projects and RTOSs
https://github.com/RISCV-on-Microsemi-FPGA
Eclipse IDE Design Flow
Compiler
Debugger Demo/Eval Boards
Firmware
Catalog
Sample
Projects
Programmer/
JTAG Dongle
Arduino ShieldPMOD
MikroBus
6© 2018 Microsemi
Drivers for Microsemi RISC-V Soft CPUs• Updates pushed to your desktop
• Release notes
• User guides
Version Controlled
MISRA/Netrino compliant
Firmware Catalog
7© 2018 Microsemi
Mi-V RISC-V Soft CPU RTOS Support Available Today
Open Source• FreeRTOS
• Huawei LiteOS
• MyNewt
• Zephyr
Commercial• Express Logic - ThreadX
• SiLabs - Micrium µC/OSIII
• Segger - embOS
These RTOS already run on the Mi-V soft RISC-V CPUs
8© 2018 Microsemi
Design examples targeted to various boards• Hello world printf via UART
• Interrupt blinky
• Touch screen Tic-tac-toe
• Crypto processor with RISC-V
Getting started building a RISC-V tutorial
Solutions: Example Designs on Github
9© 2018 Microsemi
Mi-V Development and Evaluation Boards
Future Avalanche Board (Price $179)
AVMPF300TS-01
Microsemi PolarFire Eval Kit (Price $1495)
MPF300-EVAL-KIT_ES
Microsemi PolarFire Splash Kit (Price $699)
MPF300-SPLASH-KIT-ES
Future RISCV Board (Price $99)
FUTUREM2GL-EVB
Arrow Everest Board (Price $499)
EVEREST-DEV-BOARDMicrosemi RTG4 Development Kit
10© 2018 Microsemi
HiFive Unleashed Development Platform
11© 2018 Microsemi
Enables the community to port tools, OS’s, middleware, packages to RISC-V
Makes software development easier
Enables standard and custom peripherals
Mi-V HiFive Unleashed Expansion: Advancing the Ecosystem
• Supporting the community supports our soft
CPUs for our FPGAs
• Supporting the community supports the Mi-V
ecosystem and vice versa
12© 2018 Microsemi
PolarFire HiFive Unleashed Development Platform
Designed for Expandability
Pre-programmed with a ChipLink to PCIe Root Port Bridge
Enables Root Complex on the HiFive Unleashed Board
Stay tuned for FPGA developer versions
13© 2018 Microsemi
PolarFire Mi-V HiFive Unleashed Development Platform
SiFive U500
DDR4
64b+ECC
GbEPHY
GMII
SPI
Power Tree
Ethernet Switch
MDI
RJ45
FM
C
SD
Ca
rd
SDCard
JT
AG
JTAG
SPI Flash
QSPI
SiFive Motherboard
14© 2018 Microsemi
HiFive Unleashed + Unleashed Expansion Board
15© 2018 Microsemi
Resources
Microsemi docs
• https://www.microsemi.com/hifive-unleashed-expansion-board
Sifive Docs
• https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-getting-started-guide/
SiFive Forum
• https://forums.sifive.com/c/hifive-unleashed
SiFive Freedom Unleashed SDK
• https://github.com/sifive/freedom-u-sdk
16© 2018 Microsemi
Where to Buy?
CrowdSupply – Sold-out• https://www.crowdsupply.com/microsemi/hifive-unleashed-expansion-board
New campaign under plan
For immediate needs, please contact me
17© 2018 Microsemi
Deep Learning using Microsemi FPGA and RISC-V
18© 2018 Microsemi
Inference Setup
Trained Model PredictionInput data
19© 2018 Microsemi
Deep Learning Setup
Training data
Training algorithm
Model Prediction
Evaluate
Network training
Inference
20© 2018 Microsemi
Convolutional Neural Networks (CNNs)
Pedestrian
Car
Animal
Road
OutputInput
Hand-CraftedSIFT, HOG, Gabor
Filters etc.
Traditional Image Processing Pipeline
Trainable
Feature Extractor Classifier
Pedestrian
Car
Animal
Road
OutputInput
TrainableConvolutional
Layers with optional pooling and activation
functions
Deep Learning
Trainable
Feature Extractor Classifier
• Traditionally hand-crafted features• Time consuming design• Application Specific
• Deep Learning• Feature Learning• Trainable Feature Extractor• Requires lots of training data
• Became viable with improvements in
• Training Techniques• Availability of Training Data• Processing power
21© 2018 Microsemi
Deep Learning Model
22© 2018 Microsemi
The Microsemi FPGAs Advantage
23© 2018 Microsemi
CNN Complexity
Convolution layers Fully connected layers
You Only Look Once:Redmon et al, 2016
24© 2018 Microsemi
CNN Complexity Overview
1.040
5.549
3.699 3.699
1.850
0.029 0.0060.000
1.000
2.000
3.000
4.000
5.000
6.000
1 2 3 4 5 6 7
Layer
opera
tions (
GO
P)
Computation complexity
0.005 0.442 1.180
4.719
9.437
29.360
6.021
0.000
5.000
10.000
15.000
20.000
25.000
30.000
35.000
1 2 3 4 5 6 7
Weig
hts
required (
Mill
ion)
External memory access
Convolution layers Fully connected layers Convolution layers Fully connected layers
25© 2018 Microsemi
INT8 Matrix Multiplication – Microsemi
Dot Product Matrix Computation
oj = a1*w11 + a1*w12 + a1*w13 + …. a2*w21 + a2*w22 + a2*w23 + ….
Figure: Math Block in PolarFire
26© 2018 Microsemi
CDL Design Space Exploration
Att
ain
ab
le p
erf
orm
an
ce
(GO
PS
)
Computation to communication ratio (OP/Byte access)
Computational roof (GOPS)
Design 2
Design 1
• Implementation can either be computation-bounded or memory-bounded
• Model performance to off-chip memory traffic
𝐴𝑡𝑡 𝑃𝑒𝑟𝑓 = 𝑚𝑖𝑛 ቊ𝐶𝑜𝑚𝑝𝑢𝑡𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑟𝑜𝑜𝑓𝐶𝑇𝐶 𝑟𝑎𝑡𝑖𝑜𝑛 × 𝐵𝑊
27© 2018 Microsemi
A Scalable Solution
28© 2018 Microsemi
Tiny YOLO v2.0 – PolarFire vs Zynq US+
Parameters PolarFire Zynq UltraScale+
Frame Rate 30fps 16fps
Device Power 3.5W 6W
mAP
(mean average
precision score)
45.1 48.5
Operating
Frequency200MHz n/a
29© 2018 Microsemi
Microsemi’s Advantage in Deep Learning Summary
Higher processing power due to efficient math block
Low power consumption
Scalable Deep Learning design provides optimum performance for available resources
30© 2018 Microsemi
PolarFire Tiny Yolo Video
