core-based socs testing julien pouget embedded systems laboratory (eslab) linköping university...

Core-based SoCs TestingCore-based SoCs TestingCore-based SoCs TestingCore-based SoCs Testing

Julien PougetEmbedded Systems Laboratory (ESLAB)

Linköping University

Julien PougetEmbedded Systems Laboratory (ESLAB)

Linköping University

22Julien Pouget, IDA/SaS/ESLABJulien Pouget, IDA/SaS/ESLAB SoCs’ TestingSoCs’ Testing

ContentsContents

IntroductionIntroduction Introduction to SoCs’ testingIntroduction to SoCs’ testing PhD workPhD work On-going research and future workOn-going research and future work


Introduction

B.Sc. Montpellier university, France 1998

Theoretical Physics & Electronics M.Sc. LIRMM, Montpellier university, France 1999

Microelectronics Ph.D LIRMM, Montpellier university, France 2002

SoCs’ testing: Test Scheduling and Architectural Solutions


ContentsContents



Introduction to SoCs’ Testing

PCBs SoCs

All functions are implemented on the same die



New problems Accessibility Power (test …) Number of test patterns Test time

Circuit test techniques External test

• Memory depth problems• Pin number limited• Reduced accessibility to system I/Os

BIST• Improved accessibility • Area overhead, DfT necessary• Isolation• IP: structure?

External-BIST Test • Trade-off…

DSPDSP

µPMPEG

SramSram UDL

soc

DSPDSP

µPMPEG

Sram

2

Sram

1UDL

socAnalyseur 2 Générateur 2

Analyseur 1

Générateur

1

Générateur 3Analyseur 3

Analyseur4

Générateur 4Analys.5



Core providers System designerSystem designer issue: adapt test architectures for every core in the design flow of the system

Test architecture normalisation for SoCs-P1500 Standard- Core access logic harmonisation Interface system/cores (TAM) design by system

designers


Introduction to SoCs’ Testing – P1500

Core wrapper

Test Access Mechanism

ADC PCI SRAM

CPU

wrapper

CUT ROM

MPEGUDL RAM

SOC


ContentsContents



PhD Research Work

3 steps Research direction

• Test schemes comparison

Wrapper Design Heuristic• Including P1500 mandatory modes

• Test time minimization

• Optimized connectivity

TAM Design• Bus based approach

• Co optimization mapping/scheduling


PhD Research Work

Test controllers implementation

Test schemes comparison Test time Area overhead Bus width Algorithmic complexity

ST 0,18µm implementation

Solution 1

Test time

Solution 2 Solution 3Solution 1

TAM – #E/S

ControllerArea (BIST)

Solution 2 Solution 3

Solution 1

Solution 2

Solution 3

Fixed SessionsVariable SessionsWithout

session


PhD Research Work

Core Test Interface Design (Wrapper) TAM width used/core core test time, global TAM Bandwidth limitation for test P1500 mandatory modes consideration

Normal mode (functional mode) Core Test Interconnections test Bypass

Heuristic :

I: Wlimit, core structure

O: Wneeded, Tmin, wrapper structure


Core5_D695

0

50000

100000

150000

200000

250000

2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 24 26 28 29 30 31 32 33 34 35 36 37 40 42 45 47 50 52 55 57 60 65 68 70 72 75 78 79 80 85 90

W

T

PhD Research Work

Pareto optimal points


PhD Research Work

TAM Design Wrapper built with the presented heuristic:

• Wi and Ti chosen by user for each core

Goal: Test Access Mechanism design• Bus based solution• Total test time minimisation

• Wtotal minimisation

3

2 1

4

W=5

T=19

W=2

T=15

W=8

T=20

W=5

T=21

33

22 11

44

W=5

T=19

W=2

T=15

W=8

T=20

W=5

T=21


PhD Research Work

TAM Design Exact method to generate the whole

possible solution space• Mathematic modelisation: Hypergraphs

representing all the incompatibility possibilities

Mapping: bus assignation• Fast Heuristic

Scheduling• Fast Heuristic• Power constraints• Incompatibilities• Precedence constraints

33 22 11

6655

44

8877

62 3 2 2

62 2

6Itération 1Itération 2

6

Itération 3 6

6

2

10

10

Itération 4

1010

10

Itération 5 3

3 3 3

15Itération 7Itération 6 7Itération 8 3

177 7

8

10

10

10

1(30)

2(33)

3(19)

5(11)

7(9)

6(29)

8(7)

5(7)

4(11)

W = 64W

T

t = 41


ContentsContents



On-going Research and Future Work

Test Scheduling based on Defect Probability SoC approach: Test process ended as soon as a defect is

detected ”abort-on-fail” Estimated Test Time determined by a probabilistic formula

using several schemes:• Sequential testing with fixed test times

• Sequential testing with flexible test times

• Concurrent testing with fixed test times

• Concurrent testing with flexible test times

Wrapper values pre-determined using the tools from PhD work

• 10 cores with 10 stages each means 1010 configuration possibilities !!!



Solution: heuristic Based on a ”schedule ASAP” concept maximizing the TAM use Allows reduced computation time Results close to optimal solutions (validated on small examples)

Next step - Close future Heuristic implementation

• Allow exploiting all the results from the wrapper design

• Will be applied on ITC’02 new coded benchmarks

Other possible algorithms to implement• For example maximising the intermediate test time



Low Heuristic complexity Aim: fix the NP complete problem of bin-packing Use of the defect probabilities to schedule the tests

2

0,710

20

2 500 000 5 000 000 7 500 000

3

0,85

W

1

0,9

4

0,85

t2

0,710

20

2 500 000 5 000 000 7 500 000

3

0,85

W

1

0,9

4

0,85

t

T =4 872 349 cycles

Tp =3 235 990 cyclesTime Tp weighted by pass probabilities

Maximisation of TAM width use choosing the adapted Wi/ti



Networks-on-chip Future: hundreds of elements on a chip:

Bus based solutions Network based communications Hardware/Software components

• Software already tested

• Hardware tested in production: new issue

Power problems Resource sharing problems Timing problems

Future focus: test of network-on-chip architectures

Questions?Questions?

core-based socs testing julien pouget embedded systems laboratory (eslab) linköping university...

Documents

socs testing pcbs socs

test time solution

test architectures

test scheduling

future work slide

session slide

die slide

wrapper structure slide