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CONSTRUCTING AN ARITHMETIC LOGIC

UNIT

CHAPTER 4: PART II

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An ALU (arithmetic logic unit)

• Let's build a 32-bit ALU to support the and and or instructions– we'll just build a 1 bit ALU, and use 32 of

them

• One Implementation (Figure A): Use a mux with AND/OR gates

• Another possible Implementation (sum-of-products of formula) in Figure B: Why isn’t this a good solution?

r0

r1

r2

r30

r31

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Review: The Multiplexor (mux)

• Selects one of the inputs to be the output, based on a control input

• Lets build our ALU using a MUX:

note: we call this a 4-input mux even though it has 6 inputs!

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• We will build a 1-bit ALU so some instructions from which we will build a 32 bit ALU for the instructions selected.

• Let's first look at a 1-bit adder:

• How could we build a 1-bit ALU for add, and, and or?

• How could we build a 32-bit ALU?

ALU Implementations

cout = a b + a cin + b cin

sum = a xor b xor cinSum

CarryIn

CarryOut

a

b

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Building a 32 bit ALU

• 1 bit ALU• Result = a operation b

• 32 bit ALU• a, b, Result are 32 bits each

b

0

2

Result

Operation

a

1

CarryIn

CarryOut

Result31a31

b31

Result0

CarryIn

a0

b0

Result1a1

b1

Result2a2

b2

Operation

ALU0

CarryIn

CarryOut

ALU1

CarryIn

CarryOut

ALU2

CarryIn

CarryOut

ALU31

CarryIn

CarryIn

CarryOut

ALU

a

b

Operation

Result

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• Two's complement approach: just negate b and add 1.• How do we negate?

• A very clever solution:

What about subtraction (a – b) ?

0

2

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b

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• Need to support the set-on-less-than instruction (slt)

– remember: slt is an arithmetic instruction

– produces a 1 if rs < rt and 0 otherwise

– use subtraction: (a-b) < 0 implies a < b

• Need to support test for equality (beq $t5, $t6, $t7)

– use subtraction: (a-b) = 0 implies a = b

Tailoring the ALU to the MIPS

Supporting slt: set on less than

• Can we figure out the idea?• We need 1 when the result of subtracting

is negative.• That is we need a 1 in the

least significant bit and a 0 elsewherewhen the result of subtracting hasa 1 in its most significant bit.

• Also 0’s in all bits when the result of subtracting has a 0 in its most significant bit.

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection

Overflow

a.

b.

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Seta31

0

ALU0 Result0

CarryIn

a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Binvert

CarryIn

Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

Supporting slt: set on less than

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Test for equality: beq

• Notice control lines:

000 = and001 = or010 = add110 = subtract111 = slt

• a - b is 0 if all bitsin a - b are 0. That isin the result, r = a - bNOT (r31 OR r30 OR … r0)

Note: zero is a 1 when the result is zero!

Seta31

0

Result0a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

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Interface Representation of 32 bit ALU

ALU ResultZero

Overflow

a

b

ALU operation

CarryOut

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Conclusion

• We can build an ALU to support the MIPS instruction set

– key idea: use multiplexor to select the output we want

– we can efficiently perform subtraction using two’s complement

– we can replicate a 1-bit ALU to produce a 32-bit ALU

• Important points about hardware

– all of the gates are always working

– the speed of a gate is affected by the number of inputs to the gate

– the speed of a circuit is affected by the number of gates in series(on the “critical path” or the “deepest level of logic”)

• Our primary focus: comprehension, however,– Clever changes to organization can improve performance

(similar to using better algorithms in software)– we’ll look at two examples for addition and multiplication

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• Is a 32-bit ALU as fast as a 1-bit ALU?• Is there more than one way to do addition?

– two extremes: ripple carry and sum-of-products

Can you see the ripple? How could you get rid of it?

c1 = b0c0 + a0c0 + a0b0

c2 = b1c1 + a1c1 + a1b1 c2 =

c3 = b2c2 + a2c2 + a2b2 c3 =

c4 = b3c3 + a3c3 + a3b3 c4 =

Not feasible! Why?

Problem: ripple carry adder is slow

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• An approach in-between our two extremes

• Motivation:

– If we didn't know the value of carry-in, what could we do?

– When would we always generate a carry? gi = ai bi

– When would we propagate the carry? pi = ai + bi

• Did we get rid of the ripple?

c1 = g0 + p0c0

c2 = g1 + p1c1 c2 =

c3 = g2 + p2c2 c3 =

c4 = g3 + p3c3 c4 =

Feasible! Why?

Carry-lookahead adder

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Fast Carry, First Level of Abstraction: Propagate and Generate

• ci+1 = (bi.ci) + (ai.ci) + (ai.bi) = (aibi) +(ai+bi)ci

= gi + pici, where gi = ai bi, and pi = ai + bi.

• c1 = g0 + p0c0

c2 = g1 + p1c1

= g1 + p1g0 + p1p0c0

c3 = g2 + p2c2 = g2 + p2g1 + p2p1g0 + p2p1p0c0

c4 = g3 + p3c3 = g3 + p3g2 + p3p2g1 + p3p2p1g0

+ p3p2p1p0c0

•ci+1 is 1 if an earlier adder generates a carry and all intermediate adders propagate the carry.

Plumbing analogy for First Level

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Fast Carry, Second Level of Abstraction: Carry look ahead

• Super PropagateP0 = p3.p2p1.p0

P1 = p7.p6p5.p4

P2 = p11.p10p9.p8

P3 = p15.p14p13.p12

• Super GenerateG0 = g3 + p3g2 + p3p2g1 + p3p2p1g0 G1 = g7 + p7g6 + p7p6g5 + p7p6p5g4 G2 = g11 + p11g10 + p11p10g9 + p11p10p9g8 G3 = g15 + p15g14 + p15p14g13 + p15p14p13g12

• Generate final carryC1 = G0 + P0c0

C2 = G1 + P1G0 + P1P0c0

C3 = G2 + P2G1 + P2P1G0 + P2P1P0c0

C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0

= c16

Plumbing analogy for Next LevelCarry Look ahead signals P0, G0

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Use principle to build bigger adders

CarryIn

Result0--3

ALU0

CarryIn

Result4--7

ALU1

CarryIn

Result8--11

ALU2

CarryIn

CarryOut

Result12--15

ALU3

CarryIn

C1

C2

C3

C4

P0G0

P1G1

P2G2

P3G3

pigi

pi + 1gi + 1

ci + 1

ci + 2

ci + 3

ci + 4

pi + 2gi + 2

pi + 3gi + 3

a0b0a1b1a2b2a3b3

a4b4a5b5a6b6a7b7

a8b8a9b9

a10b10a11b11

a12b12a13b13a14b14a15b15

Carry-lookahead unit

The 16 bit adder with carry look ahead

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• More complicated than addition– accomplished via shifting and addition

• More time and more area• Let's look at 3 versions based on grade school algorithm

0010 (multiplicand) x_1011 (multiplier)

• Negative numbers: convert and multiply– there are better techniques, we won’t look at them

Multiplication

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Multiplication: Implementation: 1st Version

Done

1. TestMultiplier0

1a. Add multiplicand to product andplace the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

64-bit ALU

Control test

MultiplierShift right

ProductWrite

MultiplicandShift left

64 bits

64 bits

32 bits

• Multiplier = 32 bits, Multiplicand = 64 bitsProduct = 64 bits.

• Initially Product is 64 bit Zero

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Multiplication: Implementation: 1st Version

Multiplicand x Multiplier: 2ten x 3ten = 0010two x 0011two = 0110two

Iteration Step Multiplier Multiplicand Product

0 Initial values 0011 0000 0010 0000 00001 1a: 1 => Prod = Prod + Mcand 0011 0000 0010 0000 0010

2: Shift left Multiplicand 0011 0000 0100 0000 00103: Shift right Multiplier 0001 0000 0100 0000 0010

2 1a: 1 => Prod = Prod + Mcand 0001 0000 0100 0000 01102: Shift left Multiplicand 0001 0000 1000 0000 01103: Shift right Multiplier 0000 0000 1000 0000 0110

3 1: 0 => no operation 0000 0000 1000 0000 01102: Shift left Multiplicand 0000 0001 0000 0000 01103: Shift right Multiplier 0000 0001 0000 0000 0110

4 1: 0 => no operation 0000 0001 0000 0000 01102: Shift left Multiplicand 0000 0010 0000 0000 01103: Shift right Multiplier 0000 0010 0000 0000 0110

Problem with 1st Version: 64 bit arithmetic, Half of multiplicand = 0!

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Multiplication: Implementation: 2nd Version

MultiplierShift right

Write

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test

Done

1. TestMultiplier0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

• Multiplier = 32 bits, Multiplicand = 32 bitsProduct = 64 bits.

• Product is 64 bit Zero

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Multiplication: Implementation: 2nd Version

Multiplicand x Multiplier: 2ten x 3ten = 0010two x 0011two = 0110two

Iteration Step Multiplier Multiplicand Product

0 Initial values 0011 0010 0000 00001 1a: 1 => Prod = Prod + Mcand 0011 0010 0010 0000

2: Shift right Product 0011 0010 0001 00003: Shift right Multiplier 0001 0010 0001 0000

2 1a: 1 => Prod = Prod + Mcand 0001 0010 0011 00002: Shift right Product 0001 0010 0001 10003: Shift right Multiplier 0000 0010 0001 1000

3 1: 0 => no operation 0000 0010 0001 10002: Shift right Product 0000 0010 0000 11003: Shift right Multiplier 0000 0010 0000 1100

4 1: 0 => no operation 0000 0010 0000 11002: Shift right Product 0000 0010 0000 01103: Shift right Multiplier 0000 0010 0000 0110

Problem with 2nd Version: Half of product is always = 0!

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Multiplication: Implementation: Final Version

• Multiplier = 32 bits, Multiplicand = 32 bitsProduct = 64 bits.

• Initially add Multiplier to Right half of Producti.e LeftProduct = 0, rightProduct = Multiplier

ControltestWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

Done

1. TestProduct0

1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register

2. Shift the Product register right 1 bit

32nd repetition?

Start

Product0 = 0Product0 = 1

No: < 32 repetitions

Yes: 32 repetitions

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Multiplication: Implementation: Final Version

Multiplicand x Multiplier: 2ten x 3ten = 0010two x 0011two = 0110two

Iteration Step Multiplicand Product

0 Initial values 0010 0000 00111 1a: 1 => Prod = Prod + Mcand 0010 0010 0011

2: Shift right Product 0010 0001 00012 1a: 1 => Prod = Prod + Mcand 0010 0011 0001

2: Shift right Product 0010 0001 10003 1: 0 => no operation 0010 0001 1000

2: Shift right Product 0010 0000 11004 1: 0 => no operation 0010 0000 1100

2: Shift right Product 0010 0000 0110

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Floating Point (a brief look)

• We need a way to represent

– numbers with fractions, e.g., 3.1416

– very small numbers, e.g., .000000001

– very large numbers, e.g., 3.15576 109

• Representation:

– sign, exponent, significand: (–1)sign significand 2exponent

– more bits for significand gives more accuracy

– more bits for exponent increases range

• IEEE 754 floating point standard:

– single precision [1 word]: 8 bit exponent, 23 bit significand

– double precision [2 words] : 11 bit exponent, 52 bit significand

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IEEE 754 floating-point standard

• Leading “1” bit of significand is implicit

• Exponent is “biased” to make sorting easier

– all 0s is smallest exponent all 1s is largest

– bias of 127 for single precision and 1023 for double precision

– summary: (–1)sign significand) 2exponent – bias

• Example 1:

– decimal: -.75 = -3/4 = -3/22

– binary: -.11 = -1.1 x 2-1

– floating point: exponent = bias + -1 = 127 - 1 = 126 = 01111110

– IEEE single precision: 1 01111110 10000000000000000000000• Example 2:

– decimal: 0.356

– binary: 0.01011011001 (can be more accurate) = 1.011011001 x 2-2

– floating point: exponent = 127 – 2 = 125 = 01111101

– IEEE single precision: 0 01111101 01101100100000000000000

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Floating Point Complexities

• Operations are somewhat more complicated (see text)

• In addition to overflow we can have “underflow”

• Accuracy can be a big problem

– IEEE 754 keeps two extra bits, guard and round

– four rounding modes

– positive divided by zero yields “infinity”

– zero divide by zero yields “not a number”

– other complexities

• Implementing the standard can be tricky

• Not using the standard can be even worse

– see text for description of 80x86 and Pentium bug!

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Chapter Four Summary

• Numbers can be represented as bits.

• Computer arithmetic is constrained by limited precision

• Bit patterns have no inherent meaning but standards do exist

– two’s complement

– IEEE 754 floating point

• Computer instructions determine “meaning” of the bit patterns

• Performance and accuracy are important so there are many complexities in real machines (i.e., algorithms and implementation).

• Arithmetic Algorithms have been presented.

• Logical representation of hardware to do some arithmetic operations have been given.

• We are ready to move on (and implement the datapath = ALU, registers).