conference on ''physics at the future colliders'', tbilisse, georgia, october...
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Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
The Selective Read-out Processor for the CMS Electromagnetic Calorimeter
Irakli Mandjavidze
DAPNIA, CEA Saclay,91191 Gif-sur-Yvette, France
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
2
Overview
Motivation and Goals The CMS ECAL read-out system and SRP SRP Challenges SRP Design
→ Platform FPGAs→ Xilinx Virtex-II Pro devices→ Firmware→ Optical communication channels
Current Status Conclusive remarks
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
3
Motivation and goals
CMS DAQ capabilities→ Total event size: 1 Mbyte
Allowed average ECAL event size: 100 Kbyte
→ Data throughput of 100 Gbyte/s
ECAL raw data→ Size: 1.5 Mbyte→ Bandwidth: 150 Gbyte/s @ 100 kHz L1 trigger rate
Reduction factor of almost 20 is necessary→ Crystal zero suppression: non-linearity and degraded energy resolution
Selective Read-Out→ Define zones of interest on event-by-event basis→ Read full precision data from channels within these zones→ Apply strong zero suppression on the rest of channels
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
4
The ECAL Read-out System
Trigger
Selective read-outprocessor: SRP
Front-end electronics
Rea
d-ou
t
High level triggers and DAQ
Raw data1.5 Mbyte
Selected data
Selectiveread-out flags
Triggertowerflags
5 µs timing budget
L1 Accept 100 kHz
40 MHz
100 Kbyte
ECAL
Asynchronous hard real-time system
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
5
Type of Selective Read-out Algorithms
Sliding windows algorithm→ Trigger towers (TT) are classified as
Suppressed Single Center
NN NNN
NN
NNNN NN
NN
NNNNN
NNNN C
Neighbors
ET
Low
High
→ Singles, centers, neighbors: full precision read-out→ Suppressed: zero suppression read-out → Complemented by coarse grain data
i.e. energy deposited in all TTs
Reduction factor of 20 → detector performance: no noticeable degradation 0.5 0.6 0.7 0.8 0.9 1.0
40
60
80
100
120
Low threshold (GeV)
Eve
nt s
ize
(KB
) High threshold 2 GeV
ZS (0σ)
ZS (1σ)
ZS (2σ)
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
6
SRP Challenges
Asynchronous operation at 100 kHz L1 trigger rate
5 µs timing budget
High number of input / output channels→ ~200 optical communication links
1.6 Gbit/s throughput per link
Certain flexibility to allow changes and evolution of selective read-out algorithms
Combine advances in technologies of→ the programmable logic (FPGA)→ the optical communication
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
7
SRP Architecture
Compact system: single VME 6U crate→ 12 identical VME64x compliant boards
3 boards covering each of 4 ECAL partitions
Note: the SRP board is used also as SRP tester
→ VME-PCI interface board with a contol PC→ Boindary Scan controller for remote firmware management
Just one custom board to develop and maintain
Halfbarrels
- +
End-cap +
End-cap
-
VME-PCIinterface
BoundaryScanController
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
8
SRP Boards
VME64x compliant board with PnP capability→3 firmware : « barrel », « end-cap », « tester »
sharing a bulk of VHDL code
P1 P2
VME buffers
VMESerial linksAlgorithmsTrigger IF
FPGA XilinxVirtex-II Pro
xc2vp70-6-ff1704
Power supply
Clocksynthesizer
Contrôleur JTAG
FPROMs
TTF
Rx
SRFTx
SRP
Rx
SRPTx
Parallel optics
Throttling
TTSOut O/E
Trigger, timing, and
control
Cons., JTAG
Aux.connector
Trigger Interface
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
9
SRP Boards
→ 12 layers, 1.6mm thick→ Up to 20 bidirectional optical communication links at 1.6 Gbit/s each→ 40 differential pairs with 100Ω controlled impedance→ Synthesizable clock→ Monster FPGA with 1704-pin ball grid array package
Reset
ReloadStratusLEDs
RS232Trigger
TTFSRF
SRP
Triggerthrottle
JTAG
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
10
Platform FPGAs
Xilinx 2vp70 Virtex-II Pro2 PowerPC 405 CPUs @ 300 MHz20 RocketIO transceivers up to 3 Gbit/s18 kbit dual-port memories
Flexible reconfigurable System-On-Chip Devices
Programmable logic cells→ combinatorial and synchronous
Versatile IOs→ Single ended and differential
Hard IP cores→ Clock management→ Memory blocks→ Serial transceivers→ Embedded processor(s)
Plus various soft IP cores→ Microcontrollers, network IF...
CPU
DCM MGT
MEMORY
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
11
Firmware
System-on-Chip design: handy for debugging and monitoring→ embedded 80 MHz PowerPC with 128 Kbyte memory
stand-alone “C” applications for testing, debugging and monitoring
→ 32-bit slave interface on a 40 MHz peripheral bus
SRP Barrel and Endcap: 6 000 000 equivalent logic cells: 40%→ 3.5 µs latency from L1 accept till SR flags delivered to the read-out
SRP Tester: 8 000 000 equivalent logic cells: 60%
Plenty of resources for future enhancements
Memory128 KB
Pro
cess
or b
us
PowerPC80 MHz
Bridge
RS232 console
Slave interface
SRP
board
80 MHz
pipeline
logic
40 MHz 40 MHz
32-bit R/W
Per
iphe
ral b
us
VME
Optical IO
Firmware organization
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
12
Trigger-SRP and SRP-Read-out links
Optical communication channels
Fan-in/Fan-outmodulesIndividual
LC fibers 12-fiber MTP cables
Serializer Tx
Trigger
Deserializer Rx
Readout
RxUp to 12
deserializersin FPGA
TxUp to 12
serializersin FPGA
SRP
Small form factorpluggable
transceivers
Pluggableparallel optic
modules
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
13
SRP-SRP links→ are needed to exchange information on frontiers→ passive optical cross-connect: all-to-all connectivity
Optical communication channels
RxUp to 8
deserializersin FPGA
SRP2
TxUp to 8
serializersin FPGA
SRP3
Passive optical cross-connect
Pluggableparallel optic
modules
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
14
Optical communication channels
Measurements done with the LeCroy Serial Data Analyzer
MPO/MPOcable 2m
LC/LCcable 30 m
TxSerial DataAnalyzer
Paralleltransmitter
FDM
0.8 UI @ 10-12 BER
~0.8 UI eye opening→ 0.65 is required for 10-12 BER by specifications
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
15
Some Photos
Test system with prototypes→ one card tests another
LeCroySerialData
Analyzer
Control PC
&
Consolefor the
embeddedSoC Processor
VME crate with thetwo prototypes
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
16
Some Photos
Test system with all 12 SRP boards→ organized as 6 barrel and 6 tester boards
Passive opticalcross-connect
VME crate with12 boards
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
17
Some Photos
Barrel SRP boards installed in the CMS service cavern
6 barrel SRP boards
Cross-connect & 12-fiber MPO cables
Patch-panel & 12-fiber MPO cables
Fan-in/Fan-out modulesand
individual LC fibers
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
18
Summary
All SRP boards produced and verified→ 12 + 4 spares + 2 completely operational prototypes→ up to 100 kHz trigger rate→ weeks of operation without communication link errors
6 barrel boards installed at CERN→ commissioning underway
6 end-cap boards to be commissioned early in 2008→ together with trigger and read-out electronics
6 spare boards as development systems → 4 at CERN and 2 at Saclay
Impatient to meet the very first collisions
[email protected] Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006
19
Les mots de la fin...
Just a little drop in the Sea(MS)...
→ Only one crate→ 12 electronic boards
but extremely attractive
→ Modern Platform FPGAs→ Multi gigabit per second links→ Parallel optics→ System-on-chip design
An insight of electronics to be used in HEP experiments at future colliders