Computing MachineryChapter 9: Personal Computers

The Mother of All Boards

Functional Layout of PC Motherboard

XT - Also called extended technology, this is the oldest of the Intel motherboard form factors, originally designed for the 8088 CPU.

AT - The AT (Advanced Technology) form factor replaced the XT, providing a software programmable configuration through BIOS () rather than hardwired jumpers.

Baby-AT - The Baby AT was the first attempt to reduce the size of the motherboard while maintaining a performance capability similar to the AT.

LPX/Mini-LPX - This form factor was the next step in miniturization of the PC with similar capability as the AT.

ATX/Mini-ATX - The ATX and Mini-ATX provide for the additional functions included in more modern PC's. This form factors also offers a lower voltage level (3.3volts rather than 5 volts).

NLX - This form factor is an updated version of the LPX/Mini-LPX designed to support laptops and slimline desktop PC's.

PC Motherboard Form Factors

XT

ATX

micro-ATX

Trends in Motherboard Form Factors

Back Panel I/O Connector Layout

8088 5 8 1MB

8086 5-10 16

286 6-1 16MB

386DX 16-40 32 4GB

386SX 16-33

386SL 20-25

486DX 25-100

486SX 20-40

Pentium 60-200 64

Pentium MMX 150-233

Pentium Pro 150-200

Pentium II 233-450

Pentium III 450-1.2GHz

Celeron Xeon 266-766

Xeon 400-3GHz

Pentium 4 1.4-3.06 GHz

CPU Clock Speed Bus Max RAM

8088 5 8 1MB

8086 5-10 16

286 6-1 16MB

386DX 16-40 32 4GB

386SX 16-33

386SL 20-25

486DX 25-100

486SX 20-40

Pentium 60-200 64

Pentium MMX 150-233

Pentium Pro 150-200

Pentium II 233-450

Pentium III 450-1.2GHz

Celeron Xeon 266-766

Xeon 400-3GHz

Pentium 4 1.4-3.06 GHz

CPU Clock Speed Bus Max RAM

Intel 'x86 Series of Processors

'x86 Registers

The chipsets are the integrated circuits on the motherboard that manage the transfer of information from one functional component to another.

In the early days of the personal computer, each data transfer function on the motherboard was performed by a separate IC.

Over time, the low-level intgration was replaced with higher-level integration in which multiple functions were combined in a single IC package.

The level of integration of these functions continued until we now have all the communications controlled contained in as few as two IC's called the northbridge and the southbridge.

By convention, we still refer to each of these IC's as a chipset.

Chipsets

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A read-only memory (ROM) is a type of memory that is fixed and unchangeable. Once a ROM has been loaded with a bit pattern, it cannot be changed.

Standard ROM memory is embedded into the IC at the time of manufacture. The bit patterns are chosen to represent data or instructions that will be accessed during the normal execution of the computer, but will not be changed.

An example use of ROM in a computer is to hold the first few instructions requied to start up or boot the computer.

The primary functional difference between ROM and RAM is that the contents of ROM persists even when power is off.

Read-Only Memory (ROM)

types of ROM

There are two types of random access memory (RAM). The first type called static RAM (SRAM) holds its contents after being written to only once, so long as power is applied. When power is off the contents of static RAM is lost. Due to cost, the use of SRAM is typically limited to cache memory.

Static Random Access Memory (SRAM)

Dynamic RAM or DRAM must be accessed frequently or its contents will be lost even when power is being applied.

The rate of refresh depends on the particular DRAM but typically the time between refreshes must be between a few microseconds and a few miliseconds.

The primary advantage of DRAM over SRAM is lower cost.

Dynamic Random Access Memory (DRAM)

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PROM (Programmable ROM) - a version of ROM that is manufactured with with no bit patterns but can be written to once by burning the bit patterned into its circuitry. PROM's cannot be altered after the bit pattern is set.

EPROM (Erasable PROM) - a version of ROM that can be written to more that once. These chips need to be reset out-of-circuit by exposure to UV light or some other non-electrical process.

EEPROM (Electrically Erasable PROM) - a version of ROM that can be rewritten by applying electrical signal alone. If the EEPROM can be rewritten while it is in-circuit, it is called a flash-programmable EEPROM.

Programmable Read-Only Memory (PROM)

DIMM (Dual Inline Memory Module) - a physical layout of RAM on a small circuit board with an edge connector that can be plugged into the memory slots of a motherboard. DIMM's support a 64 bit data path to the northbridge.

SIMM (Single Inline Memory Module) - a physical layout of RAM also on a small circuit board with an edge connector. SIMM's support a 32-bit data path.

Inline Memory Modules

SIMM

DIMM

EDO DRAM (Extended Data Output DRAM) - since data is partitioned into blocks, the EDO DRAM can read and write separate memory blocks simultaneously. SDRAM (synchronous DRAM) - this is a special type of RAM that runs faster than conventional RAM by sending multiple bits one each bus wire during the time required for one bit to be transferred. In conventional data transfer a bit must make it to its destination before the next bit is applied to the bus wire.

DDR SDRAM (Double Data Rate-Synchronous DRAM) - DDR SDRAM doubles the rate of data transfer by using both the rising and trailing edge of a logic pulse to carry data.

RDRAM (Rambus DRAM) - A proprietary version of DRAM by Rambus, Inc. RDRAM Short for Rambus DRAM, a type of memory (DRAM) developed by Rambus, Inc. In 1997, Intel announced that it would license the Rambus technology for use on its future motherboards, thus making it the likely de facto standard for memory architectures.

Modern Computer Memory

Cache (pronounced "cash" ) memory is a higher-speed but more costly type of random access memory that is used to increased the number of instructions per second that can be processed by a computer.

L1 Cache - The L1 cache is the cache that is closest to the CPU, usually inside the integrated circuit of the CPU itself.

L2 Cache - The L2 cache is larger than L1 cache but somewhat slower due to the greater distance to the CPU. In a dual-level cached system, the contents of the L2 cache is pre-fetched from main memory while smaller blocks of L1 cache are pre-fetched from the L2 cache.

Cache

Fully Associative Cache Memory

Direct Memory Mapping

Set-Associative Memory Mapping

Cache Timing

The best way to understand the advantage of multi-level cache memory is to look at an example of cache timing. Assume that a particular memory location is accessed 10 times over a short period of a programs execution and that the first attempt to access the address results in a cache miss.

We can further assume that cache access time is tc = 4 nsec while main memory access is tm = 35 nsec.

The total access time for the first call is given by,

t1 = tc + tm = 4 ns + 35 ns = 39 ns

Given that 1 out of 10 memory requests result in a miss (i.e. the probability of a cache hit phit is 90%), we can compute the total access time for 10 memory accesses,

ttot = tc + tm + (n-1)tc = 4 ns + tm + 9 tc

= 4 ns + 35 ns + 9x(4 ns) = 75 ns

so the average access time is given by,

tavg = ttot /n = 75/10 = 7.5 ns

The first attempt to access the memory word results in an access time of 39 ns, which is longer than a direct access to main memory (35 ns). After 10 accesses we have accumulated a total of 75 ns, for an average access time of 7.5 ns.

Bus

A communication bus is a set of parallel lines (wires) that connect two computing machinery components. The purpose of the bus is to provide a fast, simple and efficient means of data transfer. Buses are defined by their width (number of lines), and their speed (rate of data transfer).

Bus Organization (Width, Speed, Bandwidth)

The VSC has an 8-bit bus that carries data, instructions and addresses between the memory unit and the registers. The typical data bus includes lines for both the data and the address of the data (source or destination).

Direct Memory Access (DMA) or Bus Mastering

Bus mastering is the technique of providing circuitry to permit communication between peripherals without using the CPU.

Direct memory access (DMA), is a more advanced version of bus mastering, with which data transfer is completely independent of the CPU.

Bus mastering limits the level of communication with the CPU, but it needs to get permission to present data onto the bus and to inform the CPU that data transfer has been completed.

Memory Access through I/O Ports

Both ATA and SCSI disk controllers provide for bus mastering.

SCSI controller are more advanced than ATA controller, since they support a higher level of independence from the CPU.

All devices that communicate via a bus on the PC have their own addresses or I/O port numbers. The port number is necessary to communicate with the CPU or the RAM using memory mapping techniques.

A PC can access data and instructions from main memory (RAM) using the I/O ports

PCI Bus

The Peripheral Component Interconnect (PCI) bus is used to include peripheral devices to the motherboard of the PC. While we usually think of PCI peripherals as computer circuits on cards that are plugged into a PCI expansion slot, there are PCI devices integrated onto the motherboard, such as integrated graphics, audio, or network devices.

Synchronous Bus Data Transfer

The timing diagram for a synchronous bus read transaction is shown here. In this transaction the bus master provides an address for the transaction and sets the W/R signal to the read mode. The data supplier (slave) present data onto the bus and alerts the bus master that the data is ready to be read by setting the wait signal to logical low.

Hennessy & Patterson, Computer Architecture: A Quantitative Approach. Ch. 7

Asynchronous Data Bus Transfer

Asynchornous data transfers are typically slower than synchronous transfers, however, they support a much wider range of peripheral types. The timing diagram for an asynchronous write bus transaction is shown below. During an asynchronous write operation, the bus master presents the address and data to the bus. The receiver (slave) decodes the address during a predetermined time interval (between T0 and T1).

BIOS (Basic Input/Output System)

BIOS is the machine code that is run first when a PC is powered up. This BIOS software is hardwired into a ROM IC on the motherboard. The process of automacially loading and executing the BIOS instructions is called booting up the computer.

BIOS can also be said to be a coded program embedded on a chip that recognizes and controls various devices that make up the computer. In other classes of computer the BIOS is referred to as the boot loader, boot ROM, or boot monitor

AGP Video

Modern PC's include an AGP (Accelerated Graphics Port) slot on the motherboard for the addition of a high-performance graphics/video perpherial card. Intel developed the AGP specification independent of the PCI Special Interest Group.

The AGP communication channel is independent of the PCI and is restricted to the management of video/image data. The purpose of the AGP is to support 3D rendering and animations at a high-frame rate.