IEEE Tanactiont6 on NuLctea Science, Vlot.NS-24, No.6, Decembe't 1977

COMPUTER AIDED ANALYSIS OF RADIATION HARDENED CMOS MSI/LSI DESIGNS

Robert J. Antinone, David R. Alexander, and Gerald W. Brown

Abstract: Computer-aided circuit analysistechniques are utilized to predict theperformance of individual CMOS cells andcombinations of such cells which mightbe found in medium scale integratedcircuits. The predictions includestatistical variations, thermal effects,loading effects, and radiation effectsincluding variations due to appliedbias. Experimental data from testsconducted on devices from a special testwafer are compared to the predictionsto provide verification of results.

INTRODUCTION

Fabrication procedures developed at Sandia

Laboratories for radiation-hardened CMOS can consis-tently produce inverters which exhibit reliable

operation at total dose levels in excess of 106 rad(Si). While this performance is conceptually compa-!tible with the design and fabrication of MSI/LSIcircuits with comparable radiation hardness, numerousengineering problems must be solved before designguidelines can be formulated which take full advantageof the technology. The designer must anticipate theresult of total dose radiation on each of the cells inhis design and provide sufficient design margin toinsure operation within the specifications for circuitperformance over the required temperature range. Inparticular, capacitive loading, which is primarilydetermined by fanout to other cells and interconnectpatterns, must be adjusted to be consistent with thedrive capability of MOS transistors after irradiation.Also, design adjustments must be made to eliminateripple through problems in flip-flops and race condi-tions in complex chains of logic cells.

Computer-aided circuit analysis and design is avaluable tool in evaluating the effects of radiation,temperature, and loading on the performance of cellsused in MSI/LSI fabrication. In some instances, suchas determining performance as a function of loading orinvestigating radiation effects at high temperatures,computer-aided circuit analysis is the only practicalprocedure available. The parasitic capacitance addedin direct measurement is often greater than the loadcapacitance of interest; and annealing of damage athigh temperatures makes any direct measurement ofradiation effects suspect.

The remainder of this paper presents the resultsof an investigation aimed at applying computer-aidedcircuit analysis and design to the development ofhardened CMOS, MSI/LSI devices. The investigationconsidered three aspects of the design problem for theSandia Hardened CMOS process. These included: (1)effects on circuit performance of statistical varia-tions in preirradiation transistor characteristics,

This work sponsored by the Energy Research and Develop-ment Administration and monitored by Sandia Labora-tories under Contract 03-5961.

R. J. Antinone and D. R. Alexander are with TheBDM Corporation, Albuquerque, New Mexico.

G. W. Brown is with Sandia Laboratories, Albuquerque,New Mexico.

(2) effects of temperature Qn cell operation, and (3)degradation in cell characteristics due to total doseionizing radiation. The cells included in the studywere samples from the topologies available in the RCAaluminum gate standard cell library.

MODEL CHARACTER I ST I CS2,3

The SPICE2 " computer program developed by theUniversity of California at Berkeley was used inmaki ng all predictions in the investigation reportedhere. A built-in SPICE2 model incorporates severalsecond order effects which are important in thisstudy. They include:

(1) Substrate bias effects(2) Two dimensional threshold voltage effects(3) Weak inversion effects(4) Channel length modulation effects(5) Variable mobility effects(6) Temperature effects(7) Variable capacitance effects

For a general description of the MOS model the readeris directed to reference 3. The weak inversion,temperature, and variable mobility effects are ofsufficient importance to the results of this programto be discussed briefly.

Most MOS models assume that conduction beginsabruptly once the gate voltage exceeds the thresholdvoltage, where the threshold voltage is calculated fora surface potential, ( ,s which is equal to twice the

Fermi level ((s = 2 (Pf). The SPICE2 model has imple-

mented the results of Swanson and Meindl in modelingthe drain current in the weak inversion region(ps (f). SPICE2 includes the effects of fast

surface density (NFS) and two dimensional geometryon the threshold voltage as well as the usual QSSand f terms. For gate voltages less than the

classical threshold voltage, drain current ismodeled by an exponential function of gate voltage.For applied gate voltages greater than threshold, thestandard drain current equations are used. Total doseradiation can produce changes in the drain charac-teristics through variations in both the number offast surface states (NFS) and the oxide charge (QSS).

The intrinsic transconductance, K,

= K = DO Cox )

is a function of the surface E-field as determined bythe gate-to-source voltage. SPICE2 reflects thisdependence through an empirical equation which incor-porates a critical electric field and parameters whichrepresent the degree of degradation due to perpen-dicular and transverse fields. This equation may befit to either pre- or postirradiation data by varyingthe appropriate parameters.

The temperature dependence of MOS transistorcharacteristics is included in the SPICE2 modelthrough appropriate variations in the threshold vol-tage. All terms in the threshold equation in whichthe Fermi level appears are updated for temperaturealong with all terms multiplied by T. Temperaturevariations are also included in K values, diode leak-age currents, and the exponential term of the bipolardiode equation used to model the drain-to-substrateand source-to-substrate parasitic diodes.

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In applying computer aided circuit analysis anddesign techniques to the prediction of cell perfor-mance, the model described above must be combined withelements describing the parasitic resistance and cap-acitance associated with metallization interconnects,source/drain diffusions, and tunnel diffusions. Inthis investigation metallization-to-silicon capaci-tances associated with VDD or VSs lines were elimi-

nated since these lines were held at a constant vol-tage. Parasitic capacitances associated with source!drain or tunnel diffusions were modeled as voltagevariable capacitors. The resistance associated withthese diffusions was modeled with two resistor ele-ments in series and a voltage variable capacitanceconnected to their mutual node. The schematic infigure 1 shows the result of including the parasiticelements in the circuit diagram of an 1120 NOR gatecell. The voltage variable capacitances are shown ascombined diode capacitor symbols.

00 (

TEST CH I P

Test Chip Description. A special test chip wasfabricated to provide both parameterization infor-mation and verification vehicles for the evaluation ofthe computer model predictions. The chip containedbasic parameterization structures such as large areaMOS capacitors (field oxide and gate oxide), bipolar

diodes (N to P-well and P to substrate), gateddiodes, Van der Pauw structures, four-point probedevices, pinched channel transistors, and inverterswith varying geometries. These structures were usedto determine pre- and postirradiation data for com-puter model parameterization.

The test chip also included standard cells con-nected in several circuit configurations to serve asverification vehicles for the model predictions.Figure 2 is a schematic representation of the cellinterconnections contained in the standard cell block.They include a ring oscillator, an inverter chain, aNAND gate chain, a NOR gate chain, an inverter pair,and a 1480 flip-flop. Complete, parasitic inclusivemodels were implemented in SPICE2 for each of thesecells and cell interconnections. The parameterizationdata from the special structures described previouslywere used to determine model element values. Some ofthis data is presented in the following paragraphs.

9070 2 1 1 131

Figure 2. Standard CellCMOS Test Chip

Figure 1. Schematic Diagram of CMOS Cell 1120Showing Parasitic Elements Used inSPICE2 Model.

The determination of the parasitic resistor and

capacitor values was made with the aid of the CMAT5computer code developed at Sandia. CMAT performslogical operations on the various levels of fabri-cation masks to identify coincidences corresponding toparasitic elements. For example, the metallization

mask and N+ diffusion mask can be logically combinedand areas of coincidence denoted as metal/thick

oxide/N capacitances. CMAT provides both a graphicaldisplay of parasitic locations and a listing of theirnumerical values. For this investigation, all para-sitic resistance and capacitance resulting from drainor source diffusions under the gate (the result oflateral diffusion or gate overlap) were attributed to

the transistor model. All other parasitics were

included as elements external to the model.

Interconnections from

Transistor Model Parameterization. Two wafers oftest chips fabricated in the same diffusion lot were

dedicated to preirradiation parameterization of theSPICE2 NMOS and PMOS transistor models. The resultsof the measurements to determine threshold voltage(VT) and transconductance

0 Coxfrom those devices are shown in figures 3, 4, 5, and6. Figures 3 and 4 show the distribution in thresholdvoltage from wafers 1 and 2 for NMOS and PMOS tran-

sistors respectively. The smooth curve is the plot ofa normal distribution with the same mean and standarddeviation as the distribution with the greatest stan-

dard deviation. The values of VT were determined from

plots of drain current versus gate voltage with a

drain voltage of 50 mV and the device operated in thelinear region. Figure 5 and 6 show the distributionin 0 values from wafers 1 and 2 for NMOS and PMOS

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transistors respectively. The value of 5 was deter-mined from the slope of the VGS versus ID plots

(VDS = 50 mV).

These distributions in transistor parameters werereflected in the SPICE2 models as variations in thesubstrate doping concentration (N SUB), effectivesurface state density (NSs), and effective surfacemobility (p ). For PMOS devices, the substrate dopingconcentration was considered to be constant and thevariations in VT were reflected in the NSs variable.For NMOS devices, both NSUB and NSs were varied tosimulate the VT variations. In both transistor types,S variations were reflected in the p0 parameter.

Three sets of model parameters were used in theprediction of standard cell response. The first setwas based on the mean values of VT and 5; the secondwas based on the highest value of VT and lowest valueof 5, and the third was based on the lowest value ofVT and highest value of 5. The lowest and highestvalues of VT and 5 represented the +3a points of thedistributions shown in figures 3 through 6. Bymaking predictions based on the three sets of modelparameters, the performance of the cells can be brack-

eted and presented to a designer for use in nominal,best case, and worst case design tradeoffs. Predic-tions of performaince for each standard cell were madefor each set of models at temperatures of -55°C, 27°C,and +125°C. Some of the results of those predictionsfor the interconnections shown in figure 2 are pre-sented in the following section.

Variations in the model parameters due to totalionizing radiation dose were determined from radiationtests on sample devices from the two wafers of testcells. Irradiations were performed at 5 x 10 , 1 x

105, and 6 x 105 rad (Si) for both VGS = 10 V andV = 0 V on the NMOS and PMOS transistors. Post-GSirradiation measurements on these devices were used todetermine VT and X values as a function of dose.These changes in transistor characteristics werereflected in modifications to the NSs and pi modelparameters shown in table 1. The parameter variationsgiven in table 1 were used only with the mean valuesof model parameters. No attempt was made to establishthe upper and lower bounds for the postirradiationperformance. The relationship between the preirradia-tion and postirradiation distributions in VT and 5 isnot sufficiently understood to permit such predictionsat this time.

3 REL.rREQ.

IREL.8

FREQ.

80

72-

64

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40

32

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27. 3

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1 .60 1 64632 iO 2 .i 5

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CELL LIMITS

Figure 3. Distribution of N-Channel ThresholdVoltages from Two Wafers.

FREQ.

7.5

CELL LIMITS

Figure 4. Distribution of P-Channel ThresholdVoltages from Two Wafers.

r- --I

C(ElI L LIM T5

Figure 6. Distribution of P-Channel 's (Gains)froni Two Wafers.

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3REL.FREQ.

CELL LIMIlTS

Figure 5. Distribution of N-Channel 6's (Gains)for Two Wafers.

il [l

2 .(

80

IIIIIIIIIIIIIIIII

---4.

TABLE 1. SPICE2 MOr)FL 'i'ARAMETER VARIATIONS WITH DOSE

5 x 10 VGS =10

5 x 10 VGS = 0

IGS6 x 105 VGS = 10

I x 105v = 0

6 x 15 V = 10

6 x l o5 v =

N-Channel P-Channel

AN Ss %1i AN s %iSS to NSS to

1.05 x lo11 100 8.32 x 1010 loO

1.05 x 1011 100 8.32 x 1010 loo

2.22 x 1011 91 1.08 x lO loO

2.22 x 1oll

5.55 x 1o11

1.26 x 1o11

91 1.08 x lo1l 100

85 1.69 x 1011 94

85 1.11 x 1011 94

Comparison of Predictions and Experimental Data.Predictions of operati ng characteristics in terms ofrisetime, falltime, and propagation delay for each ofthe cells and interconnections shown in figure 2 weremade as a function of temperature, loading, and totaldose. Temperature and loading predictions were madefor each of the models representing the -3a, mean, and+3cr points in the transistor characteristics distribu-tion. This resulted in over 300 separate calculationsof cell, performance. Since 50 percent to 50 percentpropagation delay is perhaps the most universallyaccepted characterizati.on ',of circuit performance, itwill be used for the comparison of predictions withexperimental results. Representative examples ofthose comparisons are presented in the followingsection.

Statistical and Temperatu re Effects.. Exampleresults of the predictions for propagation delay as afunction of temperature are shown in figure 7. Theupper curve in this figure represents predictionsbased on maximum threshold voltages and minimum 5values. The middle and lower curves represent meanvalue and minimum V - maximum 5 predictions respec-Ttively. The mean values of experimental data areshown and the error bars indicate the range of thedata. For the 1120 NOR gate chain, the measured-dataare grouped about the mean value predictions with atendency to be slightly above the mean value predic-tions at the -55°C and +125%C temperatures. Since

250

225

200

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11AX VT MIN KT

PREDiCTiONS i

fiEAN VALUE

7 ~~~~~~~~~~~~~~~-PREDICTIONSMI1N VT - MAX KTPRIEDICTIONS 9 MEAN EXPERIMENTAL DATAA

CL = 10 pF

80 100 20 40TM 4N 60

TEMPERATURE °C

these measurements were made in an oven and the 27°Cmeasurements were not, the tendency toward higherpropagation delays is probably the result of a slightincrease in capacitance due to the increased cablelengths required for the measurements at temperature.For all cell interconnections, predictions indicatethat the differences between propagation delays ofgood devices (low propagation delays) and bad devices(high propagation delays) are widened with increasingtemperature. The experimental data confirms thistrend. The very worst devices appear to degrade themost, while the very best devices degrade the least.This tendency is not clearly shown by devices whichfall near the mean. The great majority of the experi-mental data falls within the prediction boundaries,and the concept of bounding the variations in propa-gation delays with predictions based on the +3apoints appears valid.

Loading Effects. The additional dimension addedto design considerations by loading factors is demon-strated in figure 8. It shows the variation in high-to-low propagation delay as a function of capacitiveload and temperature for the inverter chain composedof the 1520, 1310, and 9860. With the exception of asingle point at 27°C, these data all fall within theboundaries established by the +3u model parameters.Only experimental data for 10 pF external loads wereavailable.

ADD

150-

< 100.

o' 75

50 -

MAX VT - MIN K

/EDICTTION

XPREDtCTIONS

"*MIN VT - MAX K - PREDICTIONSPREDiCT1014S

" EAN EXPERIlMENTAL DATA

T - +27'C

CAPAC IT VE LOAD (PF)

Figure 8. Comparison of Predictions and Experi-mental Data for High-to-Low Propaga-tion Delay - 3 Inverter Chain.

Radiation Effects. The effect of radiation onpropagation delay for the 1220 NAND gated chain andthe 1480 flip-flop are shown in figures 9 through 12.In both the irradiations and predictions, two diffe-rent bias conditions were considered. The two biasesessentially resulted in VG = 10 V for one conditionand VGS = 0 V for the other condition for most of thetransistors in each circuit connection. The experi-mental data at the highest radiation level has beenslightly offset so that the difference in the two biasconditions can be observed. Both sets of data were

actually taken at 6 X 105 rad (Si). The predictionscovering the temperature range from -55°C through+1250C range are shown for the 1480 flip-flop cell.However, experimental data were only taken at -55°Cand 27°C due to the difficulty in identifying theeffect of annealing at 125°C.

Examination of the curves and the experimentaldata shows that the correct trend in propagation delay

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Figure 7. Comparison of Predictions and Experi-mental Data for High-to-Low Propaga-tion Delay - 1120 NOR GATE.

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with total dose and bias condition was always pre-dicted. The absolute accuracy of the predicitons wasgenerally sufficient to be useful as a design tool.Note that only the mean value model parameters wereused for this prediction. No attempt was made tobound the upper and lower limit of propagation delayas a function of dose. Advances in understanding thebasic mechanisms of total dose damage in MOS tran-sistors and availability of test data on larger testsamples should make such an analysis possible in thefuture.

The generally good agreement between the experi-mental data and the predictions in figures 9 through12 for the different bias conditions are especiallynoteworthy. Also, the agreement for both the -55°Cand +270C temperature ranges is encouraging.

Conclusion. Examination of the comparison of thepredictions and experimental data presented in theprevious section indicates that computer aided circuitanalysis can be a beneficial tool in bounding thevariations in cell performance due to processingvariations which inevitably occur in even a closelycontrolled, hardened CMOS production facility. Theresults of such analyses can be of major benefit ininsuring that the circuits designed from the hardenedprocess take full advantage of the technology.

The major cost involved in performing such anal-yses lies in the initial programming of the standardcell models. The inclusion of parasitic elements inthese models is essential for accurate predictions tobe achieved. Although automated programs such as CMATare tremendously beneficial, model development stillrequires a well trained analyst.

Once the models are implemented, the computersolutions are relatively inexpensive. The average run

costs $6 on a CDC6600. A high degree of automationcan also be achieved in these predictions so thatseveral variations of model parameters, temperatures,loading, and radiation effects can be run with summaryresults provided as an output. Periodically pro-cessing a test chip wafer set and upgrading the modelparameters based on the resulting data, allows thelatest processing characteristics of a production lineto be utilized in design.

REFERENCES

1. G. F. Derbenwick and B. L. Gregory, "ProcessOptimization of Radiation-Hardened CMOS IntegratedCircuits," IEEE Transactions on Nuclear Science,NS-22, No. 6, pp. December 1975.

2. E. Cohen, "Program Reference for SPICE2,'" Elec-tronics Research Laboratory Memorandum, June 1976.

3. D. R. Alexander, R. J. Antinone, and G. W. Brown,SPICE2 MOS Modeling Handbook, BDM/A-77-071-TR,16 May 1977.

4. R. M. Swanson and J. D. Meindl, "Ion-ImplantedComplementary MOS Transistors in Low VoltageCircuits," IEEE Journal of Solid State Circuits,vol. SC-7, no. 2, pp. 146-153, April 1972.

5. B. T Preas, B. W. Lindsay, and C. W. Gwyn,"Automatic Circuit Analysis Based on Mask Infor-mation," 13th Design Automation ConferenceJournal, pp. June 1976.

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