1 combinational ics - cs | computer scienceweb.cs.ucla.edu/logic_design/slpdf/ch3.pdf ·...
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1COMBINATIONAL ICs
• REPRESENTATION OF BINARY VARIABLES AT THE PHYSICAL LEVEL
• BASIC SWITCH. STRUCTURE OF GATES AND THEIR OPERATION
• REALIZATION OF GATES USING cmos CIRCUITS
• CHARACTERISTICS OF CIRCUITS: LOAD FACTORS AND FANOUT FACTORS, PROP-
AGATION DELAYS, TRANSITION TIMES, AND EFFECT OF LOAD
• THREE-STATE GATES (DRIVERS) AND BUSES
• NOISE AND NOISE MARGINS
• EVOLUTION OF ICs. VLSI CIRCUIT-LEVEL DESIGN STYLES
• PACKAGING LEVELS: CHIPS, BOARDS AND CABINETS.
Introduction to Digital Systems 3 – Combinational ICs
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2REPRESENTATION OF BINARY VARIABLES
• REPRESENTATION OF 0 AND 1 BY ELECTRICAL SIGNALS
• VOLTAGES
• CURRENTS
• ELECTRICAL CHARGES
• REALIZATION OF CIRCUITS THAT OPERATE ON THESE SIGNALS TOIMPLEMENT DESIRED SWITCHING FUNCTIONS
TYPICAL VALUES FOR A 3.3V cmos TECHNOLOGY
VHmax 3.3V VLmax 0.8VVHmin 2.0V VLmin 0.0V
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3VOLTAGE REGIONS
VHmin
VHmax
VLmin
VLmax
Forbidden region
VH region
VL region
voltage
Figure 3.1: VOLTAGE REGIONS.
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4POSITIVE AND NEGATIVE LOGIC
x
yzf
POSITIVE LOGIC
VH ←→ 1VL ←→ 0
NEGATIVE LOGIC
VH ←→ 0VL ←→ 1
Input Output Positive Negativevoltages voltage logic logicx y z x y z x y z
VL VL VL 0 0 0 1 1 1VL VH VL 0 1 0 1 0 1VH VL VL 1 0 0 0 1 1VH VH VH 1 1 1 0 0 0
f = and f = or
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5STRUCTURE AND OPERATION OF GATES
SWITCH AND mos TRANSISTORS
N-TYPE:
open (off) if VCA < VTn
closed (on) if VCA > VTn
VTn – THE THRESHOLD VOLTAGE FOR N-TYPE SWITCH
P-TYPE:
open (off) if VBC < VTp
closed (on) if VBC > VTp
VTp – THE THRESHOLD VOLTAGE FOR P-TYPE SWITCH
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6
Resistance between A and B very high: switch OPEN (off)
Resistance between A and B very low: switch CLOSED (on)
p-type switch
Resistance between A and B very low: switch CLOSED (on)
Resistance between A and B very high: switch OPEN (off)
n-type switch
VTn VTp
+
-
VBC
pS
A
B
C
A
B
C+
-V
CA
nS
VCA VBC
(a)
NMOS transistor logicalsymbol
PMOS transistor logicalsymbol
drain
sourcegate
A
B
C
A
B
C
B
A
C
(b)
source
draingate
A
B
C
Figure 3.3: a) N-TYPE AND P-TYPE CONTROLLED SWITCHES. b) nmos AND pmos TRANSISTORS.
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7CMOS NOT GATE
• COMPLEMENTARY MOS CIRCUIT
x
pS
nS
(a)(b)
z x z
A
C
B
Ground (0V)
pS closednS open
pS opennS closed
VTpVDD -
(d)
VHVL
vin
VH
VL
vout
(c)
VDD
voutvoutvin vin
VDD
VDD
vout
vinVDDVTn
x
10
z
01
zx
Figure 3.4: CIRCUIT, I/O CHARACTERISTIC, AND SYMBOL
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8OPERATION OF not GATE
VBC = VDD − vin (VDD = VBC + vin)
1. vin < VTn =⇒ VCA < VTn
=⇒ N-SWITCH OPEN
If VDD > VTn + VTp then VBC > VTp
=⇒ P-SWITCH CLOSED AND vout = VDD
2. vin > VDD − VTp =⇒ VBC < VTp
=⇒ P-SWITCH IS OPEN
If VDD > VTn + VTp then VCA > VTn
=⇒ N-SWITCH IS CLOSED AND vout = 0
CIRCUIT OPERATES AS not IF
VLmax < VTn, VHmin > VDD − VTp
VDD > VTn + VTp
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9NAND and NOR GATES
Circuit 2: NORCircuit 1: NAND
x
yz
x
yz
VDD
z
x
y
z
VDD
x
y
Figure 3.5: CIRCUITS FOR NAND and NOR GATES.
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10
NAND and NOR GATES (cont.)
Circuit 1 Circuit 2x y z z
0 0 1 10 1 1 01 0 1 01 1 0 0
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11AND and OR GATES
AND OR
xy
zxy
z
z
VDD
x
y S1
S2
S3 S4 S5
S6
VDD
x
y
z
S1 S2
S3
S4
S5
S6
Figure 3.6: CIRCUITS FOR and and or GATES.
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12COMPLEX GATES
z = (uv + xy)’ z = [(u+v)(x+y)]’
OR-AND-INVERT (OAI)
u
v
x
y
z
AND-OR-INVERT (AOI)
u
v
x
y
z
Figure 3.7: COMPLEX GATES.
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13
u v x y
VDD
z
VDD
u v x y
VDD
z
VDD
S1
S2
S3
S4 S5
S6
S7
S8
Figure 3.7: EXAMPLES OF COMPLEX GATES.
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14TRANSMISSION GATE
x z
C’
C
C01
n-switchoffon
p-switchoffon
zZx
Z - high impedance state
(a)
Figure 3.8: a) TRANSMISSION GATE
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15XOR WITH TRANSMISSION GATES
x
z
y
TG1
TG2
zx
y
(b)
Figure 3.8: b) xor GATE
y TG1 TG2 z
0 on off x
1 off on x′
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16MUX WITH TRANSMISSION GATES
z
s
TG1
TG2
s
zMUX
0
1
(c)
x0
x1x1
x0
Figure 3.8: c) 2-INPUT mux.
z = mux(x1, x0, s) = x1s x0s′
s TG1 TG2 z
0 on off x0
1 off on x1
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17TIMING PARAMETERS
low
high90% 90%
10% 10%
rise time fall time
Input
Output
low
high
high
low
high-to-lowpropagation delay
50%
50%
50%
50%
low-to-highpropagation delay
t pHL t pLH
(a)
(b)
tft r
t
t
Input Output
Figure 3.9: a) PROPAGATION DELAY. b) RISE AND FALL TIMES.
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18EFFECT OF LOAD
Gate1
Gate2
Gate4
Gate3
a
b
c d
a
z
Figure 3.10: A GATE NETWORK
R inC in
Gatei in
vin
Figure 3.11: EQUIVALENT CIRCUIT FOR GATE INPUT.
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19EFFECT OF LOAD ON PROPAGATION DELAY
Input voltage
Output voltage
low
high
high
low
Load A
Load B
t pLH (for load A)
t pLH (for load B)
Load B > Load A
Figure 3.12: EFFECT OF LOAD ON PROPAGATION DELAY.
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20LOAD FACTOR AND TOTAL LOAD
Gate2
Gate3
Gate5
Gate4
Gate1
(Driving gate)
Load factor: 1
3
1
2
Total load:
7
Figure 3.13: OUTPUT LOAD OF GATE 1.
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21VOLTAGE VARIATIONS AND NOISE MARGINS
Output levels
Forbidden region
Input levels
VHmin(OUT)
VLmax(OUT)
VHmin (IN)
VLmax (IN)
Noise margins
Figure 3.14: NOISE MARGINS.
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22NOISE MARGINS: EXAMPLE
LEVELS NOISE MARGINHIGH VHmin(out) 2.4 V 0.4 V
VHmin(in) 2.0 VLOW VLmax(out) 0.4 V 0.4 V
VLmax(in) 0.8 V
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23CONNECTING MODULES TO A BUS
ModuleM0
s0
ModuleM1
s1
ModuleMk
sk
y
a0
a1
ak
(bus line)
Figure 3.15: GATE NETWORK FOR SELECTING A MODULE OUTPUT.
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24
THREE-STATE DRIVER (BUFFER)
(c)
y
a0
s0
ModuleM0
ModuleM1
a1
s1
s2
s3
ModuleM3
a3
ModuleM2
a2
bus
s0=s2=s3=0s1=1
Figure 3.16: c) EXAMPLE OF USE OF THREE-STATE DRIVERS
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25
VDD
three-state circuit
xy
nS
pSe g
h
three-state circuit operation(b)
0 0 1 0 open open Z0 1 1 0 open open Z
1 0 1 1 open closed 01 1 0 0 closed open 1
e x g h pS nS y
(enable)
(a)
y= x if e=1Z if e=0{x
e
y
symbol function
Figure 3.16: a) THREE-STATE GATE: SYMBOL AND FUNCTION. b) CIRCUIT AND OPERATION.
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26
Table 3.2: Characteristics of a family of cmos gates
Gate Fan- Propagation delays Load factor Sizetype in tpLH tpHL
[ns] [ns] [standard [equiv.loads] gates]
and 2 0.15 + 0.037L 0.16 + 0.017L 1.0 2and 3 0.20 + 0.038L 0.18 + 0.018L 1.0 2and 4 0.28 + 0.039L 0.21 + 0.019L 1.0 3or 2 0.12 + 0.037L 0.20 + 0.019L 1.0 2or 3 0.12 + 0.038L 0.34 + 0.022L 1.0 2or 4 0.13 + 0.038L 0.45 + 0.025L 1.0 3
not 1 0.02 + 0.038L 0.05 + 0.017L 1.0 1nand 2 0.05 + 0.038L 0.08 + 0.027L 1.0 1nand 3 0.07 + 0.038L 0.09 + 0.039L 1.0 2nand 4 0.10 + 0.037L 0.12 + 0.051L 1.0 2nand 5 0.21 + 0.038L 0.34 + 0.019L 1.0 4nand 6 0.24 + 0.037L 0.36 + 0.019L 1.0 5nand 8 0.24 + 0.038L 0.42 + 0.019L 1.0 6nor 2 0.06 + 0.075L 0.07 + 0.016L 1.0 1nor 3 0.16 + 0.111L 0.08 + 0.017L 1.0 2nor 4 0.23 + 0.149L 0.08 + 0.017L 1.0 4nor 5 0.38 + 0.038L 0.23 + 0.018L 1.0 4nor 6 0.46 + 0.037L 0.24 + 0.018L 1.0 5nor 8 0.54 + 0.038L 0.23 + 0.018L 1.0 6xor 2* 0.30 + 0.036L 0.30 + 0.021L 1.1 3
0.16 + 0.036L 0.15 + 0.020L 2.0xor 3* 0.50 + 0.038L 0.49 + 0.027L 1.1 6
0.28 + 0.039L 0.27 + 0.027L 2.40.19 + 0.036L 0.17 + 0.025L 2.1
xnor 2* 0.30 + 0.036L 0.30 + 0.021L 1.1 30.16 + 0.036L 0.15 + 0.020L 2.0
xnor 3* 0.50 + 0.038L 0.49 + 0.027L 1.1 60.28 + 0.039L 0.27 + 0.027L 2.30.19 + 0.036L 0.17 + 0.025L 1.3
2-or/nand2 4 0.17 + 0.075L 0.10 + 0.028L 1.0 22-and/nor2 4 0.17 + 0.075L 0.10 + 0.028L 1.0 2
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27LEVELS OF INTEGRATION
Level of Technology Number of Typical functionsIntegration transistors
ssi bipolar ≈ 10 Individual gates, flip-flopsmsi mos, bipolar 10-100 Adders, counters, registerslsi mos, bipolar 100-10,000 ROMs, PLAs, small memoriesvlsi mos, bipolar > 10,000 large memories, microprocessors,
complex systems
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28VLSI CIRCUIT-LEVEL DESIGN STYLES
FULL-CUSTOM
SEMI-CUSTOM (standard cells)GATE-ARRAY
a’
b’
c’
abd
a’c
c’d
y
z
a
b
c
d
Vertical routingchannel
Horizontal routingchannel
(y = abd + a’c + c’d)
(z = a + b)
Figure 3.17: EXAMPLE OF GATE ARRAY.
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29PACKAGING LEVEL: CHIPS, BOARDS, AND CABINETS
chip
Silicon wafer
pin
chip-to-pin wire
Enclosed chip(IC package)
Figure 3.18: SILICON WAFER, CHIP AND INTEGRATED CIRCUIT PACKAGE
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30
ICIC
Printed circuit board (PCB)
ICs
Connector
PC boards
Backplane with connectorsand wiring
Rack
Power supply
Cabinet with racks, PC boards and auxiliaryequipment
Cooling fans
PC boards
racks
Figure 3.19: PACKAGING LEVELS
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31PACKAGING LEVELS: EXAMPLE
IBM 3081 central processing unit:
Level of Number of SizePackaging Components [mm×mm]
Module 100–133 chips 90× 90PC Board 6 – 9 modules 600× 700Subsystem (processor) 3 boardsSystem (CPU) 2 subsystems
Introduction to Digital Systems 3 – Combinational ICs