company logo final presentation spring 2008/9 performed by: alexander pavlovdavid domb supervisor:...
TRANSCRIPT
Company
LOGO
Final presentationSpring 2008/9
Performed by:Alexander Pavlov David Domb
Supervisor:Mony Orbach
GPS/INS Computing
System
GPS/INS Computing
System
AgendaAgenda
1. General overview1. General overview
2. Our Project2. Our Project
4. Results4. Results
GPS/INS Computing System
3. The Design3. The Design
5. Summary5. Summary
GPS/INS Computing System
General overviewGeneral
overview“Even Noah got no salary for the first six months partly on account of the weather and partly because he was learning navigation.”
Mark Twain
Theoretical Navigation Algorithm Theoretical Navigation Algorithm
0
•Initialization
1
•Particle Propagation
2
•Particle Update & Normalization
3
•State Estimation
4
•Effective N calculation
5
•D computation
6
•Re-sampling
7
•Regularization
8
•Weight Re-computation
GPS/INS Computing System
Developed in the “Technion” and Implements the tightly coupled INS/GPS navigation unit, with the particle filter.
The algorithm stages:
Project GoalsProject Goals
Establishing the efficiency of the particle filter based, tightly coupled INS/GPS navigation unit realization.
Designing an efficient real-time particle filter based, tightly coupled INS/GPS navigation unit.
GPS/INS Computing System
GPS Computing System
Our Project
GeneralGeneral
• Our goal was to implement Particle Propagation and State Estimation stages.
• Both stages were required to function within 0.01 sec.
GPS Computing System
Group Project GoalsGroup Project Goals
Implementation of Particle Propagation and State Estimation stages of algorithm
Successful integration with other groups for evaluating the entire algorithm’s implementation.
GPS/INS Computing System
GPS/INS Computing System
TheDesign
Solution – Top designSolution – Top design
GPS/INS Computing System
Weight vector
Particles propagation
unit
State estimation
unit
Estimated State Vector
[1..18]
xN Extended State Vector
[1..18]
Extended State Vector
[1..18]
Extended State Vector
[1..18]
Co
ntro
ller
Basic architectureBasic architecture
• 24Bit words data bus.• FIFO-Like streaming interfaces
( Request + Empty / Full )• Controlled By Start/Finished activation mechanism
BasicStreaming
Block
Start Finished
Data in
Write requestFull
Data outRead request
Empty
Control
Input Path
Output Path
Particle propagation unitParticle propagation unit
GPS/INS Computing System
clockreset
start
finish
ParticlePropagation
Unit
X[0..439]
INS[0..287]
X_OUT[0..439]
Particle propagation unitParticle propagation unit
GPS/INS Computing System
Propagation Unit 1
Propagation Unit 2
Propagation Unit 6
MUX(6 to 1)
Propagationtimingcontrol
Single particle propagation data flowSingle particle propagation data flow
Format inputs to 48 bits
Calculate trigonometric
functions• Latitude sin/cos
Format trigonometric
function output to 48 bits
R_E, R_e, R_N calculation
Denominator calculation
• d_longitude denominator• d_latitude denominator
Dividers• d_longitude• d_lattitude• R_e
Particle
Propagation
GPS Computing System
Propagationflow
control
Estimation unitEstimation unit
GPS/INS Computing System
clockreset
New_Data_In
Estimation_Ready
EstimationUnit
X[0..439]
W[0..23]
ESTIMATED_DATA[0..439]
Estimation unitEstimation unit
GPS/INS Computing System
W
X Σ Estimated Data×
GPS Computing System
RESULTS
Physical implementationPhysical implementation
GPS/INS Computing System
Physical implementation of entire design was unsuccessful due to lack of FPGA resources.
Therefore, only 1 of the 6 parallel “propagation unit” blocks was implemented.
Resources utilizationResources utilization
GPS/INS Computing System
Base design(Without our
Logic)
Base + Our design
(Without trig Logic)
Base + Full design
(Including trig Logic)
Resources analysisResources analysis
GPS/INS Computing System
A design with 6 prop units will need approximately: • 130K combinational ALUTs (85K available).• 162K logic registers (85.2K available).• 20M block memory bits (8.25M available).• 4074 DSP blocks (896 available).
Possible FPGAs:• Xilinx – Virtex6 / 7.• Altera – Stratix 5 (possible).
Timing AnalysisTiming Analysis
GPS/INS Computing System
The implemented design of 1 prop unit produced:• Particle LATENCY – 97 clock cycles (from
“start” to “finish”) @100MHz = 1uSec:
Timing AnalysisTiming Analysis
GPS/INS Computing System
The implemented design of 1 prop unit produced:• Throughput of 38 clock cycles (from “finish” to
“finish”) @100MHz = 380nSec
Timing AnalysisTiming Analysis
GPS/INS Computing System
The total time with the implemented design of 1 prop unit produced was 30,000 particles in 1,140,059 100MHz clocks = 11.4mSec.
Note that the clock frequency of 100MHz was changed from the original plan of 30MHz, due to working with only one prop unit.
Accuracy resultsAccuracy results
GPS/INS Computing System
We have encountered many problems while trying to test our results:• The “Generic program” for 1 FPGA did not
work correctly – we were unable to control the inputs to the design.
• The “Generic program” for 4 FPGAs did not work as anticipated with the SW data files:o The SW data input files were arranged not
according to the “bits order” agreed upon.o The program’s data output files did not
reflect the output values from our design correctly.
Accuracy resultsAccuracy results
GPS/INS Computing System
We have made a manual accuracy check for one particle, by comparing the result as viewed with the “signal tap” tool to the SW result.
For the tested particle, we got a location result which was different from the SW result by 0.0002%:
SW RESULT OUR RESUL
0.0910404 0.0910405814647675
GPS Computing System
Group’s goals achievement Group’s goals achievement
GPS/INS Computing System
Implementation of our design:• PARTIAL - due to lack of FPGA
resources.
Design testing and integration:• PARTIAL - due to problems with the
testing environments and no cooperation from other design teams (which finished their project).
Our conclusionOur conclusion
GPS/INS Computing System
In terms of possibility – it seems that it is possible to implement the “Propagation” and “Estimation” stages of the project, within the necessary timing requirements, on a better, more powerful FPGA (without changing the design)
For integration with other projects, it is important to have the project’s teams present. Otherwise, it can’t be done efficiently.