IMPLEMENTATION OF HIGH SPEED DIGITAL CHANNEL

High Speed Digital System LabFinal Presentation1 semester project

Instructor Mony Orbach

Students Pavel Shpilberg Ohad Fundoianu

Acquaintance and Learning noise sources and physical attributes of High Speed Digital Channels

Implementation of SerDes transceiver up to 3Gbps on ALTERA Stratix2GX SI Development board

Watching measuring and understanding Signal Integrity phenomena

Design a high speed 4 channels transmitter for academic research

Targets

QUARTUS

Equipment

Stratix 2GX and Signal Integrity Development Board

Agilent 8000B Series Infiniium Oscilloscope

HS Digital Channel Definition

Amplitude Dependent Noise CT ISI Timing PS Independent Noise Skin effect Ohmic and

Dielectric loss EMI Jitter RJ-DJ Example

CRU disturbed by Jitter

Physical Attributes and Noise sources

1rr d r d r

lt t t t l Distributed System

f c c

( ) [2 ( )]d jS t P f t t

PLL - Phase Locked Loop Used for filtering noise and achieving high rates

810b - DC-balanced coding which prevents errors insures right sampling of the signal

Salient used Mechanisms

memorymemory

Implementation of high speed channel

Transmitter

Scope

816 2Receiver

816

FPGA GX GX FPGA

Digital validation

Analog validation

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Acquaintance and Learning noise sources and physical attributes of High Speed Digital Channels

Implementation of SerDes transceiver up to 3Gbps on ALTERA Stratix2GX SI Development board

Watching measuring and understanding Signal Integrity phenomena

Design a high speed 4 channels transmitter for academic research

Targets

QUARTUS

Equipment

Stratix 2GX and Signal Integrity Development Board

Agilent 8000B Series Infiniium Oscilloscope

HS Digital Channel Definition

Amplitude Dependent Noise CT ISI Timing PS Independent Noise Skin effect Ohmic and

Dielectric loss EMI Jitter RJ-DJ Example

CRU disturbed by Jitter

Physical Attributes and Noise sources

1rr d r d r

lt t t t l Distributed System

f c c

( ) [2 ( )]d jS t P f t t

PLL - Phase Locked Loop Used for filtering noise and achieving high rates

810b - DC-balanced coding which prevents errors insures right sampling of the signal

Salient used Mechanisms

memorymemory

Implementation of high speed channel

Transmitter

Scope

816 2Receiver

816

FPGA GX GX FPGA

Digital validation

Analog validation

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

QUARTUS

Equipment

Stratix 2GX and Signal Integrity Development Board

Agilent 8000B Series Infiniium Oscilloscope

HS Digital Channel Definition

Amplitude Dependent Noise CT ISI Timing PS Independent Noise Skin effect Ohmic and

Dielectric loss EMI Jitter RJ-DJ Example

CRU disturbed by Jitter

Physical Attributes and Noise sources

1rr d r d r

lt t t t l Distributed System

f c c

( ) [2 ( )]d jS t P f t t

PLL - Phase Locked Loop Used for filtering noise and achieving high rates

810b - DC-balanced coding which prevents errors insures right sampling of the signal

Salient used Mechanisms

memorymemory

Implementation of high speed channel

Transmitter

Scope

816 2Receiver

816

FPGA GX GX FPGA

Digital validation

Analog validation

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

HS Digital Channel Definition

Amplitude Dependent Noise CT ISI Timing PS Independent Noise Skin effect Ohmic and

Dielectric loss EMI Jitter RJ-DJ Example

CRU disturbed by Jitter

Physical Attributes and Noise sources

1rr d r d r

lt t t t l Distributed System

f c c

( ) [2 ( )]d jS t P f t t

PLL - Phase Locked Loop Used for filtering noise and achieving high rates

810b - DC-balanced coding which prevents errors insures right sampling of the signal

Salient used Mechanisms

memorymemory

Implementation of high speed channel

Transmitter

Scope

816 2Receiver

816

FPGA GX GX FPGA

Digital validation

Analog validation

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

PLL - Phase Locked Loop Used for filtering noise and achieving high rates

810b - DC-balanced coding which prevents errors insures right sampling of the signal

Salient used Mechanisms

memorymemory

Implementation of high speed channel

Transmitter

Scope

816 2Receiver

816

FPGA GX GX FPGA

Digital validation

Analog validation

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

memorymemory

Implementation of high speed channel

Transmitter

Scope

816 2Receiver

816

FPGA GX GX FPGA

Digital validation

Analog validation

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Stratix 2 transmitter

Phase compensatio

n

Byte serialize

r

8B10B

Encoder

Serializer

PLL

m

n

m

m

1

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Stratix 2 reciever

Word Aligner

Deserializer

1 1PLL+CRU

Byte Deserialize

r

8B10B Decode

r

Rate matche

r

n

Phase compensation

n

nmmm

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Channels Type Implemented

Single Transiver with effective data rate of up to 325 Gbps

memorymemory Transmitter8 2

Receiver8

Single Transiver with effective data rate of up to 6375 Gbps

memorymemory Transmitter16 2

Receiver16

Single Transiver with CRU (clock recovery unit) turned off

memorymemory Transmitter8 2

Receiver8

clk

Four transmiters on single chip- each one in different freq and different line type (longstripline microstripline)

2

memorymemory Transmitter

8

Receiver

2

2

2

8

8

8

8

8

8

8

Features Transfer data from memory to memory with high rate Features The highest frequency possible on this transiverFeatures Both transmitter and receiver get clocks (different ones)Synchronization depends on data

Features Each transceiver in different block- requires different clock connection to each of the trancievers

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Serial data 2496Mbps signal - 40rdquo Line Regular

StripLine

Signal integrity Measurements

Volt Graph

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Serial data 2496Mbps signal

40rdquo Line Regular StripLine

Measurements (2) Eye Diagram

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

1248Mbps signal ndash Regular StripLine

Clock signal Serial data

Measurements (3) - Jitter

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Pre-Tap First Post-Tap

Second Post-Tap

Measurements (4) - PreEmphasis

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Features of XAUI transciever Four random data outputs at 3125 Gbps rate

All four outputs are aligned and have constant delay (delay between different channels is constant and does not change on reset or turn down)

The design is saved in EPCS64 chip so there is no need to reconfigure the device when turning on

An output clock indicates when data cycle is done

Data cycle length can be easily changed to any number (2n-310 for all n)

All four channels must be the same type (strip line)

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15

Implementation of transceiverXAUI

2

2

Transmiter

XAUI

Parallel clk

mem

counter2

2

16

16

16

16

mem

mem

mem

• Implementation of high speed digital channel
• Slide 2
• Slide 4
• Slide 5
• Slide 6
• Stratix 2 transmitter
• Stratix 2 reciever
• Slide 9
• Slide 10
• Slide 11
• Slide 12
• Slide 13
• Slide 14
• Slide 15