communication systems, 5e - homepages at wmubazuinb/ece4600/ch07_04.pdf · analog communication...
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Communication Systems, 5e
Chapter 7: Analog Communication Systems
A. Bruce CarlsonPaul B. Crilly
© 2010 The McGraw-Hill Companies
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Chapter 7: Analog Communication Systems
• Receiver block diagram design• Image frequency bands that may cause
spurious responses (more filter requirements)• Signal Multiplexing
– Frequency division (FDM) and – Time division (TDM)
• Phase-Lock Loops (PLL)
© 2010 The McGraw-Hill Companies
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Receiver Design: Linear Technology
• For possible RF front-end design architectures, see: http://www.linear.com/docs/12457
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Receiver Design: Analog Devices
• For possible RF front-end design components, see: http://www.analog.com/media/en/news-marketing-collateral/product-selection-guide/RF-and-Microwave-ICs-Selection-Guide.pdf
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Wireless Connectivity: Texas Instruments
• For possible RF solutions, see: http://www.ti.com/lit/sg/slab056d/slab056d.pdf
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The Phase-Locked LoopOne of the most important structures in
communicationsApplications:• Frequency Synthesis
– With tuning steps for radios
• Synchronous Signal Regeneration– FM Pilot, TV color burst, etc.– Coherent AM and DSB demodulator/detector
• Clock generation for digital electronics• FM demodulator/detector
… and much more
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Phase-lock loopFigure 7.3-2
Phase Lock Loop Model
• Phase Comparator• Loop Filter• Loop Gain• VCO
A linearized system model in phase is used
for analyzing performance
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Phase comparators (a) analog Figure 7.3-1
Analog Phase Comparator
• Performance depends on the small angle approximation • A “linear” capture range (linearize sin about zero)
2
ttcostcosAAtcosAtcosAte ccvcvvccphase
t2AAtsin
2AA
2tcos
2AAte vcvcvc
phase
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Phase comparators (b) digital Figure 7.3-1
Digital Phase Comparator
• The operation tracks leading and lagging edge comparisons of two digital, 50% duty cycle, square-wave inputs– Typically, bipolar current pulses are output that represent which
signal leads and how much time mismatch there is.
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Phase-lock loop: Figure 7.3-2
Phase Lock Loop Math (1)
ttf2t cc
2
ttff2t vcv
t
vv dyK2t
2
22
tttfttt vvc
Phase Equivalents in Boxes
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Phase-lock loop Figure 7.3-2
Phase Lock Loop Math (2)
tyK2dt
tdf2dt
tdv
dt
tdf2tsinK2dt
td
av KKK
tsinKK2dt
tdf2dt
tdav
Steady State Operation Derivation = 0
A non-linear differential equation
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Phase Lock Loop Math (3)
• For a stable input frequency reference
• At steady state
• Resulting in
Kftsin
dttd
K21
Kftsin
Kfarcsinss K
f1
0dt
td
0dt
td
for
2
2cos 0 sscss tftv
v
assass Kf
KfKsinKy
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Phase Lock Loop Math (4)
• Other steady state inferences: The transient response
• with the transient error solution of
• From before, we can define a frequency “capture” range for “locking-the-loop” as
0tsinK2dt
td
00 ttK2exptt
Kf
1
fK KffKf vv
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Linearized PLL Models
• Using a loop model that defines the phases offsets of the sine or cosine waveforms
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Linearized PLL models (a) time domain (b) phase domainFigure 7.3-8
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
PLL Phase Models
s
sKsHK1
sHKsY cv
a
a
sHKKs
sHKsssY
va
a
c
Linearized PLL models (b) phase domain(c) Laplace domainFigure 7.3-8
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PLL Model Frequency Response
• Frequency Response for
• Frequency Response for
Hva
Ha
c KKKsKKs
ssY
HKsH
H
Hps
psH
HvaH
2Ha
c pKKspspKs
ssY
sHKKs
sHKsssY
va
a
c
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PLL Model Steady State Error
• Error
• For
• For 00lim 2
2
0
cHvaH
H
sss pKKspspss
ssHKKs
sHKss
K1sYs
Kss cva
avvc
ssHKKs
ss cva
HKsH 00KKK
slim cHva
2
0sss
ssHKKs
sslim cva
0sss
H
Hps
psH
s
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PLL Integrated CircuitAnalog Devices ADF 4360-9 Clock Generator PLL with Integrated VCOPrimary output frequency range: 65 MHz to 400 MHzAuxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz• 3.0 V to 3.6 V power supply• 1.8 V logic compatibility• 3-wire serial interface• Digital lock detectAPPLICATIONS• System clock generation• Test equipment• Wireless LANs• CATV equipment
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Loop Filter
VCO Tuning
Ref Clock
R: 14 bits – 1:16383N=B: 13 bits – 1:8191Extra A: 2 to 31
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PLL References
• Analog Devices Technical Articles• http://www.analog.com/library/analogDialogue/cd/vol33n1.pdf
– Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 1
• http://www.analog.com/library/analogDialogue/cd/vol33n1.pdf#page=11
– Phase-Locked Loops for High-Frequency Receivers and Transmitters - Part 2
• http://www.analog.com/library/analogDialogue/cd/vol33n1.pdf#page=15
– Phase Locked Loops for High-Frequency Receivers and Transmitters – Part 3
• http://www.analog.com/library/analogDialogue/cd/vol33n1.pdf#page=20
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PLL Applications
• Frequency Synthesis• Synchronous Detection
– Costas Loop
• FM Demodulation
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Frequency Synthesis (1)
• Synthesizing higher frequencies with known step sizes
• Divide fref to provide a reference (or smaller) step size
• Divide fout for input at the phase comparator
• Resulting in
R1 dtte
N1
Rf
Nf refout
Rf
Nf refout
stepref fRf
refout fRNf
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Frequency Synthesis (2)
• The method used by the book is not wrong, but …• The method used on the previous slide is much
more common. (Hint: likely exam material)– Advantages: one IC, simple programming, test circuits
available.– Simple Design: Select fref, N(A,B) and R– Tricky parts:
• picking comparison frequency … fref/R• Making sure N and R dividers are within the ICs range
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refout fRNf
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PLL pilot filter with two phase discriminators: Figure 7.3-3
Providing a Synchronous LO
For systems where a carrier can be isolated, such as AM, FM Stereo, NTSC-TV, etc.
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FM Demodulation with a PLL (1)
ffHKKfj
fHKfjsY cav
a
fj
fXf f
c
22
fj
fXfHKKfj
fHKfjsY f
av
a
HKsHLet
FM Input
LPF of Message
PLL Phase
fX
fHKKfjfHKsY
av
af
fXKKKfj
KKsYHav
Haf
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FM Demodulation with a PLL (1)
• For FM signals in the passband of the LPF
– The output would be
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Hav
vHav
HaLPF
KKKfjKKKKfj
KKsPLL
1
11
fXK
sYv
f
Hav KKKf
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SW Cad III PLL Example PLL2
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SW Cad III PLL Example PLL
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Improved Loop Filter
PLLTest.asc
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Analog Tracking
PLLTestv1.asc
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Old Television, Monochrome
• A composite time waveform that provides:– Raster scanning of a rectangular area
• 525 Lines per frame in NTSC
– Periodic voltage levels that cause horizontal and vertical synchronization (white, black, sync levels)
• 15.75 kHz Line Frequency• 60 Hz Field Frequency
– Video Bandwidth 4.2 MHz
– See Figure7.4-2 for one scan line time waveform– See Figure 7.4-5 for composite spectrum
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Time Waveforms:Analog Video 101 from NI
• http://zone.ni.com/devzone/cda/tut/p/id/4750• Periodicity:
• Line spectrum interference from TVs– Horizontal resolution (pixel) derived in text– Horizontal retrace ~15.75 kHz
Vvn
Hhm2jexpcv,hI nm
nm
tfnfm2jexpctx vhnmnm
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Figure 7.4-6
Old Monochrome TV transmitter
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Figure 7.4-7
Old Monochrome TV receiver
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Figure 7.4-10
Old Color subcarrier modulation system
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Figure 7.4-11
Old Color demodulation system
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Figure 7.4-12
Scene capabilities of conventional NTSC system and HDTV
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Viewing angles as a function of distance
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(a) conventional NTSC (b) HDTV
Figure 7.4-13
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HDTV transmitterCopyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Figure 7.4-14
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Figure 7.4-15
HDTV receiver