common mode gain

8/11/2019 Common Mode Gain

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Section G3: Differential Amplifiers

The differential amplifier may be implemented using BJTs or FETs and is acommonly used building block in analog IC design. We are going to beconcentrating on the BJT implementation of the differential pair asemitter-coupled, common-emitter (or emitter-resistor) amplifiers. Inaddition to providing the input stage of the operational amplifier, thisconfiguration is the foundation for emitter-coupled logic (ECL), a very highspeed, universally employed family of logic circuits.

The simplest form of thedifferential amplifier is shown tothe right (a modified version ofFigure 9.1 in your text). Thiscircuit is formed using two

matched transistors (Q 1 and Q 2),in the CE configuration whoseemitters have been tied together.The differential pair has twoinputs (v 1 and v 2), and threepossible outputs (v o1 , v o2 , andv out ).

A couple of notes about thiscircuit:

The output voltage, v out , is the difference between v o1 and v o2 , or.

21 ooout v v v = The notation of the emitter resistor R E has been changed to R EE since is

common to both amplifiers. As we will see shortly, this resistor may bethe equivalent resistance of a current source as discussed in the previoussection, both to save chip space and reduce fabrication complexity(transistors are smaller than resistors and its easier to make a wholebunch of the same thing). However it is created, it is necessary that R EE have a large value to keep the voltage drop across it nearly constant withreasonable changes in current.

The resistors R C in the circuit above may be replaced with othertransistors in some applications (once again, to remove the requirementof resistive components). It is absolutely imperative however, thatwhatever is in the collector circuit ensures that Q 1 and Q 2 never entersaturation.

To solve for the dc transfer characteristics of the differential amplifier, webegin by using the expression for base-emitter voltage derived from


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Equation 4.10. In terms of total instantaneous voltage and collector current,v BE and i C, we now have

=

O

C T BE I

i V v ln ,

where I o is the reverse saturation current and we have once again assumedthat n=1. Using this relationship, and neglecting base currents so thatiE iC, we can express v BE1 and v BE2 as

=

=

O

E T BE

O

E T BE I

i V v

I i

V v 221

1 ln;ln . (Equation 9.2, Corrected)

Now, writing the KVL equation about the base junction loop as indicated by

the red path in the figure above, we have

02211 =+ v v v v BE BE . (Equation 9.1, Modified)

Assuming we have matched devices , V T and I O are the same for Q 1 and Q 2 .Substituting the information of Equation 9.2 into Equation 9.1, rearrangingand employing the property of logarithms [ln(A)-ln(B)=ln(A/B)],

=

=

=

=

+

2

121

2

12121

221

1

ln

/ /lnlnln

;0lnln

E

E

T

OE

OE

O

E

O

E

T

O

E T

O

E T

i i

V v v

I i I i

I i

I i

V v v

v I i

V I i

V v

. (Equation 9.3, Modified)

Taking the exponential of both sides of the last equation above, we can solvefor the current ratio, i E1 /i E2 :

==

=

T T

T

V v v

E E V

v v

E E

V v v

E

E

ei i and ei i

or ei i

)(

1221

2

1

2121

21

; . (Equation 9.4, Modified)

A KCL at the coupled emitters of Q 1 and Q 2 yields


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21 E E EE i i i += . (Equation 9.5)

Substituting the information from the modified version of Equation 9.4 intoEquation 9.5, we can find final expressions for i E1 and i E2 in terms of circuitand physical parameters. Note that in the equations below, i E1 iC1 andiE2 iC2 . Recall however that the emitter and collector currents are actuallyrelated by i C= iE, where = /( +1) 1 for >>1.

[ ]

[ ]T EE

C E

T

EE C E

V v v i

i i

V v v i

i i

/)(exp1

/)(exp1

2122

2111

+=

+=

. (Equation 9.6)

Lets look at what the results of Equation 9.6 tell us.

For a given current i EE, the amplifier responds only to the differencebetween the voltages applied to the bases of Q 1 and Q 2 (i.e., v 1 and v 2 inFigure 9.1 and in the equations above). This is the foundation ofdifferential amplifier operation (and is where the name comes from).

If v 1=v 2=v ci (well talk about the v ci and v di notation in a couple ofminutes), i E1 =i E2 =i EE /2 and the current is split evenly between the twotransistors for any value of common-mode voltage, v Ci.

If the differential voltage, v di=v 1 -v 2 , becomes greater than about 4V T ( 100mV), the current i EE will flow almost entirely in one of the twotransistors. Specifically,o if v di >100mV, approximately 98% of i EE will flow through Q 1 and Q 2

will be essentially cut off, oro if v di


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I am going to take a slightly different approach that your author in the nextsegment of this discussion, but I will attempt to keep all notations the same. Note that in all of the following analyses we will assume that r o is very largeso that it may be neglected unless specifically stated otherwise.

Differential Mode Gain

For differential-mode operation, we apply an ac differential voltage, v di ,between the bases of Q 1 and Q 2 , in addition to a dc common mode voltagev Ci. From the symmetry of the differential pair, this differential input signalshould divide evenly between the base emitter junctions of the twotransistors. In terms of the differential and common-mode voltages, theoriginal input voltages of Figure 9.1 may be expressed as

2221

di Ci

di Ci

v v v and

v v v =+= . (Equation 9.9, Modified)

Note that v 1-v 2=v di , which is whatwe want. This is true since the inputto Q 2 is equal in magnitude to thatof Q 1 , but 180 o out of phase(indicated by the negative sign). Thesmall signal model of the differentialamplifier in differential mode isillustrated in Figure 9.2a and isreproduced to the right. Using thesymmetry of the differential pair andcomparing the notation of this circuitwith Figure 9.1, we have v out =v od and |v o1 |=|v o2 |=v od /2. Note thatalthough v o1 and v o2 are of equalmagnitude, they are 180 o out of phase (i.e., v o1 =-v o2 ).

Modifying Equation 9.6 to reflect the differential input voltage v di ,

[ ]

[ ]T di EE

C E

T di

EE C E

V v i

i i

V v

i i i

/exp1

/exp1

22

11

+=

+=

.

Analyzing the above relationships, we can see that as the current onetransistor increases, the current through the other transistor decreases atthe same rate. Therefore, since the total current through R EE never changes,


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the voltage change across R EE is zero. This means that the ac signal voltageacross R EE is zero and the resistor may be replaced with a short circuit in theac equivalent, as shown in the above figure.

If the transistors are biased at an emitter current of i EE /2, and with R EE

effectively shorted for ac operation, another way of looking at the currentincrease/decrease may be developed in terms of r , where r = r e , assuming>>1. A KVL in either base loop yields

eeebbdi r i r i r i

v === 2.

Solving for i e , we get an expression for the current increase/decrease to be

e

di e r

v i

2= . Assuming i C iE, the output at each collector terminal will be 180 o

out of phase with a magnitude of

222|||| 21

di C m

e

C di od oo

v Rgr Rv v

v v ==== ,

or, the voltage measured between the two collector terminals will be

di C me

C di od v Rgr

Rv v == .

As indicated above, the output of the differential amplifier may be takeneither differentially (or double-ended) , where the output is takenbetween the two collectors, or single-ended , where the output is takenfrom either collector to ground.

If the output is taken between the collector terminals, the differential gain (differential, or double-ended output) of the amplifier will be equal to

e

C C md r

RRg A

== . (Equation 9.12)

As stated earlier, the single-ended output voltages at v o1 and v o2 are ofequal magnitude, and are each one-half the magnitude of the double-endedoutput voltage, v od . If the output is taken between either collector terminaland ground, the differential gain (single-ended output) of the amplifierwill be equal to one-half of the gain calculated for the double-ended output,or


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e

C d r

R A

2= . (Equation 9.11)

If the differential amplifier has resistors in the individual emitter legs, thedouble-ended differential gain is

E e

C d Rr

R A

+= ,

which should be expected, because we now have coupled emitter-resistor(ER) amplifiers.

The input resistance in differential mode is the equivalent resistance seenbetween the two bases. If there is no resistor in the emitter legs of thecircuits, and R EE is effectively shorted, we can see from Figure 9.2a that theinput resistance will be

r odemal differenti Rin 2)( = . (Equation 9.16)

For the coupled ER configuration (i.e., with R Es in the emitter leads), we canemploy the impedance reflection rule to express the input resistance as

))(1(2)1(22)( E eE in Rr Rr odemal differenti R ++=++= .

Common Mode Gain

The mid-frequency ac small signal model for common mode operation isgiven in Figure 9.2b and is reproduced below and to the left. A simplifiedversion of this small signal model is given below and to the right. Note thatthe common mode circuit may be split into a pair of parallel circuits, calledthe common-mode half-circuit , with i E=i EE /2 and with an emitter resistorof 2R EE (recall that 2R EE||2R EE=R EE, so we havent changed the originalcircuit of Figure 9.1).


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The input to each half circuit is of the same magnitude and phase. If thetransistors are matched, the circuit is perfectly symmetric, and we assumethat 2R EE>>r e , we may derive the single-ended common-mode gain ,using either half circuit, to be

EE

C C R

R A

2= . (Equation 9.13)

Ideally, the differential (double-ended) common-mode gain is zerosince v 1 -v 2=v ci-v ci=0 (and the circuit is perfectly symmetric). Practically,however, circuits are not perfectly symmetric and devices cannot beperfectly matched. This means that the common-mode gain will not be zerofor a differential output. The double-ended output voltage may then beexpressed in terms of the common-mode and differential-mode gains asfollows:

++=+=

2)( 2121

v v Av v Av Av Av c d ci c di d out . (Equation 9.14)

Even if some discrepancy from ideal exists in the differential amplifier circuit,the double-ended common-mode gain is much smaller than that for thesingle-ended output. Therefore, the input stage of a multistage amplifier (anop-amp for example) is usually a balanced differential pair with the outputtaken differentially (double-ended). This means that the differential amplifierstage will have a low common-mode gain, which we will see below is adesirable quality in terms of the common-mode rejection ratio (the next parttalks about the CMRR, hold on).


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to increase the CMRR is to make R EE as large as possible. The fabrication oflarge resistances on an IC is not practical, so an alternate approach involvesreplacing R EE with a transistor configured as a dc current source. The closerthe current source behaves to an ideal current source, the higher thecommon-mode rejection ratio (recall that an ideal current source has infinite

impedance).

The circuit of Figure 9.3a (reproduced to theright) is an example of a differential amplifierwith a diode-compensated fixed-biascurrent source . The diode compensationmakes the circuit operation less dependent ontemperature variations (see Section D10 for adiscussion of diode compensation in BJTcircuits). The diode D 1 and transistor Q 3 areselected so that they have nearly identicalcharacteristics over the range of operatingtemperatures. Just for fun realize that D 1 maybe another BJT that is matched to Q 3 and isdiode-connected (its collector is tied to its base).

Also, any of the current sources we discussed inthe previous section may be used to create theconstant current source used for biasing purposes.

To analyze the circuit of Figure 9.3a and determinethe CMRR, we need to calculate the equivalent

resistance of the constant current source circuit(called R TH by your author). A modified version ofFigure 9.3b is presented to the right and will beused for this analysis. N o t e t h a t I h a v e ch a n g e dt h e d e s i g n a t i o n s o f t h e n o d e s a n d v o l t a g e sa c r o s s r o a n d R E s i n c e t h e v 1 a n d v 2 i n F i g u r e9 . 3 b o f y o u r t e x t a r e n o t t h e s a m e a si n d i c a t e d i n F i g u r e 9 . 3 a . A l so , t h e i T H o f F i g u r e9 . 3 b i s t h e s a m e c u r r e n t a s i EE i n F i g u r e 9 . 3 a( i .e . , t h e c o l le c t o r c u r r e n t o f Q 3 ) . With all this in

mind, the circuit to the right is the small signalequivalent of the current source (with the base,collector and emitter of Q 3 noted by B 3 , C 3 and E 3 ,respectively) if the diode is assumed to be ideal and >>1. Since it isexpected that the equivalent resistance of this current source will be large,we must also include the output resistance, r o , in our analysis. Finally, byassuming an ideal diode, R B is our old friend R 1 ||R 2 .


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The equivalent resistance of the constant current source circuit is given by

TH

B ABTH i

v v R

+= . (Equation 9.18, Modified)

Writing a KCL equation at node C3 , we have

o

ABbTH r

v i i += , (Equation 9.20, Modified)

while a KCL equation at node E3 yields

0=++E

BB

o

ABB R

v i

r v

i . (Equation 9.21, Modified)

Expressing the voltages in terms of the currents i B and i TH, we have

)()(

BBB

oBTH AB

Rr i v r i i v

+==

. (Equation 9.22, Modified)

Im not going to go through all the algebra here, but if you substituteEquation 9.22 into 9.21, and solve for i TH, then substitute this result (alongwith Equation 9.22) into Equation 9.18, you get an expression for R TH to be

E B

oE BoBTH RRr

r RRr r Rr R /)(1

/)(1 ++ +++++= . (Equation 9.24)

To simplify this nasty looking expression, your author makes a series ofassumptions:

To maintain bias stability, we use R B=0.1 RE. >>1, so that 1>>1/ ro >> R E 0.1R E >> r e

Putting all this into Equation 9.24 yields the incredibly simple result

oTH r R 11 , (Equation 9.31)

where r o=V A /I C. Note that a l l of the above approximations must be valid forEquation 9.31 to be used. If it can be, life is good, R TH is independent of and is huge!


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Differential Amplifier with Single-Ended Input and Output

Figure 9.4 (given to the right)illustrates a differential amplifier wherethe input to Q 2 is grounded and the

output is taken as v o1 . As discussed inthe previous section, a constant currentsource is used in place of R EE. Thisconfiguration is known as a single-ended input and output amplifierwith phase reversal . To analyze thisamplifier, all we have to do is set v 2=0in the earlier equations. If we assumethat the equivalent resistance of thecurrent source is very large, thecommon-mode gain is approximatelyequal to zero. This means the single-ended differential-mode gain of theamplifier will determine the output, which will be

e

C di d out r

v Rv Av

21== . (Equation 9.33)

The negative sign indicates that there is a 180 o phase shift between theinput (v 1 ) and the output (v o1 ), as expected for a common emitter amplifier.If a phase reversal is not desired for a single-ended output that is referencedto ground, the output can be taken from Q 2 .

common mode gain

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