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onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.

Wideband LinearFour-Quadrant Multiplier

The MC1495 is designed for use where the output is a linear productof two input voltages. Maximum versatility is assured by allowing theuser to select the level shift method. Typical applications include:multiply, divide*, square root*, mean square*, phase detector,frequency doubler, balanced modulator/demodulator, and electronicgain control.• Wide Bandwidth

• Excellent Linearity:2% max Error on X Input, 4% max Error on Y Input Over

Temperature1% max Error on X Input, 2% max Error on Y Input at + 25°C

• Adjustable Scale Factor, K

• Excellent Temperature Stability

• Wide Input Voltage Range: ± 10 V

• ±15 V Operation

*When used with an operational amplifier.

MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted.)

Rating Symbol Value Unit

Applied Voltage(V2−V1, V14−V1, V1−V9, V1−V12,V1−V4, V1−V8, V12−V7, V9−V7,V8−V7, V4−V7)

∆V 30 Vdc

Differential Input Signal V12−V9V4−V8

± (6+I13 RX)± (6+I3 RY)

Vdc

Maximum Bias Current I3I13

1010

mA

Operating Temperature RangeMC1495MC1495B

TA0 to +70

− 40 to +125

°C

Storage Temperature Range Tstg − 65 to +150 °C

ON Semiconductor

Semiconductor Components Industries, LLC, 2004

June, 2004 − Rev. XXX1 Publication Order Number:

MC1495/D

LINEARFOUR-QUADRANT

MULTIPLIER

SEMICONDUCTORTECHNICAL DATA

MC1495

P SUFFIXPLASTIC PACKAGE

CASE 646

D SUFFIXPLASTIC PACKAGE

CASE 751A(SO-14)

1

14

1

14

ORDERING INFORMATION

PackageTested Operating

Temperature RangeDevice

MC1495DTA = 0° to + 70°C

MC1495P

MC1495BP

SO−14

Plastic DIP

Plastic DIPTA = − 40° to +125°C

MC1495

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ELECTRICAL CHARACTERISTICS (+V = + 32 V , −V = −15 V, TA = + 25°C, I3 = I13 = 1.0 mA, RX = RY = 15 kΩ, RL = 11 kΩ,unless otherwise noted.)

Characteristics Figure Symbol Min Typ Max Unit

Linearity (Output Error in percent of full scale)TA = + 25°C−10 < VX < +10 (VY = ±10 V)−10 < VY < +10 (VX = ±10 V)

TA = TLow to THigh−10 < VX < +10 (VY = ±10 V)−10 < VY < +10 (VX = ±10 V)

5

ERXERY

ERXERY

−−

−−

±1.0± 2.0

±1.5± 3.0

±1.0± 2.0

± 2.0± 4.0

%

Square Mode Error (Accuracy in percent of full scale afterOffset and Scale Factor adjustment)TA = + 25°CTA = TLow to THigh

5 ESQ

−−

± 0.75±1.0

−−

%

Scale Factor (Adjustable) 2RLK =

13 RX RY

− K − 0.1 −

Input Resistance (f = 20 Hz) 7 RinXRinY

−−

3020

−−

MΩ

Differential Output Resistance (f = 20 Hz) 8 RO − 300 − kΩ

Input Bias Current

2(I9 + I12)

2Ibx = , Iby =

(I4 + I8) TA = + 25°CTA = TLow to THigh

6Ibx, Iby −

−2.02.0

8.012

µA

Input Offset Current|I9 − I12| TA = + 25°C|I4 − I8| TA = TLow to THigh

6|Iiox|, |Iioy| −

−0.40.4

1.02.0

µA

Average Temperature Coefficient of Input Offset CurrentTA = TLow to THigh

6 |TClio|− 2.5 −

nA/°C

Output Offset Current TA = + 25°C|I14 − I2| TA = TLow to THigh

6 |IOO|−

1020

50100

µA

Average Temperature Coefficient of Output Offset CurrentTA = TLow to THigh

6 |TCIOO|− 20 −

nA/°C

Frequency Response3.0 dB Bandwidth, RL = 11 kΩ3.0 dB Bandwidth, RL = 50 Ω (Transconductance Bandwidth)3° Relative Phase Shift Between VX and VY1% Absolute Error Due to Input-Output Phase Shift

9,10BW(3dB)TBW(3dB)

fφfθ

−−−−

3.08075030

−−−−

MHzMHzkHzkHz

Common Mode Input Swing(Either Input)

11 CMV±10.5 ±12 −

Vdc

Common Mode Gain TA = + 25°C(Either Input) TA = TLow to THigh

11 ACM − 50− 40

− 60− 50

−−

dB

Common Mode QuiescentOutput Voltage

12 VO1VO2

−−

2121

−−

Vdc

Differential Output Voltage Swing Capability 9 VO − ±14 − Vpk

Power Supply Sensitivity 12 S+

S−−−

5.010

−−

mV/V

Power Supply Current 12 I7 − 6.0 7.0 mA

DC Power Dissipation 12 PD − 135 170 mW

NOTES: 1. THigh = +70°C for MC1495 TLow = 0°C for MC1495= +125°C for MC1495B = − 40°C for MC1495B

MC1495

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k =110

−10 −8.0 −6.0 −4.0 −2.0 0 2.0 4.0 6.0 8.0 10

VX, INPUT VOLTAGE (V)

−10

−8.0

−4.0

−2.0

0

2.0

−6.0

4.0

6.0

8.0

10, O

UTP

UT

VO

LTA

GE

(V)

OV+

X

Y KXY

20

10

0

−10

−20

−301.0 10 100 1000

VY VX

f, FREQUENCY (MHz)

, GA

IN (d

B)

VA

Figure 1. Multiplier Transfer Characteristic Figure 2. Transconductance Bandwidth

Figure 3. Circuit Schematic

Figure 4. Linearity (Using Null Technique)

+

−

0.1 µF

VE

V′Y

V′X

10 k

10 k

10 k VX

VY

3.0 k40 k

10 k

2

3

1

2

14

12 3 13

13 k 12 k

5.0 k

10 V9

8

5 6 10 11

MC1495

Offset AdjustSee Figure 13

ScaleFactorAdjust

7

−

+

+

+

33 k

OutputOffsetAdjust

7

8

5

1

4

6 2

3

7

8

6

4

15

Es

MC1741C

NOTE: Adjust “Scale Factor Adjust” for a null in VE.This schematic for illustrative purposes only, not specified for test conditions.

10 k

3.0 k

3.0 k

0.1 µF

10 k

10 k

10 k

4

RY = 27 k RX = 7.5 k

MC1741C

V−

−15 V

V+

+15 V

1

8

4

563

V− 7

500 500 500 500 500 500

214

9

12

111013

4.0 k

Q4

Q8Q7Q6Q5

+

−

+

−

X InputQ3Q2Q1

4.0 k

Y Input

+

−

4.0 k

Output (KXY)

4.0 k

This device contains 16 active transistors.

MC1495

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RL1 = 11 k

Figure 5. Linearity (Using X-Y Plotter Technique)

RY = 15 k RX = 15 k

To Pin4 or 9

VY

VZ

Y

X

Offset Adjust(See Figures 13 and 14)

5 6 10 111

2

14RL1 = 11 k

PlotterY-Input

X−YPlotter

I13I3

R3

+ −

32 V

R19.1 k

R13 = 13.7 k

−15 V

4

9

8

12

3

12 k

5.0 kScale

FactorAdjust

MC1495

0.1 µF

0.1 µF

PlotterX-InputVO

7 13

Figure 6. Input and Output Current Figure 7. Input Resistance

Figure 8. Output Resistance Figure 9. Bandwidth (RL = 11 kΩ)

RY = 15 k RX = 15 k

4

9

8

12

I4

I9

I8

I12 3 7 13

12 k

5 6 10 11

1

2

14I14

I2

5.6 k

9.1 k

+32 V

0.1 µFI13 = 1.0 mA

5.0 k

−15 V

12 k

5.0 k

I3 = 1.0 mA

ScaleFactorAdjust

5 6 10 11

4

9

8

12

3 7 13

1.0 M

1.0 Me1

e1

1.0 M

1.0 M

e2

e2

−15 V

+

−

9.1 k

11k

11 k

13.75 k

e1 = 1.0 Vrms20 Hz

RinX = RinY = Re1

e2−2

1

2

14

MC1495

4

9

8

12

3 7 13

13.7 k

5 6 10 11

1

2

14

RL = 11 k

9.1 k 5 6 10 114

9

8

12

3 7

13

9.1 k

11k

11k

1

2

14

0.1 µF

RY = 15 k RX = 15 k +32 V

0.1 µF

0.1 µF

12 k

5.0 k

+32 V

0.1 µF

11k

e11.0 Vrms

20 Hz

0.1 µF

12 k

5.0 kScaleFactorAdjust

+32 V

0.1 µF

eo

0.1 µF

12 k

5.0 kScaleFactorAdjust

50

+

−1.0 V

ein

ein = 1.0 Vrms

R1313.7 k

CL < 3.0 pF

RY = 15 k RX = 15 k RY = 15 k RX = 15 k

−15V −15 V

e2

RO = RL −2e1

e2

MC1495

MC1495

MC1495

MC1495

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or 20 logCMVX

VO

Figure 10. Bandwidth (RL = 50 Ω) Figure 11. Common Mode Gain andCommon Mode Input Swing

ACM = 20 logCMVY

VO

5 6 10 11

4

9

8

12

3 7

13

1.0 k

50

1

2

14

5 6 10 11

4

9

12

3

7 13

9.1 k

11k

11k

1

2

14

8

ein = 1.0 Vrms

50

ein

+

−1.0 V

15 kRY = 510 RX = 510 +15 V

50

R1313.7k

0.1 µF

eo

CL < 3.0 pF0.1µF

12 k

5.0 kScaleFactorAdjust

K = 40

+32 V

0.1 µFVO

15 k

1.0 mA

−15V −15 V

12 k

5.0 k0.1 µF

5.0 k

12 k

50

50

+

−

+

−

CMVX(f = 20 Hz)

CMVY(f = 20 Hz)

+

1.0 mA

MC1495 MC1495

Figure 12. Power Supply Sensitivity Figure 13. Offset Adjust Circuit

5 6 10 114

9

8

12

3 7 13

−15 V(V−)

0.1 µF

9.1 k

11k

13.7 k

15 k 15 k+32 V (V+)

1

2

14

VO2 VO1

2.0 k

4.3 k

22 k2N2905A

or Equivalent

+32 V

6.2 V

S+ =|∆ (VO1 − VO2)|

∆V+

S− =|∆ (VO1 − VO2)|

∆V−

V+

R

2.0 k

Pot #1 Pot #2

V+ 15 V 32 V

R 2.0 k 5.1 k

Figure 14. Offset Adjust Circuit (Alternate)

5.1 V

5.1 V

V+

R

10 k

Pot #1To Pin 8Y Offset

Adjust

Pot #2 To Pin 12X Offset Adjust

−15 V

V+ 15 V 32 V

R 10 k 22 k

2.0 kMC1495

11k

0.1 µF

−15 V

2.0 k

10 k 10 k

To Pin 8Y Offset

Adjust

To Pin 12X Offset Adjust

−15 V

10 k 10 k

MC1495

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2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0−55 −25 0 25 50 75 100 125

Figure 15. Linearity versus Temperature Figure 16. Scale Factor versus Temperature

Figure 17. Error Contributed by InputDifferential Amplifier

Figure 18. Error Contributed byInput Differential Amplifier

TA , AMBIENT TEMPERATURE (°C)

E

, E

LIN

EA

RIT

Y (%

)R

XR

Y

K Adjusted to 0.100 at 25°C

0.110

0.105

0.100

0.095

−55 −25 0 25 50 75 100 125

K, S

CA

LE F

AC

TOR

1.0

0.8

0.6

0.4

0.2

010 12 14 16 18 20

RX or RY (kΩ)

ER

RO

R, P

ER

CE

NT

OF

FULL

SC

ALE

(%) 1.0

0.8

0.6

0.4

0.2

04.0 6.0 8.0 10 12 14

RX or RY (k Ω)

ER

RO

R, P

ER

CE

NT

OF

FULL

SC

ALE

(%)

14

12

10

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16 18

|V1| or |V7| (V)

|V |

or |

V

|, M

AX

IMU

M (V

)

XY

pk

ERY

ERX

Minimum

Recommended

TA , AMBIENT TEMPERATURE (°C)

Figure 19. Maximum Allowable Input Voltage versus Voltage at Pin 1 or Pin 7

VX = VY = ± 5.0 V MaxI3 = I13 = 1.0 mAdc

VX = VY = ± 10 V Max

I3 = I13 = 1.0 mAdc

MC1495

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OPERATION AND APPLICATIONS INFORMATION

Theory of OperationThe MC1495 is a monolithic, four-quadrant multiplier

which operates on the principle of variabletransconductance. A detailed theory of operation is coveredin Application Note AN489, Analysis and Basic Operationof the MC1595. The result of this analysis is that thedifferential output current of the multiplier is given by:

2VXVYRXRYI3

IA − IB = ∆I =

where, IA and IB are the currents into Pins 14 and 2,respectively, and VX and VY are the X and Y input voltagesat the multiplier input terminals.

DESIGN CONSIDERATIONS

GeneralThe MC1495 permits the designer to tailor the multiplier

to a specific application by proper selection of externalcomponents. External components may be selected tooptimize a given parameter (e.g. bandwidth) which may inturn restrict another parameter (e.g. maximum outputvoltage swing). Each important parameter is discussed indetail in the following paragraphs.

Linearity, Output Error, E RX or ERYLinearity error is defined as the maximum deviation of

output voltage from a straight line transfer function. It isexpressed as error in percent of full scale (see figure below).

VO

+10 V

VE(max)

+10V

Vx or Vy

For example, if the maximum deviation, VE(max), is±100 mV and the full scale output is 10 V, then thepercentage error is:

VE(max)VO(max)

ER = x 100 = 100 x 10−3

10x 100 = ±1.0%.

Linearity error may be measured by either of thefollowing methods:

1. Using an X-Y plotter with the circuit shown inFigure 5, obtain plots for X and Y similar to the oneshown above.

2. Use the circuit of Figure 4. This method nulls the levelshifted output of the multiplier with the originalinput. The peak output of the null operational amplifierwill be equal to the error voltage, VE (max).

One source of linearity error can arise from large signalnonlinearity in the X and Y input differential amplifiers. Toavoid introducing error from this source, the emitterdegeneration resistors RX and RY must be chosen largeenough so that nonlinear base-emitter voltage variation can

be ignored. Figures 17 and 18 show the error expected fromthis source as a function of the values of RX and RY with anoperating current of 1.0 mA in each side of the differentialamplifiers (i.e., I3 = I13 = 1.0 mA).

3 dB Bandwidth and Phase ShiftBandwidth is primarily determined by the load resistors

and the stray multiplier output capacitance and/or theoperational amplifier used to level shift the output. Ifwideband operation is desired, low value load resistorsand/or a wideband operational amplifier should be used.Stray output capacitance will depend to a large extent oncircuit layout.

Phase shift in the multiplier circuit results from twosources: phase shift common to both X and Y channels (dueto the load resistor-output capacitance pole mentionedabove) and relative phase shift between X and Y channels(due to differences in transadmittance in the X and Ychannels). If the input to output phase shift is only 0.6°, theoutput product of two sine waves will exhibit a vector errorof 1%. A 3° relative phase shift between VX and VY resultsin a vector error of 5%.

Maximum Input VoltageVX(max), VY(max) input voltages must be such that:

VX(max) <I13 RYVY(max) <I3 RY

Exceeding this value will drive one side of the inputamplifier to “cutoff” and cause nonlinear operation.

Current I3 and I13 are chosen at a convenient value(observing power dissipation limitation) between 0.5 mAand 2.0 mA, approximately 1.0 mA. Then RX and RY can bedetermined by considering the input signal handlingrequirements.

2VX VY

RX RY I3

1.0 mA10 VRX = RY > = 10 kΩ.

The equation IA − IB =

For VX(max) = VY(max) = 10 V;

is derived from IA − IB =2VX VY

(RX + 2kTqI13

) (RY + 2kTqI3

) I3

with the assumption RX >> 2kTqI13

and RY >> 2kTqI3

.

At TA = +25°C and I13 = I3 = 1.0 mA,

2kTqI13

2kTqI3

= = 52 Ω.

Therefore, with RX = RY = 10 kΩ the above assumptionis valid. Reference to Figure 19 will indicate limitations ofVX(max) or VY(max) due to V1 and V7. Exceeding these limitswill cause saturation or “cutoff” of the input transistors. SeeStep 4 of General Design Procedure for further details.

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Maximum Output Voltage SwingThe maximum output voltage swing is dependent upon

the factors mentioned below and upon the particular circuitbeing considered.

For Figure 20 the maximum output swing is dependentupon V+ for positive swing and upon the voltage at Pin 1 fornegative swing. The potential at Pin 1 determines thequiescent level for transistors Q5, Q6, Q7 and Q8. Thispotential should be related so that negative swing at Pins 2or 14 does not saturate those transistors. See General DesignProcedure for further information regarding selection ofthese potentials.

RX RY I3

5 610

RX RY

11

RI RL

RL2

1

14 VO

9

12

4

8

3

I3

13 7

R13R3

V−

V+

VX

VY

VO = K VX VY

K =2RL

MC1495

+

+

+

−−

−

Figure 20. Basic Multiplier

If an operational amplifier is used for level shift, as shownin Figure 21, the output swing (of the multiplier) is greatlyreduced. See Section 3 for further details.

GENERAL DESIGN PROCEDURE

Selection of component values is best demonstrated by thefollowing example. Assume resistive dividers are used at theX and Y-inputs to limit the maximum multiplier input to ±5.0 V [VX = VY(max)] for a ± 10 V input [VX′ = VY′(max)](see Figure 21). If an overall scale factor of 1/10 is desired,

VO =VX′ VY′

10=

(2VX) (2VY)10

= 4/10 VX VYthen,

Therefore, K = 4/10 for the multiplier (excluding the dividernetwork).

Step 1. The fist step is to select current I3 and current I13.There are no restrictions on the selection of either of thesecurrents except the power dissipation of the device. I3 andI13 will normally be 1.0 mA or 2.0 mA. Further, I3 does nothave to be equal to I13, and there is normally no need to makethem different. For this example, let

I3 = I13 = 1.0 mA.

5

RX10 k

RY10 k

1110

RL

18 k

5.0 k

P4

OutputOffsetAdjust

10 k

R1312 k

I3

4

9

13 8 12

14

2+

−+

+10 k

VY′VY

VX

MC1495 MC1741C

P1

P2

10 k

2.0 k−15 V+15 V

5.1 V

2

37

4

6

5

1

+

−

20 k

RL

0.1 µF+15 V

R03.0 k

R03.0 k

R13.0 k

17

− 15 V − 15 V

3I13

10 k

10 k

10 k

6

0.1 µF

2.0 k

Y OffsetAdjust

ScaleFactorAdjust

R3

−10V ≤ VX ≤ +10V−10V ≤ VY ≤ +10V

12 k

5.0 k

P3X OffsetAdjust

VO =−VX VY

10

VX′

Figure 21. Multiplier with Operational Amplifier Level Shift

5.1 V

MC1495

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To set currents I3 and I13 to the desired value, it is onlynecessary to connect a resistor between Pin 13 and ground,and between Pin 3 and ground. From the schematic shownin Figure 3, it can be seen that the resistor values necessaryare given by:

R3 + 500 Ω =I3

|V−| −0.7 V

R13 + 500 Ω =I13

|V−| −0.7 V

Let V− = −15 V, then R13 + 500 = 14.3 V1.0 mA

or R13 = 13.8 kΩ

Let R13 = 12 kΩ. Similarly, R3 = 13.8 kΩ, let R3 = 15 kΩHowever, for applications which require an accurate scale

factor, the adjustment of R3 and consequently, I3, offers aconvenient method of making a final trim of the scale factor.For this reason, as shown in Figure 21, resistor R3 is shownas a fixed resistor in series with a potentiometer.

For applications not requiring an exact scale factor(balanced modulator, frequency doubler, AGC amplifier,etc.) Pins 3 and 13 can be connected together and a singleresistor from Pin 3 to ground can be used. In this case, thesingle resistor would have a value of 1/2 the abovecalculated value for R13.

Step 2. The next step is to select RX and RY. To insure thatthe input transistors will always be active, the followingconditions should be met:

VX

RX< I13,

VY

RY< I3

A good rule of thumb is to make I3RY ≥ 1.5 VY(max) andI13 RX ≥ 1.5 VX(max). The larger the I3RY and I13RX productin relation to VY and VX respectively, the more accurate themultiplier will be (see Figures 17 and 18).

Let RX = RY = 10 kΩ,then I3RY = 10 V

I13RX = 10 V

since VX(max) = VY(max) = 5.0 V, the value ofRX= RY = 10 kΩ is sufficient.

Step 3. Now that RX, RY and I3 have been chosen, RL canbe determined:

K =2RL

RX RY I3= 4

10= 4

10, or

(10 k) (10 k) (1.0 mA)(2) (RL)

Thus RL = 20 kΩ.

Step 4. To determine what power supply voltage isnecessary for this application, attention must be given to thecircuit schematic shown in Figure 3. From the circuitschematic it can be seen that in order to maintain transistorsQ1, Q2, Q3 and Q4 in an active region when the maximuminput voltages are applied (VX′ = VY′ = 10 V or VX = 5.0 V,VY = 5.0 V), their respective collector voltage should be atleast a few tenths of a volt higher than the maximum inputvoltage. It should also be noticed that the collector voltageof transistors Q3 and Q4 is at a potential which is two

diode-drops below the voltage at Pin 1. Thus, the voltage atPin 1 should be about 2.0 V higher than the maximum inputvoltage. Therefore, to handle +5.0 V at the inputs, thevoltage at Pin 1 must be at least +7.0 V. Let V1 = 9.0 Vdc.

Since the current flowing into Pin 1 is always equal to 2I3,the voltage at Pin 1 can be set by placing a resistor (R1) fromPin 1 to the positive supply:

R1 =V+ −V1

2I3

15 V −9.0 VLet V+ = 15 V, then R1 =(2) (1.0 mA)

R1 = 3.0 kΩ.

Note that the voltage at the base of transistors Q5, Q6, Q7 andQ8 is one diode-drop below the voltage at Pin 1. Thus, inorder that these transistors stay active, the voltage at Pins 2and 14 should be approximately halfway between thevoltage at Pin 1 and the positive supply voltage. For thisexample, the voltage at Pins 2 and 14 should beapproximately 11 V.

Step 5. For dc applications, such as the multiply, divideand square-root functions, it is usually desirable to convertthe differential output to a single-ended output voltagereferenced to ground. The circuit shown in Figure 22performs this function. It can be shown that the outputvoltage of this circuit is given by:

VO = (I2 −I14) RL

And since IA −IB = I2 −I14 =2IX IY

I3=

2VXVYI3RXRY

then VO =2RL VX′ VY′4RX RX I3

where, VX′ VY′ is the voltage at

the input to the voltage dividers.

Figure 22. Level Shift Circuit

I2

I14

V2

V14

RO RO

+

−

RLRL

V+

VO

The choice of an operational amplifier for this applicationshould have low bias currents, low offset current, and a highcommon mode input voltage range as well as a high commonmode rejection ratio. The MC1456, and MC1741Coperational amplifiers meet these requirements.

MC1495

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Referring to Figure 21, the level shift components will bedetermined. When VX = VY = 0, the currents I2 and I14 willbe equal to I13. In Step 3, RL was found to be 20 kΩ and inStep 4, V2 and V14 were found to be approximately 11 V.From this information RO can be found easily from thefollowing equation (neglecting the operational amplifiersbias current):

V2RL

+ I13 = V+ −V2RO

And for this example, 11 V20 kΩ+ 1.0 mA = 15 V −11 V

RO

Solving for RO: RO = 2.6 kΩ, thus, select RO = 3.0 kΩ

For RO = 3.0 kΩ, the voltage at Pins 2 and 14 is calculatedto be:

V2 = V14 = 10.4 V.

The linearity of this circuit (Figure 21) is likely to be asgood or better than the circuit of Figure 5. Furtherimprovements are possible as shown in Figure 23 where RYhas been increased substantially to improve the Y linearity,and RX decreased somewhat so as not to materially affect theX linearity. This avoids increasing RL significantly in orderto maintain a K of 0.1.

The versatility of the MC1495 allows the user to tooptimize its performance for various input and output signallevels.

OFFSET AND SCALE FACTOR ADJUSTMENT

Offset VoltagesWithin the monolithic multiplier (Figure 3) transistor

base- emitter junctions are typically matched within 1.0 mVand resistors are typically matched within 2%. Even withthis careful matching, an output error can occur. This outputerror is comprised of X-input offset voltage, Y-input offsetvoltage, and output offset voltage. These errors can beadjusted to zero with the techniques shown in Figure 21.Offset terms can be shown analytically by the transferfunction:

VO = K[Vx ± Viox ± Vx(off)] [Vy ± Vioy ± Vy(off)] ± VOO (1)

Where: K = scale factorVx = ‘‘x’’ input voltageVy = ‘‘y’’ input voltage

Viox = ‘‘x’’ input offset voltageVioy = ‘‘y’’ input offset voltage

Vx(off) = ‘‘x’’ input offset adjust voltageVy(off) = ‘‘y’’ input offset adjust voltageVOO = output offset voltage.

Figure 23. Multiplier with Improved Linearity

5

7.5 k 27 k

1110

33 k

10 k OutputOffsetAdjust

20 k

12 k

4

9

13 8 12

2

14−

++

+10 k

VY′

VX′

MC1495 MC1741C

20 k

15 k−15 V+15 V

2.0 k

2

3

7

4

6

5

1

+

−

40 k

+15 V

3.0 k3.0 k3.0 k

17

− 15 V − 15 V

3

10 k

10 k

10 k

6

15 k

Y OffsetAdjust

ScaleFactorAdjust

±10 V VO =−VX VY

10

X OffsetAdjust

2.0 k

13 k

5.0 k

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X, Y and Output Offset Voltages

VOOutputOffset

Vx

X Offset Y Offset

Vy

OutputOffset

VO

For most dc applications, all three offset adjustpotentiometers (P1, P2, P4) will be necessary. One or moreoffset adjust potentiometers can be eliminated for acapplications (see Figures 28, 29, 30, 31).

If well regulated supply voltages are available, the offsetadjust circuit of Figure 13 is recommended. Otherwise, thecircuit of Figure 14 will greatly reduce the sensitivity topower supply changes.

Scale FactorThe scale factor K is set by P3 (Figure 21). P3 varies I3

which inversely controls the scale factor K. It should benoted that current I3 is one-half the current through R1. R1sets the bias level for Q5, Q6, Q7, and Q8 (see Figure 3).Therefore, to be sure that these devices remain active underall conditions of input and output swing, care should beexercised in adjusting P3 over wide voltage ranges (seeGeneral Design Procedure).

Adjustment ProceduresThe following adjustment procedure should be used to

null the offsets and set the scale factor for the multiply modeof operation, (see Figure 21).

1. X-Input Offset(a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)

to the Y-input (Pin 4).(b) Connect X-input (Pin 9) to ground.(c) Adjust X offset potentiometer (P2) for an ac

null at the output.2. Y-Input Offset

(a) Connect oscillator (1.0 kHz, 5.0 Vpp sinewave)to the X-input (Pin 9).

(b) Connect Y-input (Pin 4) to ground.(c) Adjust Y offset potentiometer (P1) for an ac null

at the output.3. Output Offset

(a) Connect both X and Y-inputs to ground.(b) Adjust output offset potentiometer (P4) until

the output voltage (VO) is 0 Vdc.4. Scale Factor

(a) Apply +10 Vdc to both the X and Y-inputs.(b) Adjust P3 to achieve + 10 V at the output.

5. Repeat steps 1 through 4 as necessary.

The ability to accurately adjust the MC1495 depends uponthe characteristics of potentiometers P1 through P4.Multi-turn, infinite resolution potentiometers with lowtemperature coefficients are recommended.

DC APPLICATIONS

MultiplyThe circuit shown in Figure 21 may be used to multiply

signals from dc to 100 kHz. Input levels to the actualmultiplier are 5.0 V (max). With resistive voltage dividersthe maximum could be very large however, for thisapplication two-to-one dividers have been used so that themaximum input level is 10 V. The maximum output levelhas also been designed for 10 V (max).

Squaring CircuitIf the two inputs are tied together, the resultant function is

squaring; that is VO = KV2 where K is the scale factor. Notethat all error terms can be eliminated with only threeadjustment potentiometers, thus eliminating one of the inputoffset adjustments. Procedures for nulling with adjustmentsare given as follows:

A. AC Procedure:1. Connect oscillator (1.0 kHz, 15 Vpp) to input.2. Monitor output at 2.0 kHz with tuned voltmeter

and adjust P3 for desired gain. (Be sure to peakresponse of the voltmeter.)

3. Tune voltmeter to 1.0 kHz and adjust P1 for aminimum output voltage.

4. Ground input and adjust P4 (output offset) for0 Vdc output.

5. Repeat steps 1 through 4 as necessary.

B. DC Procedure:1. Set VX = VY = 0 V and adjust P4 (output offset

potentiometer) such that VO = 0 Vdc2. Set VX = VY = 1.0 V and adjust P1 (Y-input offset

potentiometer) such that the output voltage is+ 0.100 V.

3. Set VX = VY = 10 Vdc and adjust P3 such thatthe output voltage is + 10 V.

4. Set VX = VY = −10 Vdc. Repeat steps 1 through3 as necessary.

Figure 24. Basic Divide Circuit

XKVX VY

VX

R1

VY

−

+

R2

I2

I1

VZ

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Divide CircuitConsider the circuit shown in Figure 24 in which the

multiplier is placed in the feedback path of an operationalamplifier. For this configuration, the operational amplifierwill maintain a “virtual ground” at the inverting (−) input.Assuming that the bias current of the operational amplifieris negligible, then I1 = I2 and,

(1) =KVXVY

R1

−VZ

R2

(2)Solving for VY, VY =−R1

R2 K

VZ

VX

−VZ

KVX(3)If R1=R2, VY =

−VZ

VX(4)If R1= KR2, VY =

Hence, the output voltage is the ratio of VZ to VX andprovides a divide function. This analysis is, of course, theideal condition. If the multiplier error is taken into account,the output voltage is found to be:

VY = −R1

R2 KVZ

VX+

∆E

KVX (5)

where ∆E is the error voltage at the output of the multiplier.From this equation, it is seen that divide accuracy is stronglydependent upon the accuracy at which the multiplier can beset, particularly at small values of VY. For example, assumethat R1 = R2, and K = 1/10. For these conditions the outputof the divide circuit is given by:

VY =−10 VZ

VX+

∆EVX

(6)10

From Equation 6, it is seen that only when VX = 10 V isthe error voltage of the divide circuit as low as the error ofthe multiply circuit. For example, when VX is small, (0.1 V)the error voltage of the divide circuit can be expected to bea hundred times the error of the basic multiplier circuit.

In terms of percentage error,

percentage error = erroractual

x 100%

or from Equation (5),

PED =KVX

∆E

R1R2 K

VZ

VX

=R2R1

∆EVZ (7)

From Equation 7, the percentage error is inversely relatedto voltage VZ (i.e., for increasing values of VZ, thepercentage error decreases).

A circuit that performs the divide function is shown inFigure 25.

Two things should be emphasized concerning Figure 25.1. The input voltage (VX′) must be greater than zero and

must be positive. This insures that the current out ofPin 2 of the multiplier will always be in a directioncompatible with the polarity of VZ.

2. Pin 2 and 14 of the multiplier have been interchangedin respect to the operational amplifiers inputterminals. In this instance, Figure 25 differs from thecircuit connection shown in Figure 21; necessitated toinsure negative feedback around the loop.

A suggested adjustment procedure for the divide circuit.1. Set VZ = 0 V and adjust the output offset

potentiometer (P4) until the output voltage (VO)remains at some (not necessarily zero) constant valueas VX′ is varied between +1.0 V and +10 V.

2. Keep VZ at 0 V, set VX′ at +10 V and adjust the Y inputoffset potentiometer (P1) until VO = 0 V.

3. Let VX′ = VZ and adjust the X-input offsetpotentiometer (P2) until the output voltage remains atsome (not necessarily − 10 V) constant value as VZ =VX′ is varied between +1.0 and +10 V.

4. Keep VX′ = VZ and adjust the scale factorpotentiometer (P3) until the average value of VO is−10 V as VZ = VX′ is varied between +1.0 V and+10 V.

5. Repeat steps 1 through 4 as necessary to achieveoptimum performance.

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P3

Figure 25. Divide Circuit

5

RX10 k

RY10 k

1110

18 k

5.0 kP4

OutputOffsetAdjust

12 k

4

9

13 8 12

2

14−

++

+

10 k

VX′

MC1495 MC1741C

2

3

7

46

5

1

+

−

20 k

0.1 µF+15 V

3.0 k3.0 k3.9 k

17

− 15 V − 15 V

3

10 k

10 k

10 k

6

0.1 µF

ScaleFactorAdjust

0 ≤ VX′ ≤ +10 V−10 V ≤ VZ ≤ +10 V

To OffsetAdjust

(See Figure 13)

13 k

VO

−10 VZ

VXVO =

5.0 k

VZ

Figure 26. Basic Square Root Circuit

−

+

VO

KVO2 +

++

−

KVO2 = −VZ

or

VO =|VZ|

K

VZ

MC1495

Square RootA special case of the divide circuit in which the two inputs

to the multiplier are connected together is the square rootfunction as indicated in Figure 26. This circuit may sufferfrom latch-up problems similar to those of the divide circuit.Note that only one polarity of input is allowed and diodeclamping (see Figure 27) protects against accidentallatch-up.

This circuit also may be adjusted in the closed-loop modeas follows:

1. Set VZ to −0.01 V and adjust P4 (output offset) forVO = +0.316 V, being careful to approach the outputfrom the positive side to preclude the effect of theoutput diode clamping.

2. Set VZ to −0.9 V and adjust P2 (X adjust) forVO = +3.0 V.

3. Set VZ to −10 V and adjust P3 (scale factor adjust)for VO = +10 V.

4. Steps 1 through 3 may be repeated as necessary toachieve desired accuracy.

AC APPLICATIONSThe applications that follow demonstrate the versatility of

the monolithic multiplier. If a potted multiplier is used forthese cases, the results generally would not be as goodbecause the potted units have circuits that, although theyoptimize dc multiplication operation, can hinder acapplications.

Frequency doubling often is done with a diode wherethe fundamental plus a series of harmonics aregenerated. However, extensive filtering is required to obtainthe desired harmonic, and the second harmonic obtainedunder this technique usually is small in magnitude andrequires amplification.

When a multiplier is used to double frequency the secondharmonic is obtained directly, except for a dc term, whichcan be removed with ac coupling.

eo = KE2 cos2 ωt

eo = KE2

2(1 + cos 2ωt).

A potted multiplier can be used to obtain the doublefrequency component, but frequency would be limited by itsinternal level-shift amplifier. In the monolithic units, theamplifier is omitted.

In a typical doubler circuit, conventional ± 15 V suppliesare used. An input dynamic range of 5.0 V peak-to-peak isallowed. The circuit generates wave-forms that are doublefrequency; less than 1% distortion is encountered withoutfiltering. The configuration has been successfully used inexcess of 200 kHz; reducing the scale factor by decreasingthe load resistors can further expand the bandwidth.

Figure 29 represents an application for the monolithicmultiplier as a balanced modulator. Here, the audio inputsignal is 1.6 kHz and the carrier is 40 kHz.

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P3

Figure 27. Square Root Circuit

5

RX10 k

RY10 k

1110

13 k

5.0 kP4

OutputOffsetAdjust

12 k

4

9

13 8 12

14

2−

++

+

10 k

MC1495 MC1741C

2

3

7

46

5

1

+

−

20 kRL

0.1 µF+15 V

3.0 k3.0 k3.9 k

17

− 15 V − 15V

310 k

6

0.1 µF

ScaleFactorAdjust

−10 ≤ VZ ≤ +0 VTo Offset

Adjust(See Figure 13)

13 k

VO

10 |VZ|√VO =

(11 V)

5.0 k

VZ

eo ≈ E2

20cos 2 ωt

When two equal cosine waves are applied to X and Y, the resultis a wave shape of twice the input frequency. For this examplethe input was a 10 kHz signal, output was 20 kHz.

Figure 28. Frequency Doubler

5 6 10

RY8.2 k

RX8.2 k

4

9

8

12

3 713

1

2

14

E cos ωt(< 5.0 Vpp)

6.8 k

R13.0 k

R13.3 k

*Select

OffsetAdjust

MC1495

C1*

1.0 µF

1.0 µF

VCC +15 V

R13.3 k

−15 V

+−

Y

11

5 6 10

RY8.2 k

RX8.2 k

4

9

8

12

Figure 29. Balanced Modulator

3 713

1

2

14

eY = E cos ωmt

6.8 k

3.0 k

RL3.3 k

*Select

(A)

+

−

Y

X

OffsetAdjust

C1*

eX = E cos ωct

1.0 µF

1.0 µF

+15 V

(B)

eo

RL3.3 k

−15 V

+−

11

MC1495

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The defining equation for balanced modulation is

K(Emcos ωmt) (Ec cos ωct) =

KEc Em

2[ cos (ωc + ωm)t + cos (ωc − ωm) t ]

where ωc is the carrier frequency, ωm is the modulatorfrequency and K is the multiplier gain constant.

AC coupling at the output eliminates the need for leveltranslation or an operational amplifier; a higher operatingfrequency results.

A problem common to communications is to extract theintelligence from single-sideband received signal. The ssbsignal is of the form:

essb = A cos (ωc + ωm) t

and if multiplied by the appropriate carrier waveform, cosωct,

essbecarrier =AK2

[cos (2ωc + ωm)t + cos (ωc) t ].

If the frequency of the band-limited carrier signal (ωc) isascertained in advance, the designer can insert a low passfilter and obtain the (AK/2) (cosωct) term with ease. He/shealso can use an operational amplifier for a combination levelshift-active filter, as an external component. But in pottedmultipliers, even if the frequency range can be covered, theoperational amplifier is inside and not accessible, so the usermust accept the level shifting provided, and still add a lowpass filter.

Amplitude ModulationThe multiplier performs amplitude modulation, similar to

balanced modulation, when a dc term is added to the

modulating signal with the Y-offset adjust potentiometer(see Figure 30).

Here, the identity is:

Em(1 + m cos ωmt) Ec cos ωct = KEmEccos ωct +

KEmEcm

2[ cos(ωc + ωm)t + cos (ωc − ωm) t ]

where m indicates the degrees of modulation. Since m isadjustable, via potentiometer P1, 100% modulation ispossible. Without extensive tweaking, 96% modulation maybe obtained where ωc and ωm are the same as in the balancedmodulator example.

Linear Gain ControlTo obtain linear gain control, the designer can feed to one

of the two MC1495 inputs a signal that will vary the unit’sgain. The following example demonstrates the feasibility ofthis application. Suppose a 200 kHz sinewave, 1.0 Vpeak-to-peak, is the signal to which a gain control will beadded. The dynamic range of the control voltage VC is 0 Vto +1.0 V. These must be ascertained and the proper valuesof RX and RY can be selected for optimum performance. Forthe 200 kHz operating frequency, load resistors of 100 Ωwere chosen to broaden the operating bandwidth of themultiplier, but gain was sacrificed. It may be made up withan amplifier operating at the appropriate frequency (seeFigure 31).

Figure 30. Amplitude Modulation

5 6 10

RY8.2 k

RX8.2 k

4

9

8

12

3 713

1

2

14

6.8 k

R13.0 k

RL13.3 k

*Select

Y

XOffset Adjust

MC1495

C1*

1.0 µF

VCC = +15 V

eo

RL13.3 k

−15 V

% Modulation Adjust

eY = E cos ωmt

eX = E cos ωmt

eX, eY < 5.0 Vpp

11

The signal is applied to the unit’s Y-input. Since the totalinput range is limited to 1.0 Vpp, a 2.0 V swing, a currentsource of 2.0 mA and an RY value of 1.0 kΩ is chosen. Thistakes best advantage of the dynamic range and insures linearoperation in the Y-channel.

Since the X-input varies between 0 and +1.0 V, the currentsource selected was 1.0 mA, and the RX value chosenwas 2.0 kΩ. This also insures linear operation over theX-input dynamic range. Choosing RL = 100 assures widebandwidth operation.

MC1495

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K =RL

RX RY I3

= 100(2 k) (1 k) (2 x 103)

V−1

= 140

V−1

Hence, the scale factor for this configuration is: The 2 in the numerator of the equation is missing in this scalefactor expression because the output is single-ended and accoupled.

Figure 31. Linear Gain Control

P3

5

2.0 k 1.0 k

1110

100

11 k

13 7

−

+MC1495

1.5 k

3

6

3.0 k

5.0 k

AmplifierAV = 40

Vin

VC

OffsetAdjust

51

1.0 k

0.1 µF

4

9

8

12

Y

Y

X

X

2.0 mA

1.0 µF

−12 V

VO

+12 V

100

1

2

14

+

−

NOTE: Linear gain control of a 1.0 Vpp signal is performed with a 0 V to 1.0 V control voltage. If VC is 0.5 V the output will be 0.5 Vpp.

1.25

1.0

0.75

0.5

0.25

00

0.2 0.4 0.6 0.8 1.0 1.2

Vin = 1.0 Vpp200 kHz

VAGC (V)

VO

(Vpp

)

+

k =140

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PACKAGE DIMENSIONS

D SUFFIXPLASTIC PACKAGE

CASE 751A−03ISSUE F

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

−A−

−B−

G

P 7 PL

14 8

71M0.25 (0.010) B M

SBM0.25 (0.010) A ST

−T−

FR X 45

SEATING

PLANED 14 PL K

C

JM

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019

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PACKAGE DIMENSIONS

P SUFFIXPLASTIC PACKAGE

CASE 646−06ISSUE M

1 7

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80B 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53F 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43L

M −−− 10 −−− 10 N 0.015 0.039 0.38 1.01

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

F

H G DK

C

SEATING

PLANE

N

−T−

14 PL

M0.13 (0.005)

L

MJ

0.290 0.310 7.37 7.87

MC1495

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Notes

MC1495

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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MC1495/D

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