combinatorial logic

EE201: Digital Circuits and Systems 1 Combinatorial Logic page 1 of 29

EE201: Digital Circuits and Systems

Section 1 - Combinatorial Logic

1.1 Encoders:

Definition

An encoder produces a digital code which depends on which one of its input is activated

Only one of M inputs is activated at a time

Encoder outputs a N-bit output code

I0 EncI1

I2

O0

O1

ON-1

IM


Always: 2N MExample

4-Line to Binary Encoder:

o 4 inputso 2 outputs

The logic diagram can be generated using formal methods:

Y = D + C

Similarly:

Y

AB/CD0001111000X1X1010XXX11XXXX100XXX

Inputs OutputsA B C D Y X1 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1

A EncBC

Y

XD


X = D + B

Application

Decimal to BCD Encoder:


S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 B0 B1 B2 B3

1 0 0 0 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 0 0 0 1 10 0 0 0 1 0 0 0 0 0 0 1 0 00 0 0 0 0 1 0 0 0 0 0 1 0 10 0 0 0 0 0 1 0 0 0 0 1 1 00 0 0 0 0 0 0 1 0 0 0 1 1 10 0 0 0 0 0 0 0 1 0 1 0 0 00 0 0 0 0 0 0 0 0 1 1 0 0 1

S0

EncS1

S9

B0

B3


1.2 Decoders:

Definition

An decoder activates only one of its outputs depending on the binary code provided as input

Decoder receives a N-bit input code

Only one of M outputs is activated at a time

Always: 2N M

IN-1

O0DecO1

O2

OM-1

I0

I1


Example

Binary to 4-Line Decoder:


The logic diagram can be generated using formal methods:

_ _ _ _ A = X Y, B = X Y, C = X Y, D = X Y

A

X/Y01010100

Inputs OutputsX Y A B C D0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

ADecBC

X

YD


Implementation

Application 1

BCD to Decimal Decoder:


B0 DecB1

B2

S0

S9B3


Implementation

S0

B0B1/B2 B30001111000100001000011XXXX1000XX

Inputs OutputsB0 B1 B2 B3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9

0 0 0 0 1 0 0 0 0 0 0 0 0 00 0 0 1 0 1 0 0 0 0 0 0 0 00 0 1 0 0 0 1 0 0 0 0 0 0 00 0 1 1 0 0 0 1 0 0 0 0 0 00 1 0 0 0 0 0 0 1 0 0 0 0 00 1 0 1 0 0 0 0 0 1 0 0 0 00 1 1 0 0 0 0 0 0 0 1 0 0 00 1 1 1 0 0 0 0 0 0 0 1 0 01 0 0 0 0 0 0 0 0 0 0 0 1 01 0 0 1 0 0 0 0 0 0 0 0 0 1


Application 2

BCD to 7-segment Decoder:

a d b

c g

f

e

A

B

C

D

Decabcdefg

A B C D No. Segments0 0 0 0 0 a, b, d, e, f, g0 0 0 1 1 b, g0 0 1 0 2 a, b, c, e, f0 0 1 1 3 a, b, c, f, g0 1 0 0 4 b, c, d, g0 1 0 1 5 a, c, d, f, g0 1 1 0 6 a, c, d, e, f, g0 1 1 1 7 a, b, g1 0 0 0 8 a, b, c, d, e, f, g1 0 0 1 9 a, b, c, d, f, g1 0 1 0 X -1 0 1 1 X -1 1 0 0 X -1 1 0 1 X -1 1 1 0 X -1 1 1 1 X -


Horizontal segments: a, c, f

a => 0, 2, 3, 5, 6, 7, 8, 9c => 2, 3, 4, 5, 6, 8, 9f => 0, 2, 3, 5, 6, 8, 9

Minimisation

a

AB/CD 00 01 11 10

00 1 0 1 1

01 0 1 1 1

11 X X X X

10 1 1 X X

Equation


Minimisation

c

AB/CD 00

01

11 10

00 0 0 1 1

01 1 1 0 1

11 X X X X

10 1 1 X X

Equation

Minimisation

f


AB/CD 00

01

11 10

00 1 0 1 1

01 0 1 0 1

11 X X X X

10 1 1 X X

What’s missing?

Equation

Implementation (a segment)


Implementation (with NAND gates)


1.3 Multiplexers:

Definition

A multiplexer selects one of its inputs to direct to the output depending on the binary code provided at the select inputs

Multiplexer receives a M-bit selection code

Only one of N inputs is directed at the output

Always: 2M = N

IN-1

Mux

Z

I0

I1

S0 S1 SM


Example 1 Two-channel Multiplexer

o 2 inputso 1 select inputo 1 output

The logic diagram can be generated using formal methods and minimising, it results: _ Z = A S + B S

Implementation???

Inputs Select OutputA B S Z0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

S

MuxZ

A

B


Example 2 Two-channel two-bit Multiplexer o 4 inputso 1 select inputo 2 outputs

After minimisation, results: _ _ Z0 = A0 S + B0 S Z1 = A1 S + B1 S

Implementation

Select OutputS Z1 Z0

0 A1 A0

1 B1 B0

S

MuxA1

B0

A0

B1

Z0

Z1


Homework: implementation using gates!Example 3

Four-channel Multiplexer o 4 inputso 2 select inputo 1 output

We have: _ _ _ _ Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0

Implementation

S1 S0 Z1

0 0 I0

0 1 I1

1 0 I2

1 1 I3

ZMuxI1

I2

I0

I3

S0 S1


Homework: implementation with 2-channel MUXExample 4

Eight-channel Multiplexer o 8 inputso 3 select inputo 1 output

We have: _ _ _ _ _ Z = I0 S2 S1 S0 + I1 S2 S1 S0 + … + I7 S2 S1 S0

Homework: implementation with 2-channel MUX

Homework: implementation with logic gates

Applications

Data selection, data routing, parallel to serial conversion, waveform generation, logic function generation, etc.

S2 S1 S0 Z1

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

S1S0

ZMuxI1

I6

I0

I7

S2


Application 1

Parallel to serial conversion:

o 4 inputso 1 outputo 4-bit Registero 2-bit Countero 4-channel Muxo 1 serial line

The Register contains parallel data 2-bit Counter generates S1 and S2 At every Clock, a different input of the 4:1 line

Mux is outputted on the Serial line: X0, X1, X2, X3

Serial line

X0

X1

X2

X3

2-bit Counter

4:1 line MUX

S1 S2

Clock


Application 2

Logic function generator:

E.g. 1

o Original function:

o Full form:

o 4-channel Multiplexer:

o Matching data and select inputs:

F

C

0

_ C

1

4:1 line MUX

S1 S2

A B


Notes:

o There are other ways of implementing the same function by matching different input variables on the select inputs of the MUX

o In general the number of select lines needed is equal to the number of input variables minus 1 (there are also exceptions: see next)

Homework:

o Implement F in another way using 4-channel MUX

o Implement F using 2-channel MUX

o Implement F using logic gates

o Implement F using NAND logic gates


E. g. 2


o Partial form:

o 4-channel Multiplexer:

o Matching data and select inputs:

o Note: normal implementation would have required a 16-channel MUX

E. g. 3

F

C

_ D

0

_ E

4:1 line MUX

S1 S2

A B




o Factorised function:

0

0

0

00

1

1

0

v

v

v

v

v

v

v

v

16 Channel MUX

S1 S2 S3 S4

w x y z

F



Can you reduce it further if you had 2-ch MUX?

1.4 Demultiplexers:

Definition

A demultiplexer transfers its input to one of the outputs depending on the binary code provided at the select inputs

v010

4 Channel MUX

S1 S2

w x

4 Channel MUX

S1 S2

w x

4 Channel MUX

S1 S2

w x

00v

v

v

v

v1

4 Channel MUX

S1 S2

y z

F1

F2

F3

F

I

O0 O1

ON-1

S0 S1 SM-1

DMUX


Demultiplexer receives a M-bit selection code

The input is directed to one of the N outputs

Always: 2M = N

Example 1 Two-channel Demultiplexer

o 1 inputo 1 select input


o 2 outputs

o implementation using logic gates

S O0 O1

0 I 01 0 I

I

O0 O1

S

DMUX


Example 2 Eight-channel Demultiplexer

o 1 inputo 3 select inputso 8 output


Application 4-bit/4-word Serial Data Transmission System:

A

B

C

D

Mod-4 Counter

Mod-8 Counter

4:1 line MUX

S1 S2

Serial line

1:4 line

DMUX

S1 S2

Serial line

Mod-4 Counter

Mod-8 Counter

Clock (16 pulses)

Is Mod-8 Counter correct?


The circuit serially transmits four 4-bit words stored in registers A, B, C and D to registers W, X, Y and Z

Initially all Counters are RESET to 0

16 clock pulses are applied on the Clock line

First clock determines such a select input combination at MUX that the first bit from register A is outputted to the serial line

The same clock determines such a select input combination at DMUX that the incoming bit on the serial line will be directed and stored in register W

Next clock triggers the transmission of bit 2 from register A and its storage in bit 2 of register W, etc.

Each clock determines a SHIFT of bits in the registers

Therefore clock five determines the transmission of bit two from register B and its storage into bit two of register X, etc.

combinatorial logic

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