combinatorial logic design multiplexers and alus · combinatorial vs. sequential logic • the cpu...
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CombinatorialLogicDesignMultiplexersandALUs
CS64:ComputerOrganizationandDesignLogicLecture#14
ZiadMatni
Dept.ofComputerScience,UCSB
Administrative
• Remainingonthecalendar…Thissupersedesanythingonthesyllabus
2
DATE TOPIC ASSIGNMENTS
Thu.3/1 SimplifyingDigitalLogicFunctions Lab6(dueFri.3/2)
Tue.3/6 CombinatorialLogic
Thu.3/8 SequentialLogic Lab7(dueFri.3/9)
Tue.3/13 FiniteStateMachines
Thu.3/15 Ethics Labs8and9(dueFri.3/16)
LectureOutline
• CombinatorialLogic
• SelectionusingMultiplexers
• BasicALUDesign
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Exercise2
• Giventhefollowingtruthtable,drawtheresultinglogiccircuit
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A B C F0 0 0 10 0 1 10 1 0 10 1 1 01 0 0 11 0 1 11 1 0 01 1 1 0
00 01 11 10
0
1
ABC
111
F(A,B,C)=B’+A’.C’
1 1
B
AC
F
Exercise3
• Giventhefollowingschematicofacircuit,(a)writethefunctionand(b)filloutthetruthtable:
X=A.B+(A.C)’(notethatalsomeans:X=A.B+A’+C’)
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ABAC
X
A.B
(A.C)’
A B C X0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1
X
Exercise3
• Giventhefollowingschematicofacircuit,(a)writethefunctionand(b)filloutthetruthtable:
X=A.B+(A.C)’(notethatalsomeans:X=A.B+A’+C’)
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ABAC
X
A.B
(A.C)’
A B C X0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1
Multiplexer(Muxforshort)
• Typicallyhas3groupsofinputsand1output– IN:2data,1select– OUT:1data
• 1oftheinputdatalinesgetsselectedtobecometheoutput,basedonthe3rd(select)input– If“Sel”=0,thenI0getstobetheoutput– If“Sel”=1,thenI1getstobetheoutput
• TheoppositeofaMuxiscalledaDemulitplexer(orDemux)
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MuxConfigurations
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MuxescanhaveI/Othataremultiplebits
Ortheycanhavemorethantwodatainputs
2:1
A0A1B0B1SEL
O0O1
Thisiscalleda2-bit,2-to-1mux
6:1
ABCDEFSEL
O
Thisiscalleda1-bit,6-to-1mux
TheUseofMultiplexers
• Makesitpossibleforseveralsignals(variables)toshareoneresource– Verycommonlyusedindatacommunicationlines
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Mux De
mux
… …DataLines
DataLines
Select
Shareddataline(“trunk”)
MuxTruthTableandLogicCircuit1-bitMux
I0 I1 S O0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
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00 01 11 10
0
1
I0I1S
1
11
1
O=S.I1+S’.I0
I0I1
S
O
=linesarephysicallyconnected
00011011
Beyond1-bitMuxes• Generalmuxform:N-bit,M-to-1• Where: N=howwidethedatabusis(inbits,min.1)
M=howmanyinputstothemux(min.2)
• The“select”input(S)hastobeabletoselect 1outofMinputs– So,ifM=2,Sshouldbeatleast1bit(S=0foroneline,S=1fortheother)– ButifM=3,Sshouldbeatleast2bits(why?)– IfM=4,Sshouldbeatleast???
• Atleast2bits– IfM=5,Swillhavetobe???
• Atleast3bits
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...
S
Minputs
WhatDoesThisCircuitDo?
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101010(akasynchronousclock)
01S
a0a1a2a3a4a5
b0b1b2b3b4b5
time
time
a0 a1 a2 a3 a4 a5
1 0 1 0 1 0
b0 a1 b2 a3 b4 a5
b0 b1 b2 b3 b4 b5
b0a1b2a3b4a5
WhatDoesThisCircuitDo?
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S0
AB 0
1S
01S
RCo
RCo
S0
1bAdder
1bAdder
01
01S
S1
F
I0I1Ci
I0I1Ci
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S0
AB 0
1S
01S
RCo
I0I1Ci
RCo
S0
1bAdder
1bAdder
01
01S
S1 S0F0 0 A&&B0 1 A||B1 0 A+B1 1 A–B
S1
F
Forsimplicity,theCarryOutandOverflowbitsarenotshown
I0I1Ci
WhatDoesThisCircuitDo?
SimulationofCombinatorialLogic
• Goto:https://logic.ly/demo/
IN-CLASSDEMONSTRATION
(NeededforLab#7)3/6/18 Matni,CS64,Wi18 16
Arithmetic-LogicUnit(ALU)
• Recall:theALUdoesallthecomputationsnecessaryinaCPU
• ThepreviouscircuitwasasimplifiedALU:– WhenS=00,R=A+B– WhenS=01,R=A–B– WhenS=10,R=AANDB– WhenS=11,R=AORB
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SimplifiedALU
• Wecanstring1-bitALUstogethertomakebigger-bitALUs(e.g.32bALU)
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1bitALU
…
A31B31S
R0 R1 R2 R3 R31
1bitALU
Co
RABS
Ci
1bitALU
1bitALU
1bitALU
1bitALU
A0B0S A1B1S A2B2S A3B3S
CoCi
Combinatorialvs.SequentialLogic
• TheCPUschematicshows bothcombinatorialandsequentiallogicblocks
• CombinatorialLogic– Combiningmultiplelogicblocks– Theoutputisafunctiononlyofthepresentinputs– Thereisnomemoryofpast“states”
• SequentialLogic– Combiningmultiplelogicblocks– Theoutputisafunctionofboththepresentinputsandpastinputs– Thereexistsamemoryofpast“states”
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YourTo-Dos
• Lab7willbedueonFriday,3/9– WewilltakeattendanceforthislabonThursday
• Lab8willbedueonFriday,3/16– I’llissueitthisweek,butyouhavemoretimeforit– WillcontaininfofromnextMonday’slecture
• Reminder:there’saLab9aswell!– Online“quiz”ontheEthicslesson,dueFri.3/16
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