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The Von Neumann ArchitectureThe Von Neumann Architecture

Chapter 5.1Chapter 5.1--5.25.2

Von NeumannVon NeumannArchitectureArchitecture

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CMPUT101 Introduction to Computing (c) Yngvi Bjornsson 2

Designing ComputersDesigning Computers

All computers more or less based on the sameAll computers more or less based on the same

basic design, thebasic design, the Von Neumann ArchitectureVon Neumann Architecture!!

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The Von Neumann ArchitectureThe Von Neumann Architecture

Memory

Processor (CPU)

Input-OutputControl Unit

ALU

Store data and programStore data and program

Execute programExecute program

Do arithmetic/logic operationsDo arithmetic/logic operations

requested by programrequested by program

Communicate withCommunicate with

"outside world", e.g."outside world", e.g. ScreenScreen

KeyboardKeyboard

Storage devicesStorage devices

......

Bus

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Memory SubsystemMemory Subsystem

Memory, also calledMemory, also called RAMRAM ((RRandomandomAAccessccess MMemory),emory),

Consists of many memory cells (storage units) of a fixed size.Consists of many memory cells (storage units) of a fixed size.

Each cell has an address associated with it: 0, 1, Each cell has an address associated with it: 0, 1,

All accesses to memory are to a specified address.All accesses to memory are to a specified address.A cell is the minimum unit of access (fetch/store a complete cell).A cell is the minimum unit of access (fetch/store a complete cell).

The time it takes to fetch/store a cell is the same for all cells.The time it takes to fetch/store a cell is the same for all cells.

When the computer is running, bothWhen the computer is running, both ProgramProgram

Data (variables)Data (variables)

are stored in the memory.are stored in the memory.

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RAMRAM Need to distinguish betweenNeed to distinguish between

thethe addressaddress of a memory cell andof a memory cell andthethe contentcontent of a memory cellof a memory cell

Memory width (Memory width (WW):):

How many bits is each memoryHow many bits is each memorycell, typically onecell, typically one bytebyte (=8 bits)(=8 bits)

Address width (Address width (NN):): How many bits used to representHow many bits used to represent

each address, determines theeach address, determines themaximum memory size =maximum memory size = addressaddressspacespace

If address width isIf address width is NN--bits, thenbits, thenaddress space isaddress space is 22NN (0,1,...,2(0,1,...,2NN--1)1)

...

00

11

22

22NN--11

1 bit1 bit

WW

00000000000000010000000000000001

NN

22NN

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Memory Size / SpeedMemory Size / Speed

Typical memory in a personal computer (PC):Typical memory in a personal computer (PC): 64MB64MB -- 256MB256MB

Memory sizes:Memory sizes:

KilobyteKilobyte (KB)(KB) = 2= 21010 == 1,024 bytes ~ 1 thousand1,024 bytes ~ 1 thousand Megabyte(MB)Megabyte(MB) = 2= 22020 == 1,048,576 bytes ~ 1 million1,048,576 bytes ~ 1 million

GigabyteGigabyte (GB)(GB) = 2= 23030 == 1,073,741,824 bytes ~ 1 billion1,073,741,824 bytes ~ 1 billion

Memory Access Time (read from/ write to memory)Memory Access Time (read from/ write to memory)

5050--75 nanoseconds (1 nsec. = 0.000000001 sec.)75 nanoseconds (1 nsec. = 0.000000001 sec.)

RAM isRAM is volatile (can only store when power is on)volatile (can only store when power is on)

relatively expensiverelatively expensive

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Operations on MemoryOperations on Memory Fetch (address):Fetch (address):

Fetch a copy of the content of memory cell with the specifiedFetch a copy of the content of memory cell with the specified

address.address.

NonNon--destructive, copies value in memory cell.destructive, copies value in memory cell.

Store (address, value):Store (address, value):

Store the specified value into the memory cell specified by address.Store the specified value into the memory cell specified by address.

Destructive, overwrites the previous value of the memory cell.Destructive, overwrites the previous value of the memory cell.

The memory system is interfaced via:The memory system is interfaced via: Memory Address Register (MAR)Memory Address Register (MAR)

Memory Data Register (MDR)Memory Data Register (MDR)

Fetch/Store signalFetch/Store signal

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Structure of the Memory SubsystemStructure of the Memory Subsystem

Fetch(address)Fetch(address) Load address into MAR.Load address into MAR.

Decode the address in MAR.Decode the address in MAR.

Copy the content of memory cell withCopy the content of memory cell withspecified address into MDR.specified address into MDR.

Store(address, value)Store(address, value) Load the address into MAR.Load the address into MAR.

Load the value into MDR.Load the value into MDR. Decode the address in MARDecode the address in MAR

Copy the content of MDR intoCopy the content of MDR intomemory cell with the specifiedmemory cell with the specifiedaddress.address.

MAR MDR

...

Memorydecoder

circuit

Fetch/Storecontroller

F/S

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Input/Output SubsystemInput/Output Subsystem

Handles devices that allow the computer system to:Handles devices that allow the computer system to:

Communicate and interact with the outside worldCommunicate and interact with the outside world

Screen, keyboard, printer, ...Screen, keyboard, printer, ...

Store information (massStore information (mass--storage)storage)

HardHard--drives, floppies, CD, tapes, drives, floppies, CD, tapes,

MassMass--Storage Device Access Methods:Storage Device Access Methods:

Direct Access Storage Devices (DASDs)Direct Access Storage Devices (DASDs) HardHard--drives, floppydrives, floppy--disks, CDdisks, CD--ROMs, ...ROMs, ...

Sequential Access Storage Devices (SASDs)Sequential Access Storage Devices (SASDs) Tapes (for example, used as backup devices)Tapes (for example, used as backup devices)

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I/O ControllersI/O Controllers

Speed of I/O devices is slow compared to RAMSpeed of I/O devices is slow compared to RAM

RAM ~ 50 nsec.RAM ~ 50 nsec.

HardHard--Drive ~ 10msec. = (10,000,000 nsec)Drive ~ 10msec. = (10,000,000 nsec)

Solution:Solution: I/O Controller, a special purpose processor:I/O Controller, a special purpose processor:

Has a small memory buffer, and a control logic to control I/OHas a small memory buffer, and a control logic to control I/Odevice (e.g. move disk arm).device (e.g. move disk arm).

Sends an interrupt signal to CPU when done read/write.Sends an interrupt signal to CPU when done read/write. Data transferred between RAM and memory buffer.Data transferred between RAM and memory buffer.

Processor free to do something else while I/O controllerProcessor free to do something else while I/O controllerreads/writes data from/to device into I/O buffer.reads/writes data from/to device into I/O buffer.

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I/O controller

Structure of the I/O SubsystemStructure of the I/O Subsystem

I/O Buffer

Control/Logic

I/O device

Data from/to memoryInterrupt signal (to processor)

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The ALU SubsystemThe ALU Subsystem

The ALU (Arithmetic/Logic Unit) performsThe ALU (Arithmetic/Logic Unit) performs

mathematical operations (+,mathematical operations (+, --, x, /, ), x, /, )

logic operations (=, , and, or, not, ...)logic operations (=, , and, or, not, ...)

In today's computers integrated into the CPUIn today's computers integrated into the CPU

Consists of:Consists of:

Circuits to do the arithmetic/logic operations.Circuits to do the arithmetic/logic operations.

Registers (fast storage units) to store intermediateRegisters (fast storage units) to store intermediate

computational results.computational results.

Bus that connects the two.Bus that connects the two.

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Structure of the ALUStructure of the ALU

Registers:Registers: Very fast local memory cells, thatVery fast local memory cells, that

store operands of operations andstore operands of operations andintermediate results.intermediate results.

CCRCCR (condition code register), a(condition code register), aspecial purpose register that storesspecial purpose register that storesthe result of operationsthe result of operations

ALU circuitry:ALU circuitry:

Contains an array of circuits to doContains an array of circuits to domathematical/logic operations.mathematical/logic operations.

Bus:Bus: Data path interconnecting theData path interconnecting the

registers to the ALU circuitry.registers to the ALU circuitry.

ALU circuitry

GT EQ LT

R0

R1

R2

Rn

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The Control UnitThe Control Unit

Program is stored in memoryProgram is stored in memory

as machine language instructions, in binaryas machine language instructions, in binary

The task of theThe task of the control unitcontrol unit is to execute programsis to execute programsby repeatedly:by repeatedly:

FetchFetch from memory the next instruction to be executed.from memory the next instruction to be executed.

DecodeDecode it, that is, determine what is to be done.it, that is, determine what is to be done.

ExecuteExecute it by issuing the appropriate signals to theit by issuing the appropriate signals to the

ALU, memory, and I/O subsystems.ALU, memory, and I/O subsystems.

Continues until the HALT instructionContinues until the HALT instruction

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Machine Language InstructionsMachine Language Instructions

A machine language instruction consists of:A machine language instruction consists of:

Operation codeOperation code, telling which operation to perform, telling which operation to perform

Address field(s)Address field(s), telling the memory addresses of the, telling the memory addresses of the

values on which the operation works.values on which the operation works.

Example: ADD X, YExample: ADD X, Y (Add content of memory locations(Add content of memory locationsX and Y, and store back in memory location Y).X and Y, and store back in memory location Y).

Assume: opcode for ADD is 9, and addresses X=99, Y=100Assume: opcode for ADD is 9, and addresses X=99, Y=100

00001001 0000000001100011 0000000001100100

Opcode (8 bits)Opcode (8 bits) Address 1 (16 bits)Address 1 (16 bits) Address 2 (16 bits)Address 2 (16 bits)

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Instruction Set DesignInstruction Set Design

Two different approaches:Two different approaches:

Reduced Instruction Set Computers (RISC)Reduced Instruction Set Computers (RISC)

Instruction set as small and simple as possible.Instruction set as small and simple as possible. Minimizes amount of circuitryMinimizes amount of circuitry ----> faster computers> faster computers

Complex Instruction Set Computers (CISC)Complex Instruction Set Computers (CISC)

More instructions, many very complexMore instructions, many very complex

Each instruction can do more work, but require moreEach instruction can do more work, but require morecircuitry.circuitry.

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Typical Machine InstructionsTypical Machine Instructions

Notation:Notation:

We use X, Y, Z to denote RAM cellsWe use X, Y, Z to denote RAM cells

Assume only one register R (for simplicity)Assume only one register R (for simplicity) Use EnglishUse English--like descriptions (should be binary)like descriptions (should be binary)

Data Transfer InstructionsData Transfer Instructions

LOADLOAD XX Load content of memory location X to RLoad content of memory location X to R

STORE XSTORE X Load content of R to memory location XLoad content of R to memory location X

MOVEMOVE X, YX, Y Copy content of memory location X to loc. YCopy content of memory location X to loc. Y(not absolutely necessary)(not absolutely necessary)

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Machine Instructions (cont.)Machine Instructions (cont.)

ArithmeticArithmetic ADD X, Y, ZADD X, Y, Z CON(Z) = CON(X) + CON(Y)CON(Z) = CON(X) + CON(Y)

ADD X, YADD X, Y CON(Y) = CON(X) + CON(Y)CON(Y) = CON(X) + CON(Y)

ADD XADD X R = CON(X) + RR = CON(X) + R similar instructions for other operators, e.g. SUBTR,OR, ...similar instructions for other operators, e.g. SUBTR,OR, ...

CompareCompare

COMPARE X, YCOMPARE X, YCompare the content of memory cell X to the content of memoryCompare the content of memory cell X to the content of memory

cell Y and set the condition codes (CCR) accordingly.cell Y and set the condition codes (CCR) accordingly.

E.g.E.g. If CON(X) = R then set EQ=1, GT=0, LT=0If CON(X) = R then set EQ=1, GT=0, LT=0

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Machine Instructions (cont.)Machine Instructions (cont.)

BranchBranch

JUMP XJUMP X Load next instruction from memory loc. XLoad next instruction from memory loc. X

JUMPGT XJUMPGT X Load next instruction from memory loc. XLoad next instruction from memory loc. Xonly if GT flag in CCR is set, otherwise loadonly if GT flag in CCR is set, otherwise load

statement from next sequence loc. asstatement from next sequence loc. as

usual.usual.

JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQJUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ ControlControl

HALTHALT Stop program execution.Stop program execution.

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ExampleExample

PseudoPseudo--code:code: Set A to B + CSet A to B + C

Assuming variable:Assuming variable:

A stored in memory cell 100, B stored in memory cellA stored in memory cell 100, B stored in memory cell

150, C stored in memory cell 151150, C stored in memory cell 151

Machine language (really in binary)Machine language (really in binary)

LOAD 150LOAD 150

ADDADD 151151 STORE 100STORE 100

or or

(ADD(ADD 150, 151, 100)150, 151, 100)

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Structure of the Control UnitStructure of the Control Unit

PC (Program Counter):PC (Program Counter): stores the address of next instruction to fetchstores the address of next instruction to fetch

IR (Instruction Register):IR (Instruction Register):

stores the instruction fetched from memorystores the instruction fetched from memory

Instruction Decoder:Instruction Decoder: Decodes instruction and activates necessary circuitryDecodes instruction and activates necessary circuitry

Instruction

Decoder

IR

+1

PC

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von Neumannvon Neumann

ArchitectureArchitecture

von Neumannvon Neumann

ArchitectureArchitecture

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How does this all work together?How does this all work together?

Program Execution:Program Execution:

PC is set to the address where the first programPC is set to the address where the first program

instruction is stored in memory.instruction is stored in memory. Repeat until HALT instruction or fatal errorRepeat until HALT instruction or fatal error

Fetch instructionFetch instruction

Decode instructionDecode instruction

Execute instructionExecute instruction

End of loopEnd of loop

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Program Execution (cont.)Program Execution (cont.)

Fetch phaseFetch phase

PCPC ----> MAR> MAR (put address in PC into MAR)(put address in PC into MAR)

Fetch signalFetch signal (signal memory to fetch value into MDR)(signal memory to fetch value into MDR) MDRMDR ----> IR> IR (move value to Instruction Register)(move value to Instruction Register)

PC + 1PC + 1 ----> PC> PC (Increase address in program counter)(Increase address in program counter)

Decode PhaseDecode Phase IRIR --> Instruction decoder> Instruction decoder(decode instruction in IR)(decode instruction in IR)

Instruction decoder will then generate the signals toInstruction decoder will then generate the signals to

activate the circuitry to carry out the instructionactivate the circuitry to carry out the instruction

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Program Execution (cont.)Program Execution (cont.)

Execute PhaseExecute Phase

Differs from one instruction to the next.Differs from one instruction to the next.

Example:Example: LOAD X (load value in addr. X into register)LOAD X (load value in addr. X into register)

IR_addressIR_address --> MAR> MAR

Fetch signalFetch signal

MDRMDR ----> R> R ADD XADD X

left as an exerciseleft as an exercise

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Instruction Set for Our Von Neumann MachineInstruction Set for Our Von Neumann MachineOpcodeOpcode OperationOperation MeaningMeaning

0000 LOAD X CON(X) --> R

0001 STORE X R --> CON(X)

0010 CLEAR X 0 --> CON(X)

0011 ADD X R + CON(X) --> R

0100 INCREMENT X CON(X) + 1 --> CON(X)

0101 SUBTRACT X R - CON(X) --> R

0101 DECREMENT X CON(X) - 1 --> CON(X)

0111

COMPARE X If CON(X) > R then GT = 1 else 0

If CON(X) = R then EQ = 1 else 0

If CON(X) < R then LT = 1 else 0

1000 JUMP X Get next instruction from memory location X1001 JUMPGT X Get next instruction from memory loc. X if GT=1

... JUMPxx X xx = LT / EQ / NEQ

1101 IN X Input an integervalue and store in X

1110 OUT X Output, in decimal notation, content of mem. loc. X

1111 HALT Stop program execution

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