cmput101 introduction to computing(c) yngvi bjornsson & vadim bulitko1 the von neumann...

CMPUT101 Introduction to Computing (c) Yngvi Bjornsson & Vadim Bulitko 1

The Von Neumann The Von Neumann ArchitectureArchitecture

Odds and EndsOdds and EndsChapter 5.1-5.2Chapter 5.1-5.2

Von NeumannVon NeumannArchitectureArchitecture


Designing ComputersDesigning Computers

• All computers more or less based on the same All computers more or less based on the same basic design, the basic design, the Von Neumann ArchitectureVon Neumann Architecture!!



• Model for designing and building computers, Model for designing and building computers, based on the following three characteristics:based on the following three characteristics:

1)1) The computer consists of four main sub-systems:The computer consists of four main sub-systems:• MemoryMemory• ALU (Arithmetic/Logic Unit)ALU (Arithmetic/Logic Unit)• Control UnitControl Unit• Input/Output System (I/O)Input/Output System (I/O)

2)2) Program is stored in memory during execution.Program is stored in memory during execution.3)3) Program instructions are executed sequentially.Program instructions are executed sequentially.



Memory

Processor (CPU)

Input-OutputControl Unit

ALUStore data and programStore data and program

Execute programExecute program

Do arithmetic/logic operationsDo arithmetic/logic operationsrequested by programrequested by program

Communicate withCommunicate with"outside world", e.g. "outside world", e.g. • ScreenScreen• KeyboardKeyboard• Storage devices Storage devices • ......

Bus


Structure of the Memory Structure of the Memory SubsystemSubsystem

• Fetch(address)Fetch(address)– Load address into MAR.Load address into MAR.– Decode the address in MAR.Decode the address in MAR.– Copy the content of memory cell with Copy the content of memory cell with

specified address into MDR.specified address into MDR.• Store(address, value)Store(address, value)

– Load the address into MAR.Load the address into MAR.– Load the value into MDR.Load the value into MDR.– Decode the address in MARDecode the address in MAR– Copy the content of MDR into memory Copy the content of MDR into memory

cell with the specified address.cell with the specified address.

MAR MDR

...

Memorydecodercircuit

Fetch/Storecontroller

F/S


Implementation of the Implementation of the Memory SubsystemMemory Subsystem


CACHE - Modern additionCACHE - Modern addition

• High-speed memory, integrated High-speed memory, integrated on the CPUon the CPU– Ca. 10 times faster than RAMCa. 10 times faster than RAM– Relatively small (128-256K)Relatively small (128-256K)

• Stores data most recently usedStores data most recently used– Principle of LocalityPrinciple of Locality

• When CPU needs data:When CPU needs data:– First looks in the cache, only if not First looks in the cache, only if not

there, then fetch from RAM.there, then fetch from RAM.– If cache full, new data overwrites If cache full, new data overwrites

older entries in cache.older entries in cache.

Memory

Processor (CPU)

I/O

Control Unit

ALU

Cache


I/O Subsystem: Hard-DrivesI/O Subsystem: Hard-Drives• Uses magnetic Uses magnetic surfacessurfaces to store the data. to store the data.

– Each surface has many circular Each surface has many circular trackstracks..– Each track consists of many Each track consists of many sectorssectors..

The surfaces rotate at a high speed The surfaces rotate at a high speed Typically ~7000 rev/minTypically ~7000 rev/min

The read/write arm moves:The read/write arm moves:back and forth to locate a trackback and forth to locate a track


Hard-DriveHard-Drive


Disk Access TimeDisk Access Time• The time it takes to read/write data to a disk, consists of:The time it takes to read/write data to a disk, consists of:

– Seek timeSeek time• The time it takes to position the read/write head over correct track The time it takes to position the read/write head over correct track

(depends on arm movement speed).(depends on arm movement speed).– LatencyLatency

• The time waiting for the beginning of the desired sector to get under the The time waiting for the beginning of the desired sector to get under the read/write head (depends on rotation speed) read/write head (depends on rotation speed)

– Transfer time Transfer time • The time needed for the sector to pass under the read/write head The time needed for the sector to pass under the read/write head

(depends on rotation speed)(depends on rotation speed)– Disk Access Time = Seek time + Latency + Transfer timeDisk Access Time = Seek time + Latency + Transfer time

• Measure worst, best, and average case. (Measure worst, best, and average case. (Example: p. 189Example: p. 189))


Structure of the ALUStructure of the ALU• Registers:Registers:

– Very fast local memory cells, that Very fast local memory cells, that store operands of operations and store operands of operations and intermediate results.intermediate results.

– CCRCCR (condition code register), a (condition code register), a special purpose register that stores special purpose register that stores the result of <, = , > operationsthe result of <, = , > operations

• ALU circuitry:ALU circuitry:– Contains an array of circuits to do Contains an array of circuits to do

mathematical/logic operations.mathematical/logic operations.• Bus:Bus:

– Data path interconnecting the Data path interconnecting the registers to the ALU circuitry.registers to the ALU circuitry.

ALU circuitry

GT EQ LT

R0R1R2

Rn


Implementation of the Implementation of the ALUALU

ALU Circuitry

Every circuit produces a result but only the desired one is selected


Structure of the Control Structure of the Control UnitUnit• PC (Program Counter):PC (Program Counter):

– stores the address of next instruction to fetchstores the address of next instruction to fetch• IR (Instruction Register):IR (Instruction Register):

– stores the instruction fetched from memorystores the instruction fetched from memory• Instruction Decoder:Instruction Decoder:

– Decodes instruction and activates necessary circuitryDecodes instruction and activates necessary circuitry

Instruction Decoder

IR

+1

PC


Machine Language Machine Language InstructionsInstructions

• A machine language instruction consists of:A machine language instruction consists of:– Operation codeOperation code, telling which operation to perform, telling which operation to perform– Address field(s)Address field(s), telling the memory addresses of the , telling the memory addresses of the

values on which the operation works.values on which the operation works.• Example: ADD X, Y Example: ADD X, Y (Add content of memory locations X (Add content of memory locations X

and Y, and store back in memory location Y).and Y, and store back in memory location Y).• Assume: opcode for ADD is 9, and addresses X=99, Y=100Assume: opcode for ADD is 9, and addresses X=99, Y=100

00001001 0000000001100011 0000000001100100Opcode (8 bits)Opcode (8 bits) Address 1 (16 bits)Address 1 (16 bits) Address 2 (16 bits)Address 2 (16 bits)


Implementation of the Implementation of the

Control UnitControl Unit


von Neumannvon Neumann

ArchitectureArchitecture

von Neumannvon Neumann

ArchitectureArchitecture


How does this all work How does this all work together?together?

• Program Execution:Program Execution:– PC is set to the address where the first program PC is set to the address where the first program

instruction is stored in memory.instruction is stored in memory.– Repeat until HALT instruction or fatal errorRepeat until HALT instruction or fatal error

Fetch instructionFetch instruction Decode instructionDecode instruction Execute instructionExecute instruction

End of loopEnd of loop


Program Execution (cont.)Program Execution (cont.)

• Fetch phaseFetch phase– PC --> MARPC --> MAR (put address in PC into MAR)(put address in PC into MAR)– Fetch signalFetch signal (signal memory to fetch value into MDR)(signal memory to fetch value into MDR)– MDR --> IRMDR --> IR (move value to Instruction Register)(move value to Instruction Register)– PC + 1 --> PC PC + 1 --> PC (Increase address in program counter)(Increase address in program counter)

• Decode PhaseDecode Phase– IR -> Instruction decoder IR -> Instruction decoder (decode instruction in IR)(decode instruction in IR)– Instruction decoder will then generate the signals to Instruction decoder will then generate the signals to

activate the circuitry to carry out the instructionactivate the circuitry to carry out the instruction


Program Execution (cont.)Program Execution (cont.)

• Execute Phase Execute Phase – Differs from one instruction to the next.Differs from one instruction to the next.

• Example:Example:– LOAD X (load value in addr. X into register)LOAD X (load value in addr. X into register)

• IR_address -> MARIR_address -> MAR• Fetch signalFetch signal• MDR --> RMDR --> R

– ADD X ADD X • left as an exerciseleft as an exercise


Instruction Set for Our Von Instruction Set for Our Von Neumann MachineNeumann Machine

OpcodeOpcode OperationOperation MeaningMeaning0000 LOAD X CON(X) --> R0001 STORE X R --> CON(X)0010 CLEAR X 0 --> CON(X)0011 ADD X R + CON(X) --> R0100 INCREMENT X CON(X) + 1 --> CON(X)0101 SUBTRACT X R - CON(X) --> R0101 DECREMENT X CON(X) - 1 --> CON(X)

0111COMPARE X If CON(X) > R then GT = 1 else 0

If CON(X) = R then EQ = 1 else 0

If CON(X) < R then LT = 1 else 01000 JUMP X Get next instruction from memory location X1001 JUMPGT X Get next instruction from memory loc. X if GT=1... JUMPxx X xx = LT / EQ / NEQ1101 IN X Input an integer value and store in X1110 OUT X Output, in decimal notation, content of mem. loc. X1111 HALT Stop program execution

cmput101 introduction to computing(c) yngvi bjornsson & vadim bulitko1 the von neumann...

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memory subsystem slide

neumann architecture

readwrite data

track slide

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bus slide

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