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CMPEN 411 VLSI Digital Circuits Kyusun Choi Chip Fabrication and Layout

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Page 1: CMPEN 411 VLSI Digital Circuits

CMPEN 411 VLSI Digital Circuits

Kyusun Choi

Chip Fabrication and Layout

Page 2: CMPEN 411 VLSI Digital Circuits
Page 3: CMPEN 411 VLSI Digital Circuits
Page 4: CMPEN 411 VLSI Digital Circuits

Substrate to VDD contact

Source to VDD

contact

N well, green

Metal2 to metal1

connection, VIA

Metal2 wire,

M2Drain, P-diffusion

Metal1 to P-diffusion

connection, CONTACT

VDD to source

connection, M1

VDD wire, M1

Poly wire,

P

Gate, poly

Source,

P-diffusion

Page 5: CMPEN 411 VLSI Digital Circuits
Page 6: CMPEN 411 VLSI Digital Circuits

Also check the transistor layout tutorial at:

http://www.egr.msu.edu/classes/ece410/mason/files/TutorialB.pdf

or local copy at:

http://www.cse.psu.edu/~kyusun/class/cmpen411/13s/hw/msuOldTutorialB.pdf

http://www.egr.msu.edu/classes/ece410/mason/files/TutorialB.pdf
http://www.cse.psu.edu/~kyusun/class/cmpen411/13s/hw/msuOldTutorialB.pdf
Page 7: CMPEN 411 VLSI Digital Circuits
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Using ‘gimp’ program running in Linux to delete black background color.

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Fig. 1. Cross-section of a 64-bit

high-speed processor in a 90nm

technology. (Courtesy: IBM)

Page 21: CMPEN 411 VLSI Digital Circuits
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CMPEN 411 VLSI Digital Circuits Lecture 03: MOS …kxc104/class/cmpen411/16s/lec/C411L03...CMPEN 411 L03 S.1 CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi

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CMPEN 411 VLSI Digital Circuits - cse.psu.edu

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CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 16

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CMPEN 411 VLSI Digital Circuits Lecture 01: Introduction