cmpen 411 vlsi digital circuits spring 2011 lecture 01...
TRANSCRIPT
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CMPEN 411VLSI Digital Circuits
Spring 2011
Lecture 01: Introduction
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Lecture 01: Introduction
� Kyusun Choi
� Course Website: http://www.cse.psu.edu/~kyusun/class/cmpen411/11s/index.html
� [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
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How Do the Pieces Fit Together?
I/O systemInstr. Set Proc.
Compiler
OperatingSystem
Application
Instruction SetArchitecture
Firmware
Memory
system
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Digital Design
Circuit Design
� Coordination of many levels of abstraction
� Under a rapidly changing set of forces
� Design, measurement, and evaluation
Datapath & Control
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Course Contents
� Introduction to digital integrated circuits
� CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Memory circuit design.
� Course goals
Ability to design and implement CMOS digital circuits and
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� Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability
� Course prerequisites
� EE 310. Electronic Circuit Design
� CMPEN 471. Logic Design of Digital Systems
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Background from CMPEN 471 and EE 310
� Basic circuit theory
� resistance, capacitance, inductance
� MOS gate characteristics
� Hardware description language
� VHDL or verilog
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� Use of modern EDA tools
� simulation, synthesis, validation (e.g., Synopsys)
� schematic capture tools (e.g., LogicWorks)
� Logic design
� logical minimization, FSMs, component design
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Course Structure
� Design and tool intensive class
� Industrial Standard toolset for layout
- Online documentation and tutorials
� HSPICE for circuit simulation
� unix (Sun/Solaris) operating system environment
� Lectures:
� 2 weeks on the CMOS inverter
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� 2 weeks on the CMOS inverter
� 3 weeks on static and dynamic CMOS gates
� 2 weeks on C, R, and L effects
� 2 week on sequential CMOS circuits
� 2 weeks on design of datapath structures
� 2 weeks on memory design
� 1 week on design for technology scaling, trends
Schedule is on-line syllabus
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What is the most important invention for the last 50 years?
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The evolution of IC
� When was the first transistor invented?
A. 1945 B. 1947 C. 1951 D. 1958
� The inventors were in which company?
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� The inventors were in which company?
A. IBM B. Bell Lab C. TI D. Motorola
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The evolution of IC
� When was the first transistor invented?
� Modern-day electronics began with the invention in 1947 of the transfer resistor, also known as the bi-polar transistor by Bardeen et.al at Bell Laboratories
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The evolution of IC
� When was the first IC invented?
A. 1956 B. 1958 C. 1959 D. 1961
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� The inventor was with which company?
A. IBM B. Bell Labs C. TI D. Motorola
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The evolution of IC
� When was the first IC (integrated circuit) invented?
� In 1958 the integrated circuit was born when Jack Kilby at Texas Instruments successfully interconnected, by hand, several transistors, resistors and capacitors on a single substrate
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Transistor Revolution
� Transistor –Bardeen et.al. (Bell Labs) in 1947
� Bipolar transistor – Schockley in 1949
� First bipolar digital logic gate – Harris in 1956
� First monolithic IC – Jack Kilby in 1958
� First commercial IC logic gates – Fairchild 1960
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� First commercial IC logic gates – Fairchild 1960
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MOSFET Technology
� MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935
� CMOS – 1960’s, but plagued with manufacturing problems (used in watches due to their power limitations)
� PMOS in 1960’s (calculators)
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� PMOS in 1960’s (calculators)
� NMOS in 1970’s (4004, 8080) – for speed
� CMOS in 1980’s – preferred MOSFET technology because of power benefits
� BiCMOS, Gallium-Arsenide, Silicon-Germanium
� SOI, Copper-Low K, strained silicon, High-k gate oxide...
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Worldwide Semiconductor RevenueSource: ISSCC 2003 G. Moore “No exponential is forever, but ‘forever’ can be delayed”
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Transistors shipped per year
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How many transistors you can buy with 1$?
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Average Transistor Price by Year
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1’’ Wafer in 1964 vs. 300 mm (12 ”) Wafer in 2003
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The IC in 1961 vs. Intel Pentium 4 in 2004
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Moore’s Law
� In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time).
� Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s.
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crossed in the 1980’s.
� 2300 transistors, 108 KHz clock (Intel 4004) - 1971
� 16 Million transistors (Ultra Sparc III)- 1998
� 42 Million, 2 GHz clock (Intel P4) - 2001
� 125 Million, 3.4Ghz (Intel P4 Prescott)- 2004 Feb 02
� 234 Million, IBM Cell processor, 2005
� 1.7 Billion, 1.6Ghz (Intel Itanium-2)-2006, Sept.
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Moore’s Law plot (from his original paper)is
tors
106
107
108
integrated
circuit
invented
109
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year
# t
ran
sis
t
100
101
100
102
100
103
104
105
10
memoryCPU
19701960 1980 1990
invented
2000 2010
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Moore’s Law in Microprocessors
Pentium® procP6
10
100
1000
Transistors (MT)
2X growth in 1.96 years!
# transistors on lead microprocessors double every 2 years
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400480088080
8085 8086
286386
486Pentium® proc
0.001
0.01
0.1
1
1970 1980 1990 2000 2010
Year
Transistors (MT)
Courtesy, Intel
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# of Transistors per Die
Source: ISSCC 2003 G. Moore “No exponential is forever, but ‘forever’ can be delayed”
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Intel 4004 Microprocessor (10000 nm) 1971
2300 transistors13.5 mm2108k Hz
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Intel Pentium 4 –Prescott (2004)
90 nmArea: 112 mm2125 M transistorsL1-Instruction: 16KL1-Data: 16KL2: 1MB
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Two chips you are seeing today
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Microprocessor ASIC (Application Specific IC)
366MHz 40mm2 3.65M 40Mhz 10 mm2 500K
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IBM Cell Overview
PPU
SPU
SPU
SPU
SPU
MIC
RRAC
BIC
MIB
Cell Prototype Die (Pham et al, ISSCC 2005)
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� IBM/Toshiba/Sony joint project - 4-5 years, 400 designers, 3/9/2001, $400M, 234 million transistors, 4+ Ghz, 256 Gflops (billions of floating pointer operations per second)
SPU
SPU
SPU
SPU
C
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State-of-the Art: Lead Microprocessors
Freq
(HZ)
Transistors Die size
mm2
Power Date
Server IBM Power 4+ 1.7G 180M 267 N/A 2003
Itanium 2 1.5G 410M 374 130W 2003
IBM Power 5 2G 276M 389 N/A 2004/2
PC IBM Power PC970 1.8G 58M 118 42W 2003/6
Pentium 4 3.2G 55M 131 82W 2003/6
AMD Athlon 64 2.2G 105M 192 89W 2003/9
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Pentium 4 180 nm (2001) 1.7 G Hz 42 M transistors 217 mm2 Pentium 4 130 nm (2003) 3.2G Hz 55 M Transistors 131 mm2 Pentium 4 90 nm (2004) 3.4 Hz 125 M Transistors 112 mm2 Pentium on 65nm (2005/2006) 250 Million Pentium on 45nm (2007) 400 to 500 Million
AMD Athlon 64 2.2G 105M 192 89W 2003/9
Pentium 4 (Prescott)
3.4G 125M 112 103W 2004/2
(All use 0.13 um technology except Pentium 4 – Prescott, which uses 90 nm tech)
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State-of-the Art: Lead Microprocessors (up to date)
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300mm wafer and Pentium 4 IC. Photos courtesy of Intel.
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64,000
256,000
1,000,000
4,000,000
16,000,000
64,000,000
100000
1000000
10000000
100000000Kbit capacity/chip
Evolution in DRAM Chip Capacity
0.35-0.4 µm
0.18-0.25 µm
0.13 µm
0.1 µm
0.07 µm
human memoryhuman DNA
book
4X growth every 3 years!
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64
256
1,000
4,000
16,000
10
100
1000
10000
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010
Year
Kbit capacity/chip
1.6-2.4 µm
1.0-1.2 µm
0.7-0.8 µm
0.5-0.6 µm
0.35-0.4 µm
encyclopedia2 hrs CD audio30 sec HDTV
page
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Die Size Growth
486Pentium ® proc
P6
100
Die size (mm)
Die size grows by 14% to satisfy Moore’s Law
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40048008
808080858086
286386
486Pentium ® proc
1
10
1970 1980 1990 2000 2010
Year
Die size (mm)
Courtesy, Intel
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Clock Frequency
Lead microprocessors frequency doubles every 2 years
P6
Pentium ® proc100
1000
10000
Frequency (Mhz)
2X every 2 years
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Pentium ® proc486
3862868086
8085
8080
8008
40040.1
1
10
1970 1980 1990 2000 2010
Year
Frequency (Mhz)
Courtesy, Intel
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Power Dissipation
P6Pentium ® proc
486
386
2868086
10
100
Power (Watts)
Lead Microprocessors power continues to increase
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3868086
80858080
80084004
0.1
1
1971 1974 1978 1985 1992 2000
Year
Power (Watts)
Courtesy, Intel
Power delivery and dissipation will be prohibitive
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Power Density
100
1000
10000Power Density (W/cm2)
Nuclear
Reactor
Rocket
Nozzle
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4004
8008
8080
8085
8086
286386
486Pentium® procP6
1
10
1970 1980 1990 2000 2010
Year
Power Density (W/cm2)
Hot Plate
Power density too high to keep junctions at low temp
Courtesy, Intel
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Power Density
100
1000
10000Power Density (W/cm2)
Nuclear
Reactor
Rocket
Nozzle
Sp11 CMPEN 411 L01 S33
4004
8008
8080
8085
8086
286386
486Pentium® procP6
1
10
1970 1980 1990 2000 2010
Year
Power Density (W/cm2)
Hot Plate
Power density too high to keep junctions at low temp
Courtesy, Intel
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ITRS
� The “International Technology Roadmap for Semiconductors” (ITRS) is the industry’s prediction for the future of semiconductors.
� It is mostly an extrapolation of existing trends.
� The ITRS is often “slow”.
� http://public.itrs.net
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� http://public.itrs.net
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Technology Directions: “Old” SIA Roadmap
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
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Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183
Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4
http://public.itrs.net
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Technology Scaling
� Technology shrinks by ~0.7 per generation
� With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly
� Cost of a function decreases by 2x
� But P
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� But P
� How to design chips with more and more functions?
� Design engineering population does not double every two yearsP
� Hence, a need for more efficient design methods
� Exploit different levels of abstraction
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Design Abstraction Levels
SYSTEM
GATE
MODULE
+
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GATE
CIRCUIT
VoutVin
CIRCUIT
VoutVin
DEVICE
n+
S D
n+
G
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Design Productivity Trends
Logic Tr./Chip
Tr./Staff Month.
x x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
Logic Transistor per Chip(M)
10
100
1,000
10,000
100,000
Productivity
(K) Trans./Staff -Mo.
Complexity
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2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x0.1
0.01
0.001
Logic Transistor per Chip
0.01
0.1
1
(K) Trans./Staff
Courtesy, ITRS Roadmap
Complexity outpaces design productivity
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Design Productivity Crisis
Year Tech. (nm)
Complexity Frequency 3 Yr. Design Staff Size
Staff Costs
1997 350 13 M Tr. 400 MHz 210 $90 M
1998 250 20 M Tr. 500 MHz 270 $120 M
1999 180 32 M Tr. 600 MHz 360 $160 M
2002 130 130 M Tr. 800 MHz 800 $360 M
Sp11 CMPEN 411 L01 S39
��We need to improve the productivity via design automationWe need to improve the productivity via design automation
� 1996: 100 person in P6 team
� 2007: 1600 person in P10 team
� Question: ?? Person in P38 team ?
� Answer: Every inhabitant of our planet
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Major Design Challenges
� Microscopic issues
� ultra-high speeds
� power dissipation and supply rail drop
� growing importance of interconnect
noise, crosstalk
� Macroscopic issues
� time-to-market
� design complexity (millions of gates)
� high levels of abstractions
reuse and IP, portability
Sp11 CMPEN 411 L01 S40
� noise, crosstalk
� reliability, manufacturability
� clock distribution
� reuse and IP, portability
� systems on a chip (SoC)
� tool interoperability
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Next Lecture and Reminders
� Next lecture
� Design metrics
- Reading assignment – 1.3
� Reminders
Sp11 CMPEN 411 L01 S41