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Chapter 3 CMOS Processing Technology116

adding checkerboard links to tie the wires together. Additionally, there may be spacingrules that are applied to long, closely spaced parallel metal lines.

Older nonplanarized processes required greater width and spacing on upper-level metawires (e.g., metal3) to prevent breaks or shorts between adjoining wires caused by the vertica

topology of the underlying layers. This is no longer a consideration for modern planarizedprocesses. Nevertheless, width and spacing are still greater for thicker metal layers.

Mask Summary:Metal rules may be complicated by varying spacing dependent onwidth: As the width increases, the spacing increases. Metal overlap over contact might bezero or nonzero. Guidelines will also exist for electromigration, as discussed in Section7.3.3.1.

3.3.1.5 Via Rules Processes may vary in whether they allow stackedvias to be placed overpolysilicon and diffusion regions. Some processes allow vias to be placed within theseareas, but do not allow the vias to straddle the boundary of polysilicon or diffusion. Thisresults from the sudden vertical topology variations that occur at sublayer boundariesModern planarized processes permit stacked vias, which reduces the area required to pasfrom a lower-level metal to a high-level metal.

Mask Summary:Vias are normally of uniform size within a layer. They may increasein size toward the top of a metal stack. For instance, large vias required on power bussesare constructed from an array of uniformly sized vias.

3.3.1.6 Other Rules The passivation or overglass layer is a protective layer of SiO2 (glassthat covers the final chip. Appropriately sized openings are required at pads and any inter-nal test points.

Some additional rules that might be present in some processes are as follows:

Extension of polysilicon or metal beyond a contact or via

Differing gate poly extensions depending on the device length

Maximum width of a feature

Minimum area of a feature (small pieces of photoresist can peel off and float away

Minimum notch sizes (small notches are rarely beneficial and can interfere withresolution enhancement techniques)

3.3.1.7 Summary Whereas earlier processes tended to be process driven and frequentlyhad long and involved design rules, processes have become increasingly designer friendlyor, more specifically, computer friendly (most of the mask geometries for designs are algo-rithmically produced). Companies sometimes create generic rules that span a number odifferent CMOS foundries that they might use. Some processes have design guidelines

that feature structures to be avoided to ensure good yields. Traditionally, engineers followed yield-improvement cycles to determine the causes of defective chips and modify thelayout to avoid the most common systematic failures. Time to market and product lifecycles are now so short that yield improvement is only done for the highest volume partsIt is often better to reimplement a successful product in a new, smaller technology ratherthan to worry about improving the yield on the older, larger process.

3.3.2 Scribe Line and Other Structures

The scribe linesurrounds the completed chip where it is cut with a diamond saw. The construction of the scribe line varies from manufacturer to manufacturer. It is designed to

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