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    Zou Zhige VLSI, EST 3

    Last Class Exercise

    Calculate the

    Output voltage swing

    (Vx, Vy, Vout=Vx-Vy)

    low frequency Av

    1in

    out

    2

    DD

    SS

    b 3 4

    ( )//V m on opA g r r=

    , , ,

    , 1

    ,

    in com thn x y DD od mp

    in com GS P

    od mn P

    V V V V V

    V V V

    V V

    < <

    = +

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    Zou Zhige VLSI, EST 5

    Introduction

    We have learned current source:Current source can act as a large resistorwithout consuming excessivevoltage headroom.

    MOS in saturation can act as current source.All the amplifier need current source or resistor for load current.

    Current source has many applications:

    current source load for common source amplifiers

    tail current source for differential pairsbias currents for folded cascode amplifierDAC

    Current count and so on.This Chapter we will learn current mirrorforbias elements and signalprocessing components.

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    Table of Contents

    Introduction

    Basic Current Mirrors

    Cascode Current Mirrors

    Active Current Mirrors

    Introduction

    Large-signal analyses

    Small-signal analyses Common response

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    Zou Zhige VLSI, EST 7

    Current Source in Differential amplifier

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    Basic Current Mirrors

    The simplest current source is as follows:

    2 ,1

    ( )2 n oxout TGS

    WI C V V

    L=

    2

    1 2DD

    GS

    RV V

    R R=

    +

    Is this current source

    always constant ?

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    The problem of Basic CM

    Influence of: power supply, process, temperature

    Vgs and Vth are not constant.

    Even if the Vgs is precisely defined, the Id is not constant.

    , Vth will change due to different process or temperature

    We must seek other method of biasing MOS currentsources.

    Current copy from a constant current reference!

    Why?

    But how to

    copy?

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    Copying Current

    Current

    Mirror

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    Basic Current Mirror

    Both in saturation and Neglecting the Lambda, We get:

    It allows precise copying of the current with no dependence on processand temperature !

    2 1( ) /( )out ref W W

    I I

    L L

    =

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    Zou Zhige VLSI, EST 12

    Current Source & Current Sink

    current source

    current sink

    out1

    REF

    out2

    DD

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    Zou Zhige VLSI, EST 13

    Amplifier Bias Example

    All the MOS should have the same channel length!

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    Another Example

    2

    31

    )/()/(

    LWLWRgA LmV=

    Current Transfer!

    )||()||1

    ||( 3322

    11 Lomo

    m

    omV Rrgrg

    rgA =

    Av=?

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    Zou Zhige VLSI, EST 15

    Table of Contents

    Introduction

    Basic Current Mirrors

    Cascode Current Mirrors

    Active Current Mirrors

    Introduction

    Large-signal analyses

    Small-signal analyses Common response

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    Zou Zhige VLSI, EST 16

    Drawback of Basic CM

    Consider the channel length modulation effect:

    Because the load is not constant, so:

    We should reduce the channel length modulation. Or there isother method?

    )1()(

    2

    1 2DSTHGSoxnOUT VVV

    L

    WCuI +=

    )1(

    )1(

    1)/(

    2)/(

    1

    2

    1

    2

    DS

    DS

    D

    D

    V

    V

    LW

    LW

    I

    I

    +

    +=

    21 DSDS VV

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    How about this current mirror ?

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    Simple cascode amplifier

    Large signal behavior (Vin fixed to VG1, Vout (VDS) sweeping from 0 to 3V)

    Which one is better for the ideal current source?

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    Cascode Current Mirror

    Choose , let ,then

    Output resistance:

    Trade-off: accuracy and voltage headroom

    3 3 2pout m o oR g r r=

    YX VV =bV REFout II

    2

    3 3 2 3 3

    1oy p p

    m o o m o

    rV V V

    g r r g r = =

    2oY rR =

    How to get Vb ?

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    Cascode Current Mirror

    To ensure:

    We should have :

    XGSb VVV += 3

    YX VV =

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    Cascode Current Mirror

    Add M0 for Vb

    Choose proper dimension of M0 and M3 for VGS3=VGS0

    If Then:3 1 2( ) /( ) ( ) /( )oW W W W

    L L L L=

    YX VV =

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    Region of M2 and M3

    M2 and M3 both are in triode

    M2 in sat, and M3 in triode

    M2 and M3 both are in sat

    When Vout

    if M2

    triode first, but Vgs2

    constant

    so Vds2 and Id2,3

    Vb constant, Vgs3 its impossible for M3 still in saturation.

    Conclusion: M3 enter triode zone first, then M2

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    Voltage Headroom 1

    min 2 2 21y GS T odV V V V = =

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    Voltage Headroom 2

    min 3 2 3

    1 3

    2

    p GS od TH

    od od

    od

    V V V V V V

    V

    = = +

    =

    Notice: YX VV

    REFout II So:

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    Voltage Headroom 3

    min 3 2

    3 2 2 2

    2

    p od GS

    od GS TH TH

    od TH

    V V V

    V V V V

    V V

    = +

    = + += +

    To ensure:YX VV =

    REFout II So:

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    Low voltage Cascode CM

    In Sub-micro process, the ro isvery small. Cascode is useful.

    In sub-micro process, the voltage

    supply is very low. So, we should reduce the voltage

    headroom.

    Here is A good example

    out

    1

    2

    3

    4b

    DD

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    Low voltage Cascode CM

    M1 in satu

    M2 in satu

    Range of Vb

    The over-drive voltage of M2 is lower than Vth1

    2 2 1GS TH TH V V V

    2x b THV V V

    2 2 1x T H b G S x T HV V V V V V + +

    112 HTGSGSbA VVVVV =

    1GSX VV =

    out

    1

    2

    3

    4

    b

    DD

    122 THXGSAGSb VVVVVV ++=

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    Vb of Low voltage Cascode CM M1 at the edge of satu:

    Vout reaches the lowest level (headroom)

    min 4 2 1 4p b TH GS x TH THV V V V V V V = = +

    4 4 3 4 3GS TH x TH od od V V V V V V = + = +

    )( 112 THGSGSb VVVV +=

    out

    1

    2

    3

    4b

    DD

    How to generate Vb?

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    How to generate Vb?

    The left figure:

    I*R=VTH1

    VGS2=VGS5

    The right figure:

    We need big (W/L)7 for VGS7=VTH1

    VGS2=VGS5

    )( 112 THGSGSb VVVV +=

    Are the above result always correct?

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    General Advantages of MOS Current Sources

    Effective current gain

    No dc loading of slave stages on the master stage

    ( Unlike the BJT multi-stage current mirrors)Current ratioMOS channel geometric ratio

    Iout can be as small as several nA

    The ratio is not constant any more

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    Design Considerations

    Work with integer ratios and unit devices as much as possible.Using a unit device of size 1

    Keep mirror ratio (IOUT/IREF) reasonably small

    Typically no larger than 1020 Typically, we'll only have one single reference current

    generator on a chip

    Can generate/distribute currents across chip in two different

    ways Distribute gate voltage

    Can cause big problems due to IR drop

    Usually limited to local distribution

    Distribute currents Have one global bias cell close to reference that sends currents into local

    biasing sub-circuits

    Disadvantage: Consumes additional current

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    Class Exercise

    Ignore the outputvoltage of IREF

    All W/L, except M4:W/4L

    Please calculate :

    Iout And the min Vpand VDD

    2

    12

    34

    DD

    REF

    out

    5

    6

    A

    B

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    Thanks!