circuit design with vhdl-problem solutions.pdf

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Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, 2004

Circuit Design with VHDL

Volnei A. PedroniMIT Press Aug. 2004

Problem Solutions (*)(*) Details about the physical circuits, codes, and binary algebra can be found in reference [1] below.

[1] V. A. Pedroni, Digital Electronics and Design with VHDL, Elsevier, 2008.

Book website: http://textbooks.elsevier.com/9780123742704

Chapter 2: Code Structure

Problem 2.1: Multiplexer

Solution:

(Physical circuits and operation of multiplexers are described in chapter 11 of [1].)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -LI BRARY i eee;USE i eee. st d_l ogi c_1164. al l ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -ENTI TY mux I S

PORT ( a, b: I N STD_LOGI C_VECTOR(7 DOWNTO 0) ;sel : I N STD_LOGI C_VECTOR( 1 DOWNTO 0) ; c: OUT STD_LOGI C_VECTOR(7 DOWNTO 0) ) ;

END mux;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -ARCHI TECTURE exampl e OF mux I SBEGI N

PROCESS ( a, b, sel )BEGI N

I F ( sel ="00") THENc


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Chapter 3: Data Types

Problem 3.2: Dealing with data types

Solution:

Examples of data structures.

0 1 0 0 00 1 0 0 0

1 0 0 1 01 0 0 1 0

First, recall figure 3.1 (repeated above), which shows four types of data structures. From it, we conclude the

following for the signals listed in Problem 3.2:

a: a scalar of type BIT.

b: a scalar of type STD_LOGIC.

x: a 1D array (a vector) of type ARRAY1, whose 8 individual elements are of type STD_LOGIC.

y: a 2D array (a matrix) of type ARRAY2, whose 4x8=32 individual elements are of type STD_LOGIC.

w: a 1Dx1D array (another matrix) of type ARRAY3, whose 4 individual 8-element vectors are of typeARRAY1.

z: another 1D array (another vector) whose 8 individual elements are again of type STD_LOGIC.

Therefore:

a


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w(1) 0 ) , ( OTHERS=> 0 ) , 10000001) ;

ents above, thus requiring

y element (with GENERATE, for example).

=2**i ) THENresul t ( i ) : = ' 1' ;t emp : = t emp - 2**i ;

ELSEresul t ( i ) : = ' 0' ;

END I F;END LOOP;RETURN r esul t ;

END conv_st d_l ogi c;

BEGI Nout put


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c1 c2 c3 cn

x1 x2 x3 xn

y

x_input

c_input

y

m bits

2m bits

tap1 tap2 tap3 tapn

acc

Circuit diagram for Problem 12.4.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -LI BRARY i eee;USE i eee. st d_l ogi c_1164. al l ;USE i eee. st d_l ogi c_ari t h. al l ; - - package needed f or SI GNED- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -ENTI TY FI R I S

GENERI C ( n: I NTEGER : = 4; - - number of coef f i ci ent sm: I NTEGER : = 4) ; - - number of bi t s per coef f i ci ent

PORT ( cl k, r st : I N STD_LOGI C;l oad: STD_LOGI C; - - t o ent er new coef f i ci ent val ues

r un: STD_LOGI C; - - t o comput e t he out putx_i nput , coef _i nput : I N SI GNED( m- 1 DOWNTO 0) ;y: OUT SI GNED( 2*m- 1 DOWNTO 0) ;overf l ow: OUT STD_LOGI C) ;

END FI R;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -ARCHI TECTURE FI R OF FI R I S

TYPE i nternal _ar r ay I S ARRAY ( 1 TO n) OF SI GNED( m- 1 DOWNTO 0) ;SI GNAL c: i nt ernal _ar r ay; - - st or ed coef f i ci ent sSI GNAL x: i nt er nal _ar r ay; - - st or ed i nput val ues

BEGI NPROCESS ( cl k, r st )

VARI ABLE prod, acc: SI GNED( 2*m- 1 DOWNTO 0) : = ( OTHERS=>' 0' ) ;VARI ABLE si gn_pr od, si gn_acc: STD_LOGI C;

BEGI N

- - - - - Reset : - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -I F ( r st =' 1' ) THEN

FOR i I N 1 TO n LOOPFOR j I N m- 1 DOWNTO 0 LOOP

x( i ) ( j )


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END LOOP;I F (cl k' EVENT AND cl k=' 1' ) THEN

y

circuit design with vhdl-problem solutions.pdf

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