circuit design with alternative energy-efficient devices
DESCRIPTION
Circuit Design with Alternative Energy-Efficient Devices. Elad Alon Collaborators: Hei Kam, Fred Chen (MIT), Tsu-Jae King-Liu, Vladimir Stojanovic (MIT), Dejan Markovic (UCLA), Mark Horowitz (Stanford). Dept. of EECS, UC Berkeley. CMOS is Scaling, Power Can Not. 1000. - PowerPoint PPT PresentationTRANSCRIPT
Circuit Design with Alternative Energy-Efficient Devices
Elad Alon
Collaborators: Hei Kam, Fred Chen (MIT), Tsu-Jae King-Liu, Vladimir Stojanovic (MIT),
Dejan Markovic (UCLA), Mark Horowitz (Stanford)
Dept. of EECS, UC Berkeley
2
CMOS is Scaling, Power Can Not
S. Borkar, Intel
0.1
1
10
100
1000
1970 1975 1980 1985 1990 1995 2000 2005
Pow
er (W
)
4004
8008 8080
8086
8088
80286
386DX
486DXPentium
Pentium Pro
Pentium II
Pentium III Pentium 4Itanium
Itanium II Reality(Core 2)
Predictions(ca. 2000)
2010
3
Supply and Threshold Voltages
• kT/q doesn’t scale, so lowering Vth increases leakage• Fixed Vth, Vdd power density doesn’t scale well
Ed Nowak, IBM
Dra
in C
urre
nt I d
Gate Voltage Vg
Scaling Vth, Vdd
4
Alternative Devices to the Rescue?
Dra
in C
urre
nt I d
Gate Voltage Vg
Slope=S-1
MOSFET
New Device
• Many new devices withS-1<60mV/dec proposed
• But, many of these are slow (low Ion)– And/or have other “weird”
characteristics
• Can these devices reduce energy? If so, at what performance?– Need to look at the circuits
5
Outline
• Energy-Performance Analysis
• Circuit Design with Relays
• Conclusions
6
Processor Power Breakdown
• Most components track performance vs. energy curves of logic• Control, Datapath, Clock
• Use proxy circuit to examine tradeoffs
7
Proxy Circuit for Static Logic
Ld stages Switching activity factor = ,
Gate capacitance per stage = C
0V
Vdd
Input Output
Vdd
• tdelay = LdCVdd/(2Ion)• Edyn+Eleak = αLdCVdd
2 + LdIoffVddtdelay
8
Simple Optimization Rule
• Optimal Ion/Ioff Ld/α– Derived in CMOS– But holds for nearly
all switching devices
• Pleak/Pdyn ~constant– ~30-50% across wide
range of parameters
Nose and Sakurai
9
Using the Rule to Compare
• Match Ioff by adjusting “VT”• New device wins if:
Ion,new(Vdd) > Ion,MOS(Vdd)
Dra
in C
urre
nt I d
Gate Voltage Vg
MOSFET
“New Device” Ener
gy
Performance
Vddx
Vddx
MOSFET
“New Device”
10
What Else Matters: Variability
• Leakage: – E(Ioff) vs. E(Vth)
0.2 0.3 0.4 0.50
0.5
1
1.5
2
2.5
Vth
Rel
ativ
e Le
akag
e C
ontri
butio
n
Leakage
Vth
• Delay: – Finite Ld
– Cycle time set by worst-case
11
What Else Matters: Wires & Area
0V
Vdd
Input Output
Vdd
Cw
• Devices don’t drive just other devices
• Need to look at extrinsic cap (wires) too– Especially if device has area overhead
CwCw Cw
12
Parallelism
Ener
gyPerformance
MOSFET
“New Device”
• If available, parallelism allows slower devices– Extends energy benefit to higher performance
Serial: Perf. f
Parallel: Perf. 2f, E/op ~const
13
Minimum Energy
Lower Seff
Nor
mal
ized
Ene
rgy/
cycl
eVdd(V)
• At low performance or high parallelism: – Lowest Vdd for required Ion/Ioff wins
• Vdd,min Seff, Emin Seff2
Seff-1
Dra
in C
urre
nt I d
Gate Voltage Vg
14
Example: Tunneling FET
• Band-to-band tunneling device– Steep transition (<60mV/dec) at low current– Low Ion(<~100μA)
• Assume work function can be tuned
NP
Source DrainGate
Ion ≈A(Vgs+VT)exp[-B/(Vgs+VT)] [1]
Gate Voltage Vg (V)
Dra
in C
urre
nt I d
(A/
m)
[1]J. Chen et al., IEEE Electron Device Lett., vol. EDL-8, no. 11, pp. 515–517, Nov. 1987.
15
MOSFET
TFETEn
ergy
(J)
Performance (GHz)
30 stagesα=0.01
Energy-Performance Tradeoff
• Competitive with subthreshold CMOS• TFETs promising below ~100MHz
16
Outline
• Energy-Performance Analysis
• Circuit Design with Relays
• Conclusions
17
Nano-Electro-Mechanical Relay
• Based on mechanically making and breaking contact– No leakage, perfectly abrupt transition
• Reliability is the key challenge
Con
duct
ance
Gate Voltage Vg [V]
Gon
VpiVrl
18
Circuit Design with Relays
• CMOS delay set by electrical time constant– Distribute logical/electrical effort over many stages
• Relay: mechanical delay (~10ns) >> electrical (~1ps)– Implement logic as a single complex gate
CMOS: Relay:
19
MOSFETTFET
Ener
gy (J
)
Performance (GHz)
Relay Energy-Perf. Tradeoff
• Stack of 30 series relays
• No leakage– Vdd,min set only
by functionality(surface force)
• How about real logic circuits?
Relay
20
Relay-Based Adder• Manchester carry
chain
• Ripple carry– Cascade full adder
cells
• N-bit adder still 1 mechanical delay
21
Adder Energy-Delay• Compare vs. optimal
CMOS adder
• ~10-40x slower– Low Rcont not critical
• ~10-100x lower E/op– Lower Cg
– Fewer devices, all minimum size– Lower Vdd,min
22
Parallelism and Area
• If parallelism available, can trade area for throughput
• Competing with sub-threshold CMOS– Area-overhead bounded
23
Power Breakdown RevisitedPower Breakdown: core implemented in relays
3%5%
15%
77%
Control +DatapathMemory
Clock
I/O
Typical Power Breakdown for Embedded Processor
5%
25%
25%45%
Control +DatapathMemory
Clock
I/O
• Better logic “uncore” power dominant
• Need to analyze (and leverage) devices for entire system…– Relay DRAM or NVM (not SRAM)?– Relay ADC/DACs?
24
Outline• Simple Energy-Performance Analysis
• Circuit Design with Relays
• Conclusions
25
Summary• New devices need circuit level analysis• Ion/Ioff set by logic depth, activity factor• Don’t forget about variability, wires• Tailor circuit style to the device
• If available, parallelism may allow slower (low Ion) devices• Don’t forget about the rest of the system
26
Good News/Bad News• Parallelism still
available in CMOS• But eventually limited
by Emin
• Opportunity for new devices…• At least in sub-
100MHz applications
Today: Parallelism lowers E/op
Future: Parallelism doesn’t help
-1
27
Acknowledgements• Berkeley Wireless Research Center• NSF• DARPA• FCRP