#an alternative energy recovery clamp circuit

2828 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

An Alternative Energy Recovery Clamp Circuitfor Full-Bridge PWM Converters With Wide

Ranges of Input VoltageHonnyong Cha, Lihua Chen, Rongjun Ding, Qingsong Tang, and Fang Zheng Peng, Fellow, IEEE

Abstract—A full-bridge dc–dc converter employing a diode rec-tifier in the output experiences a severe voltage overshoot and os-cillation problem across the diode rectifier caused by interactionbetween junction capacitance of the rectifier diode and leakageinductance of the transformer. The pronounced reverse-recoverycurrent of high-power diodes significantly contributes to these is-sues by increasing power loss and voltage overshoot. Conventionalenergy recovery clamping circuits suffer from high voltage over-shoot if the converter input voltage is wide. In this paper, a novelenergy recovery clamp circuit is proposed to overcome this prob-lem. The proposed circuit requires neither active switches nor lossycomponents. Therefore, the proposed circuit is very promising inhigh-voltage and high-power applications. Performance of the pro-posed circuit is verified both theoretically and experimentally witha 70-kW dc–dc converter.

Index Terms—Diode rectifier, energy recovery, snubber circuit,voltage oscillation.

I. INTRODUCTION

FULL-BRIDGE pulsewidth-modulated (PWM) dc–dc con-verters have been widely used in high-power and high-

voltage dc–dc converters because they have several advantagesover resonant converters. However, a full-bridge dc–dc con-verter employing a diode rectifier in the output experiencessevere voltage overshoot and oscillation across the diode recti-fier because the rectifier diode is located between two currentsources, i.e., transformer leakage inductance and the output fil-ter inductor [1]–[3]. Therefore, it increases the diode voltagerating and cost, and causes EMI problems. As the output volt-age of the dc–dc converter increases, higher voltage diodes arerequired. However, the use of higher voltage diodes increasespower loss and voltage overshoot in the diodes because highervoltage diodes have poor recovery characteristics.

In order to reduce voltage spike in rectifier diodes, severaltechniques have previously been proposed. The conventionalmethod is the use of a resistor–capacitor–diode (RCD) snubbercircuit, as shown in Fig. 1(a) [1]. However, power loss in the

Manuscript received February 17, 2008; revised May 15, 2008. Current ver-sion published December 9, 2008. Recommended for publication by AssociateEditor Y.-F. Liu.

H. Cha, L. Chen and F. Z. Peng are with the Department of Electrical andComputer Engineering, Michigan State University, East Lansing, MI 48824USA (e-mail: [email protected]; [email protected]; [email protected]).

R. Ding and Q. Tang are with Zhuzhou Electric Locomotive ResearchInstitute (ZELRI), Zhuzhou 412001, China (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2008.2003131

Fig. 1. Conventional snubber circuits used in the PWM dc–dc converter.(a) RCD clamped snubber circuit. (b) Active-clamp circuit.

Fig. 2. DC–DC converter using energy recovery clamp circuit.

snubber resistor Rs is very high as the output power increases.As a result, it degrades system efficiency.

The active clamp method shown in Fig. 1(b) can solve theefficiency degradation problem and the voltage overshoot canbe clamped, but it increases system complexity and degradessystem reliability because an additional gate drive signal is re-quired to control switch Qs [2]. Therefore, it is not desirable inhigh-power applications, either.

To overcome the aforementioned problems, several energyrecovery clamp circuits (ERCCs) have been proposed recently[4]–[11]. Fig. 2 shows one example of an ERCC employed in

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CHA et al.: ALTERNATIVE ENERGY RECOVERY CLAMP CIRCUIT FOR FULL-BRIDGE PWM CONVERTERS 2829

Fig. 3. ERCC modified from the circuit proposed in [6].

a PWM dc–dc converter [6]. However, the voltage stress acrossrectifier diodes in Fig. 2 could be very high for PWM converterswith wide ranges of input voltage, especially when the duty cycleis less than 0.5. The converter circuit in [12] used a capacitorconnected in series with the transformer to eliminate the voltageoscillation problem in the secondary diode rectifier and showedgood performance. However, this method is also not desirablein high power applications due to the series connection of thebulky capacitor.

This paper proposes a novel ERCC that overcomes the draw-backs of the previously proposed circuit. The proposed circuitemploys a simple auxiliary circuit in which neither lossy com-ponents nor active switches are used. Therefore, the efficiencyand reliability of the dc–dc converter can be improved with thisproposed ERCC.

In Section II, several previous ERCCs are reviewed and theirassociated problems are pointed out in detail. In Section III,a novel ERCC is proposed and its principle operation is de-scribed in detail. The simulation and experimental results of theproposed ERCC is shown in Section IV. Performance of theproposed ERCC is verified by applying it to a 70-kW PWMdc–dc converter.

II. REVIEW OF PREVIOUSLY PROPOSED ERCC

Fig. 3(a) shows an ERCC modified from the circuit shownin Fig. 2. To achieve high output voltage, the transformer sec-ondary winding is split into two windings. Two rectifier bridgesare used and their outputs are connected in series. With thisconfiguration, each bridge needs to sustain only one-half of theoutput voltage. In this paper, the transformer turns number isset to 6:7:7 (Np :Ns1 :Ns2) by considering the duty cycle losscaused by transformer leakage inductance Llk and others. Llk

is the transformer leakage inductance reflected to the secondaryside of the transformer. The operation of this circuit is the sameas the one shown in Fig. 2. Fig. 3(b) depicts the peak voltageacross the rectifier diodes, Vrec pk , without considering diodereverse recovery current and with the assumption that snubbercapacitors Cs1 and Cs2 are much bigger than diode junction ca-pacitance Cj . With this assumption, Vrec pk can be expressed [6]

Vrec pk = 2(Vsec −

Vo

2

)+

Vo

2= 2Vsec −

Vo

2= (2 − D)Vsec

(1)where Vin is the input voltage of the dc–dc converter, n isthe transformer turns ratio [n = (Ns1/Np) = (Ns2/Np)], Vsec



Fig. 4. ERCC modified from the circuit proposed in [8] with the insertion of snubber resistors.

is voltage in the transformer secondary winding (=nVin), Vo isoutput voltage, and D is the duty cycle of the converter (=(1/2)(Vo/Vsec)). Fig. 3(c) shows the Vrec pk as D changes. In thispaper, Vin changes from 333 to 666 V and Vo is regulated to750 V. With this input voltage range, the minimum duty cyclecan be determined as

Dmin =Vo/2Vsec

=750/2

7/6 × 666≈ 0.483. (2)

From (1) and (2), Vrec pk can be calculated as

Vrec pk = (2 − D)Vsec = (2 − 0.483) × 76× 666 = 1180 V.

(3)Considering the reverse recovery current in the rectifier

diodes, the voltage stress in diodes would be easily higher than1200 V. Thus, we cannot use standard 1200 V diodes in this case.The use of higher voltage diodes increases power loss and volt-age overshoot across diodes because higher voltage diodes havepoor recovery characteristics. Therefore, the ERCC shown inFig. 3(a) is not applicable to the system described in this paper,although it has the advantages of resetting circulating currentin the primary side and achieves zero-voltage and zero-currentswitching (ZVZCS) in switching devices using the phase shiftPWM control method [6].

Fig. 4 shows another example of an ERCC modified from thecircuit shown in [8]. The circuit in [8] works only when Vsecis less than Vo (i.e., D > 0.5) and the Vrec pk is clamped toVo . However, when Vsec is higher than Vo (i.e., D < 0.5), thiscircuit does not work because a huge current will flow throughsnubber diodes, Ds1 and Ds2 , eventually destroying them. Onepossible way is to insert additional snubber resistors Rs1 andRs2 , as shown in the dashed box in Fig. 4. By inserting Rs1and Rs2 in the discharging path of snubber capacitors Cs1 andCs2 , a portion of energy stored in Llk is dissipated in Rs1 andRs2 , and the rest of the energy can be transferred to the output

capacitor. The total power loss in Rs1 and Rs2 is calculated as

P =PRs1 + PRs2 = 2(Vrec pk −Vo)2

Rs= 2

(Vrec pk − 2DVsec)2

Rs(4)

where Rs = Rs1 = Rs2 .Compared with conventional RCD snubber circuits, such as

the one shown in Fig. 1(a), the power loss in Rs1 and Rs2 ofFig. 4 can be reduced significantly because the voltage acrossRs1 and Rs2 can be reduced a lot. The power losses in Rs1and Rs2 , however, are not negligible when D varies in a widerange. Therefore, the ERCC shown in Fig. 4 also suffers fromthe efficiency degradation problem and is not applicable in thesystem discussed in this paper.

III. PRINCIPLE OPERATION OF THE PROPOSED ERCC

The two snubber circuits discussed in Figs. 3 and 4 have somelimitations and are not desirable for systems with wide rangesof input voltage, especially when D < 0.5. Fig. 5 shows theERCC proposed in this paper. The transformer secondary cur-rent ILl k

(t) and diode voltage Vrec(t) waveforms are sketchedin Fig. 6. The output filter inductor Lo is assumed big enough,and thus Io can be modeled as constant. To control the outputvoltage, either duty cycle control or phase shift PWM controlcan be used. In this paper, the duty cycle control method is used.The operational modes of the proposed ERCC are explainedas follows and are shown in Fig. 7. For the sake of simplicity,only the diode rectifier located at the bottom is considered andanalyzed because the top and bottom rectifiers operate in thesame manner.

Mode 1 (∼to): S1 − S4 turned off and rectifier diodes are infreewheeling period. Vsec remains zero. D1 − D4 are ON andeach diode carries Io/2.

Mode 2 (to − t1): S1 and S4 turn on. Vsec changes from zeroto nVin and transformer secondary current builds up linearlywith the slope of nVin/Llk until it reaches Io . The current



Fig. 5. Configuration of the proposed ERCC.

Fig. 6. Key waveforms of the proposed ERCC.

in D1 and D4 increases, while the current in D2 and D3decreases in this mode.

Mode 3 (t1 − t2): Reverse recovery period of D2 and D3 .The current in D1 and D4 builds up with the same slopeof nVin/Llk until D2 and D3 turn off at t2 . At t = t2 , thecurrent in Llk becomes Io + 2Irr , where Irr is the reverserecovery current of the rectifier diode. Until this mode, Vrecremains zero because D2 and D3 are still ON (conducting).

Mode 4 (t2 − t3): D2 and D3 snap off at t2 and its junctioncapacitors Cj start resonance with Llk . During this mode, Vrecand ILl k

are expressed as follows with the initial conditionsVrec(0) = 0, ILl k

(0) = Io + 2Irr :

Vrec(t) =nVin [1 − cos(wot)] + (IRZc) sin(wot) (5)

ILl k(t) =Io +

nVin

Zcsin(wot) + IR cos(wot) (6)

where Zc =√

Llk/2Cj , wo = 1/√

Llk2Cj , IR = 2Irr

Mode 5 (t3 − t4): When Vrec reaches Vo at t3 , Ds1 starts con-ducting and there is another resonance between Cs1 and Llk .Because Cs1 is much bigger than Cj , the current flowingthrough Cj can be ignored in this mode analysis. Cs11 isadded to minimize circuit stray inductance in the snubberpath Cs1 − Ds1 − Cs11 , and can be assumed large enoughbecause it is connected in parallel with the output capacitor.During this mode, Vrec and ILl k

are expressed as (7) and (8)with the initial conditions Vrec(0) = Vo , ILl k

(0) = Ip . Ip isthe current at t = t3 and can be calculated from (5) and (6)

Vrec(t) = Vo + (nVin − Vo) [1 − cos(wdt)]

+Zd

Zc

√(IRZc)2 + 2nVinVo − V 2

o sin(wdt) (7)

ILl k(t) = Io +

nVin − Vo

Zdsin(wdt)

+

√(IRZc)2 + 2nVinVo − V 2

o

Zccos(wdt) (8)

where Zc =√

Llk/2Cj , Zd =√

Llk/Cs1 , and wd =1/√

LlkCs1 . At t = t4 , Vrec(t) reaches its peak value Vrec pkbecause ILl k

(t) becomes equal to Io at this point. From (7)and (8), Vrec pk can be derived as

Vrec pk = nVin

+√

(nVin−Vo)2 +Llk

Cs1I2R +

2Cj

Cs1(2nVinVo−V 2

o ).

(9)

Vo can be expressed as

Vo = 2 × D × nVin . (10)



Fig. 7. Operational mode analysis of the proposed ERCC.



Fig. 8. Comparison of Vrec pk as a function of D.

Substituting (10) into (9) yields

Vrec pk = nVin

+√

[nVin(1 − 2D)]2 +Llk

Cs1I2R +

2Cj

Cs1(nVin)24D(1 − D).

(11)

Mode 6 (t4 − t5): When ILl kis equal to Io at t4 , Ds1 stops

conducting and there is a resonance between Llk and Cj .This resonance is similar to that of mode 4. During this mode,Vrec and ILl k

starts decaying with oscillation, and finally,converges to nVin and Io , respectively. The voltage in Cs1 iskept constant to VCS 1 during this mode.

Mode 7 (t5 − t6): S1 and S4 turn off at t5 . ILl kand Vrec start

decreasing.Mode 8 (t6 − t7): Vrec is equal to VCS 1 at t6 and Dh1 starts

conducting at this point. Cs1 can be discharged through Dh1and supplies a portion of the load current Io . VCS 1 is fullydischarged at t7 and D1 − D4 turn on and start freewheelingafter t7 .

The operational mode analysis shown before is appliedto the condition D < 0.5 (i.e., Vsec > Vo ). For D > 0.5,Vrec pk(=VCs 1 + Vo) is almost equal to Vo because the cur-rent in the transformer leakage inductance is not sufficient tocharge Cs1 . From the results mentioned earlier, Vrec pk can beexpressed as (12) and (13) for D < 0.5 and D > 0.5, respec-tively. It should be pointed out that reverse recovery current ofthe rectifier diode is not included in (12) and (13) for the sakeof simplicity

Vrec pk = 2(Vsec −Vo)+ Vo = 2(1−D)Vsec(D < 0.5) (12)

Vrec pk ≈ Vo = 2 × Vo

2= 2DVsec(D > 0.5). (13)

Using (12) and (13), Vrec pk of the proposed ERCC is plottedin Fig. 8 as a function of D with Vsec and Vo . Vrec pk in Fig. 3(a)is plotted again for comparison with the proposed ERCC. Asshown in Fig. 8, Vrec pk is clearly reduced by using the proposedERCC within the duty cycle range of 0 < D < (2/3). WhenD = 0.5, for example, Vrec pk of the proposed ERCC is Vsec(or Vo ) while Vrec pk of Fig. 3(a) is 1.5 × Vsec (or 1.5 × Vo ).

Thus, there is a 50% reduction in Vrec pk by using the proposedERCC, which enables the use of low-voltage diodes and leads tohigher efficiency of the dc–dc converter. Although the proposedERCC has higher voltage spike when D > (2/3), it does notdegrade the performance of the proposed ERCC because thediode voltage rating is determined with maximum input voltageor minimum duty cycle of the converter. In other words, theincreased voltage spike when D > (2/3) is still within the rangeof the diode voltage rating.

IV. SIMULATION AND EXPERIMENTAL RESULTS

A 70-kW prototype dc–dc converter employing the proposedERCC has been built and tested to verify the principle of op-eration and is compared with simulation results. Table I showsoperational conditions and circuit parameters of the dc–dc con-verter developed in this paper. In this paper, the two output in-ductors, Lo , are coupled together to minimize inductor size. Theinterleaved winding method is used in the transformer windingto minimize leakage inductance and copper loss.

Fig. 9 shows the simulation results of the dc–dc converterwhen D = 0.483 and 0.8, respectively. The simulation wave-forms shown in Fig. 9 are consistent with theoretical onesshown in Fig. 6. When D > 0.5, Vrec pk is almost clampedto Vo as expected because the current in Llk is not sufficientto charge snubber capacitors Cs1 and Cs2 . Fig. 10(a) showsVrec measured without snubber circuits under the test condi-tions of Vin = 328 V, Vo = 374 V, and Po = 14 kW. Withoutthe snubber circuits, Vrec pk was increased to 1100 V whentransformer secondary voltage Vsec was 328 × (7/6) ≈ 383 V.Vrec pk was almost 2.9 times that of Vsec because the re-verse recovery currents of the rectifier diodes contribute sig-nificantly to this voltage overshoot. Fig. 10(b) shows Vrec mea-sured with the proposed ERCC under the same test conditionsmentioned before. As shown in Fig. 10(b), Vrec pk was wellclamped to almost 1.3 times that of Vsec with the proposedERCC.

Fig. 11(a) shows the experimental waveforms of the trans-former primary current and Vrec using the proposed ERCC un-der the worst case conditions of Vin = 666 V, Vo = 750 V,D = 0.483, and Po = 70 kW. Due to the physical layout of thesecondary busbar, the transformer primary current is measuredinstead of the secondary. Fig. 11(b) shows the expanded wave-forms of Fig. 11(a). Vrec pk is effectively clamped to almost1000 V. The current and voltage waveforms in Fig. 11(b) arecompatible to those of theoretical waveforms shown in Fig. 6and simulation waveforms shown in Fig. 9(a).

Fig. 12 shows the experimental waveforms of the transformerprimary current and Vrec using the proposed ERCC under thetest conditions of Vin = 400 V, Vo = 750 V, D = 0.8, andPo = 70 kW. Vrec pk is almost clamped to Vo as expected andis close to the simulation results shown in Fig. 9(b).

Fig. 13 shows the zoom in waveforms of transformer primarycurrent and Vrec when Vin = 600V, Vo = 670V, D = 0.48, andPo = 50kW to compare the performance of the proposed ERCCwith the ERCC in Fig. 3(a). As shown in Fig. 13, Vrec pk wasdecreased from 1060 to 850 V with the proposed ERCC, which



TABLE IOPERATIONAL CONDITIONS AND CIRCUIT PARAMETERS OF DC–DC CONVERTER

Fig. 9. Simulation waveforms of dc–dc converter with the proposed ERCC. (a) D = 0.483. (b) D = 0.8.

Fig. 10. Experimental waveforms measured with and without snubber circuit. (a) Without snubber circuit. (b) With proposed ERCC.



Fig. 11. Experimental waveforms using proposed ERCC when D = 0.483. Transformer primary current (top) and Vrec (bottom). (a) Waveforms with proposedERCC. (b) Zoom-in waveforms of (a).

Fig. 12. Experimental waveforms using the proposed ERCC when D = 0.8. Transformer primary current (top) and Vrec (bottom). (a) Waveforms with theproposed ERCC. (b) Zoom-in waveforms of (a).

Fig. 13. Comparison of the proposed ERCC with Fig. 3(a). (a) ERCC in Fig. 3(a). (b) Proposed ERCC.



Fig. 14. Measured and theoretical results of Vrec pk versus Cs1 .

Fig. 15. Comparison of efficiency.

is almost a 30% reduction in Vrec pk . In addition to voltagereduction in Vrec pk , the peak current in the transformer primary(secondary) winding was increased with the ERCC in Fig. 3(a)because snubber capacitors Cs1 and Cs2 start charging whenVrec reaches Vo/2 instead of Vo . Therefore, it will increaseconduction loss in the transformer and insulated gate bipolartransistor (IGBT) that results in the decrease of system efficiency(see Fig. 15).

Fig. 14 shows the measured Vrec pk as Cs1 (or Cs2) changesfrom 10 to 600 nF under the test conditions of Vin = 450 V,Vo = 510 V, and Io = 55 A. The measured Vrec pk is com-pared with the theoretical results plotted using (11). The mea-sured Vrec pk is very close to the theoretical value. Vrec pk is in-versely proportional to snubber capacitance Cs1 . In this paper, a100-nF capacitor is selected for Cs1 and Cs2 because a largerthan necessary capacitor will increase current in the transformerand IGBT. Therefore, converter efficiency will be decreased.

Fig. 15 shows the measured efficiency of dc–dc converterusing the proposed ERCC and is compared with the efficiencymeasured in Fig. 3(a). The efficiency of the proposed converter

was almost the same as in Fig. 3(a) when Vin is low and slightlyimproved as Vin moves toward maximum value as expected. Inthe test, a digital power meter (YOKOGAWA, WT1600) wasused to measure the input and output power, and the outputpower was 50 kW.

V. CONCLUSION

This paper introduced a novel ERCC for PWM dc–dc con-verters with wide ranges of input voltage. The limitations anddrawbacks of previously proposed ERCCs have been pointedout. Detailed analysis has been presented, and performance ofthe proposed ERCC was compared with previously proposedERCCs. A 70-kW prototype dc–dc converter employing theproposed ERCC has been built and tested to verify the principleof operation. The proposed ERCC consists of two small capac-itors and two diodes in each bridge. Neither lossy componentsnor additional active switches are used to clamp diode voltage.Therefore, the efficiency and reliability of the dc–dc convertercan be improved by using the proposed ERCC. The proposedERCC is very promising for high-voltage and high-power dc–dcconverters with wide ranges of input voltage.

REFERENCES

[1] L. H. Mweene, C. A. Wright, and M. F. Schlecht, “A 1 kW 500 kHzfront-end converter for a distributed power supply system,” IEEE Trans.Power Electron., vol. 6, no. 3, pp. 398–407, Jul. 1991.

[2] J. A. Sabate, V. Vlatkovic, R. B. Ridley, and F. C. Lee, “High-voltage, high-power, ZVS, full-bridge PWM converter employing an active snubber,”in Proc. IEEE APEC, 1991, pp. 158–163.

[3] S. Lin and C. Chen, “Analysis and design for RCD clamped snubber usedin output rectifier of phase-shift full bridge-bridge ZVS converters,” IEEETrans. Ind. Electron., vol. 45, no. 2, pp. 358–359, Apr. 1998.

[4] E. S. Kim, K. Y. Joe, M. H. Kye, Y. H. Kim, and B. D. Yoon, “Animproved soft switching PWM FB dc/dc converter for reducing conductionlosses,” IEEE Trans. Power Electron., vol. 14, no. 2, pp. 258–264, Mar.1999.

[5] J. G. Cho, J. W. Baek, D. W. Yoo, H. S. Lee, and G. H. Rim, “Novelzero-voltage and zero-current-switching (ZVZCS) full bridge PWM con-verter using transformer auxiliary winding,” IEEE Trans. Power Electron.,vol. 15, pp. 250–257, Mar. 2000.

[6] J. G. Cho, J. W. Baek, C. Y. Jeong, and G. H. Rim, “Novel zero-voltageand zero-current-switching (ZVZCS) full bridge PWM converter using asimple auxiliary circuit,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 15–20,Jan./Feb. 1999.

[7] E. S. Kim and Y. H. Kim, “A ZVZCS PWM FB dc/dc converter using amodified energy-recovery snubber,” IEEE Trans. Ind. Electron., vol. 49,no. 5, pp. 1120–1127, Oct. 2002.

[8] A. Bendre, S. Norris, D. Divan, I. Wallace, and R. W. Gascoigne, “Newhigh power dc–dc converter with loss limited switching and lossless sec-ondary clamp,” IEEE Trans. Power Electron., vol. 18, no. 4, pp. 1020–1027, Jul. 2003.

[9] T. T. Song, N. Huang, and A. Ioinovici, “A family of zero-voltage and zero-current-switching (ZVZCS) three-level dc–dc converters with secondary-assisted regenerative passive snubber,” IEEE Trans. Circuits Syst., vol. 52,no. 11, pp. 2473–2481, Nov. 2005.

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Honnyong Cha received the B.S. and M.S. de-grees in electrical engineering from Kyungpook Na-tional University, Taegu, Korea, in 1999 and 2001,respectively. He is currently working toward thePh.D. degree at Michigan State University, EastLansing.

From 2001 to 2003, he was a Research Engineerwith Power System Technology (PSTEK) Company,An-san, Korea, where he was involved with the de-velopment of power electronics application systems.His current research interests include dc–dc convert-

ers, dc–ac inverters, and hybrid vehicles.

Lihua Chen received the B.S. and M.S. degrees inelectrical engineering from Changchun University ofScience and Technology, Changchun, China, in 1993and 1996, respectively. He is currently working to-ward the Ph.D. degree at the Department of Electricaland Computer Engineering, Michigan State Univer-sity, East Lansing.

From 1996 to 1999, he was an Assistant Profes-sor with Changchun University of Science and Tech-nology. From 1999 to 2002, he was with ArgonneNational Laboratory, Argonne, IL, as a Visiting Sci-

entist. His current research interests include high-power converters and invert-ers, intelligent gate drives, and high-temperature superconductors and theirapplications.

Rongjun Ding was born in Jiangsu Province, China,in 1961. He received the B.S. degree in electri-cal engineering from Southwest Jiaotong University,Sichuan, China, in 1984, and the M.S. degree in elec-trical engineering from the Central South University,Changsha, China, in 1998.

He is currently a Professor with Zhuzhou ElectricLocomotive Research Institute (ZELRI), Zhuzhou,China. Since 1988, he has been engaged in the re-search of ac dive systems for electric locomotives,especially in control technology and converter design.

Qingsong Tang was born in HuBei Province, China,in 1974. He received the B.S. and M.S. degrees inelectrical engineering from Beijing Jiaotong Univer-sity, Beijing, China, in 1997 and 2007, respectively.

He is currently a Research Engineer with ZhuzhouElectric Locomotive Research Institute (ZELRI),Zhuzhou, China. Since January 2006, he has beena Visiting Scholar at Michigan State University, EastLansing. His current research interests include powerconverter circuits, especially in soft-switching tech-nology, motor drives, and DSP-based power electron-

ics control systems.

Fang Zheng Peng (M’92–SM’96–F’05) receivedthe B.S. degree in electrical engineering from WuhanUniversity, Wuhan, China, in 1983, and the M.S. andPh.D. degrees in electrical engineering from NagaokaUniversity of Technology, Nagaoka, Japan, in 1987and 1990, respectively.

From 1990 to 1992, he was a Research Scientistwith Toyo Electric Manufacturing Company, Ltd.,where he was engaged in research and development ofactive power filters, flexible ac transmission systems(FACTS) applications, and motor drives. From 1992

to 1994, he was with Tokyo Institute of Technology, Tokyo, Japan, as a ResearchAssistant Professor, where he initiated a multilevel inverter program for FACTSapplications and a speed-sensorless vector control project. From 1994 to 2000,he was with Oak Ridge National Laboratory (ORNL), from 1994 to 1997, hewas a Research Assistant Professor at the University of Tennessee, Knoxville,where he was also a staff member, and from 1997 to 2000, he was the Lead(principal) Scientist of the Power Electronics and Electric Machinery ResearchCenter, ORNL. In 2000, he joined Michigan State University, East Lansing, asan Associate Professor, and he is currently a Professor in the Department ofElectrical and Computer Engineering. He is the holder of more than ten patents.

Dr. Peng was the recipient of the 1996 First Prize Paper Award and the 1995Second Prize Paper Award of the Industrial Power Converter Committee in theIEEE/Industrial Application Society (IAS) Annual Meeting, the 1996 AdvancedTechnology Award of the Inventors Clubs of America, Inc., the InternationalHall of Fame, the 1991 First Prize Paper Award in the IEEE TRANSACTIONS ON

INDUSTRY APPLICATIONS, and the 1990 Best Paper Award in the Transactions ofthe Institute of Electrical Engineers of Japan (the Promotion Award of ElectricalAcademy). He was an Associate Editor for the IEEE TRANSACTIONS ON POWER

ELECTRONICS from 1997 to 2001, and again since 2005. He was the Chair of theTechnical Committee for Rectifiers and Inverters of the IEEE Power ElectronicsSociety from 2001 to 2005.


#an alternative energy recovery clamp circuit

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