cin2_lecon6
TRANSCRIPT
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HW
SW
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2
2
!
2
2
5
2
2
2
"#$%&$#$'(
Intuitive architecture for N x M memoryToo many select signals:
N words == N select signals
Decoder reduces the number of select signals
"#$%&$#$'(
)
!" # #
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! " ##!!"" ####
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WL
BL
WL
BL
1WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
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WL [0]
VDD
BL [0]
WL [1]
WL [2]
WL [3]
Vbias
BL [1]
Pull-down loads
BL [2] BL [3]
VDD
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! !
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
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! !
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5 x 7)
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! !
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11 x 7)
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Electrically Erasable Programmable Read-Only Memory
Gate
floating gateThe application of a potential on the upper gatecauses the transfer of charges from the channel
trough the thin oxyde layer, which charges thefloating gate.Oxyde layer
S D
G
N+
Silicon oxyde
Polysilicon
level 1
Vcc
G
Floating gate
Bit output
Word selection
Polysiliconlevel 2
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x0 x1 x2
AND
plane
x0 x1
x2
Product terms
OR
plane
f0 f1
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"#"#$ $
Inverting format (NOR-NOR) more effective
Every logic function can beexpressed in sum-of-products
format (AND-OR)
minterm
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%%
*
=
= +
= + +
*
*
*
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& &
PLA PROM PAL
I5 I4
O0
I3 I2 I1 I0
O1O2O3
Programmable AND array
ProgrammableOR array I5 I4
O0
I3 I2 I1 I0
O1O2O3
Programmable AND array
Fixed OR array
Indicates programmable connection
Indicates fixed connection
O0
I3 I2 I1 I0
O1O2O3
Fixed AND array
ProgrammableOR array
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f0
1 X2 X1 X0
f1NANA
: programmed node
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$ $ Programmable Logic Arraystructured approach to random logictwo level logic implementation
NOR-NOR (product of sums)NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main differenceROM: fully populatedPLA: one element per minterm
Note: Importance of PLAs has drastically reduced1. slow2. better software techniques (mutli-level logic
synthesis)
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AND-plane OR-plane
Pseudo-NMOS PLA
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!" #$$#%" &" !" #$$#%" !" #$$#%" &"&"
&&+, ,+)-) -&-*.//./,-"01//+, 1+/ /1./ &" '1"*./( &1-/%-&-*./ '-/&+"1-,"&+(
!!"# "# $!%"%&"#2 / $ 3$ '# $ ( 3$ #$4 5 66 678 -/.","&+ )/&+,"&+ *&&.//++/ &1 &-/ )91+/ &/
."",// )/ &+&/ '. .) /.)888( &1 )91+-//1 )/ /..1./ '(
%"$!"# " ''%!2 1"*./'/,.( +,"1"*./ '",/ &(
,-+",&- & -"../ .&,+,/ '/.)( -,,"01/ '%-!"
# $ %
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''()(" *&+ ,()(" *&+ ,
'( ))*'($" "" * + ( )( "
-,. ( '( ( )()( * '*
$,- $+./ $"$
* + ( )( " " %0 ''( )1( )()( * '* 2*( )3'( 4'3(!
,%3 5' 6./ ' 3 ( ( ' )( 37*'**-*
8# 4* + ( )( ! 8 %5 -,.
8 2*( 3)*3*'( 3 7'*
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ProgrammableProgrammable LogicLogicDeviceDeviceFamiliesFamiliesSource: Dataquest
Logic
StandardLogic
ASIC
ProgrammableLogic Devices
(PLDs)
GateArrays
Cell-BasedICs
Full CustomICs
CPLDsSPLDs(PALs) FPGAs
AcronymsSPLD = Simple Prog. Logic DevicePAL = Prog. Array of LogicCPLD = Complex PLD
FPGA = Field Prog. Gate Array
Common ResourcesConfigurable Logic Blocks (CLB)
Memory Look-Up Table AND-OR planes
Simple gatesInput / Output Blocks (IOB) Bidirectional, latches, inverters
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! "# $ %
& '( ) *
& ! $ ) "*
& )$" $ *
+ " )"# ,-* . )- /'*
+ 0 1 "2 $
" 3 " )*
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FPGA Design Flow :FPGA Design Flow : ExampleExample
XC4000XC4000XC4000
Design entry and synthesis in schematicand/or text.
Download directly to the hardware device(s)
with unlimited reconfigurations
1
Implementation includes Map, Place, Route, andbitstream generation using Xilinxsoftware. Also,analyze timing, view layout, and more.
2
3
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/*/* %5 $ #
$ $
*2'* 9* *: 4%5!;5 $
$ $ % $
$% $
#
((') 3 +( *
%< # # $ 5$
% "
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Programming technologies
One time programming
Bit
FuseVcc
Mtal 1
Mtal 2
Dielectric
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!"
! 4 5(6 ". $ . !
1! ) 5(6*
! 1 # ) +1+* 7 "$" )1! "2 2 8*
# $
! " # ! $% &
% & % '
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Bit
Vcc
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!" (%
/ 1
4 1
"$# " 4 $ .2 #
19 2 #" " :#" "$ " 19 "#$ 4 ;!#"9
% 5 : 3$ /-&% ; $
% # '66 # 1< $ 3$(
G
S
D
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/ /
+= +=
# ((
'% '( '
)$
4%$%
::
$ ? : $ 6 : : 6 # !?
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DS
Floating gate
Source
Substrate
Gate
Drain
n+ n+_p
toxtox
Device cross-section
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"" 00,,11
*' 2( > *3*('
)'* 37* ' ' *'3- *( 3 )'/
'* 3)2*'+
1( 3 ) ( '" ( )'( 3
2'* ()*'( 2*( )'( ()( ? '*9 : 4*('* 3 (2 ' 3( 22'( !
Mtal 1
Mtal 2
Dielectric
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//& /*& /*
antifuse polysilicon ONO dielectric
n+ antifuse diffusion
2 l
From Smith97
Open by default, closed by applying current pulse
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8 &'(!!)" # (**
8 '( 3 '*(((* '-( *3)( 3( (
8 ( )( ''*' 3 *2 (*'**-*( ' 3 ( (
8 %5 3' @' *2) ? ( (( '*(*
? ' 37* ) -'* 4!
/-&
)*#'
)
/-&
)
/-&
/-&@
)
'' ((/'/'++5'65'6))
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22
$
9$#$
*
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+4 +4 2244
*
8*
=* A = A8*
*
*
A
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&
#=
= =
$ #
$ )
B
) 0
0
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66
WL
BL
VDD
M5
M6
M4
M1
M2
M3
BL
QQ
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6"6" 77
VDD
GND
QQ
WL
BLBL
M1 M3
M4M2
M5 M6
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4848334 9 $ '4 9 $ '
@
33 , ,
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33 , $ 4 , $ 4
*
*
A
%)! *
' < =
> > > ?> > ? >> ? > ?> ? ? ?? > > ?? > ? ?? ? > ?? ? ? >
@ 0 ! A
#
+
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-
-
-
.
* B6( C
-
/
/ C ?
/ C >
D8E D * E
D=E AD * D
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0000
0001
0010
0011
0100
0101 0110
0111
1000
1001
1010
1011 1100
1101
1110
1111
Inputs
0 Output
Lookup table principle (LUT)
A four-input lookup table: LUT 4
Memory adresses Memory Bits
2n possible combinational functions
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Lookup table principle (LUT)
LUT realization : Tree of Muxes
A B C
S
0
01
00
00
0
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
A B C
S
0
0
1
0
0
0
0
0
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A B C
S
0
11
10
10
1
MUXAAAAABAA
AABA
BBBA
AAAB
BBAB
AABB
BBBB
+
#", > C
SRAM cells
Lookup table principle (LUT)
LUT realization example
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:: %%
*
=
= +
= + +
** +#+# #$#$
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** +#+##$#$
# $ $ %5# # $# $ ,. C # # 3 7 5 %5# -.!(/")0 !)"& +!&1234*('' ? ' 37* 3 (( )*)'( 3 2*'*( 4#> ,D# .! #* ,#. (*3 ? * 3 '-( **') ? 3(*'( )( 4!
# $ E $ #
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!:F
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CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Reconf. block I/O blockArrays of reconfigurable blocks (CLB) connected by
Programmables interconnections (switch matrix)
The block architecture differs from vendors,but is always LUT-based.
FPGAs : Field Programmable Gate Arrays
Reconfigurable technology : FPGAs
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Basic idea: two-dimensional array of logic blocks and flip-flops with a meansfor the user to configure:
1. the interconnection between the logic blocks,
2. the function of each block.
Reconfigurable technology : FPGAs
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
FPGAs : Reconfigurability
Switch Matrix
Reconfigurable technology : FPGAs
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Basic idea: two-dimensional array of logic blocks and flip-flops with a meansfor the user to configure:
1. the interconnection between the logic blocks,
2. the function of each block.
Reconfigurable technology : FPGAs
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
FPGAs : Reconfigurability
4-LUT FF1
0
latchLogic Block
set by configurationbit-stream
4-input "look up table"
OUTPUT
INPUTS
Programmablel i bl k
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logic blocks
Programmableinterconnect
!+$ 1!
+ ++ + +
+
+ +
+ +
+
+ +
+ +
+
+
+
+ +
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"" /0+ /0+1+ %#2 %)!23331+ %#2 %)!2333
0)
-
&%
< C
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&% , $#F$ 2
/0+ 1+
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/0+1+ 4
%%#
4
4
1+
/ /0+1+
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56/
&' " &' "
/
#
/ /0+ 1+
!"# "$!%
& ' ( "$!)* / G &+ H 4
6 $ $ 6$
56/
(
&'
(
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Reconfiguration de FPGA-SRAM
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conf1
conf2
conf3
conf4
SRAM SRAM SRAM
SRAM SRAM SRAM
SRAM SRAM SRAM
Couche OPERATIVECouche OPERATIVE
Couche de CONFIGURATIONCouche de CONFIGURATION
Chargement squentiel de plusieurs architectures
Une architecture par application
Chargement squentiel de plusieurs architectures Plusieurs architectures par application
Chargement continu
Larchitecture volue en cours de traitement
56/
56/
" "
/
&
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&
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Switch Box
Connect Box
InterconnectPoint
Courtesy Dehon and Wawrzyniek
" ( , " ( ,
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" ( , " ( ,
Courtesy Dehon and Wawrzyniek
= !#5= !#5
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= !#5= !#5
Use overlayed meshto support longer connections
Reduced fanout and reduced
resistance
Courtesy Dehon and Wawrzyniek
4 784
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4
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* (F'(
*D* 'F F(*'(
F'- (G 3*3(* ' (G *3 * 2(F'(
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6 *'8 ,
8
!
"## !"##$!
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6 *'8 ,
8
!
"## !"##$!
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Exemple : XC4000 ArchitectureExemple : XC4000 Architecture
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Exemple : XC4000 ArchitectureExemple : XC4000 Architecture
.*
.*
.*
.*
!:
F
Programmable
Interconnect I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
Pad
D Q
SD
RD
EC
S/R
Control
D Q
SD
RD
EC
S/R
Control
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
XC4000 Configurable Logic Blocks
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XC4000 ConfigurableXC4000 Configurable
LogicLogic
BlocksBlocks
D QSD
RD
EC
S/RControl
D Q
SD
RD
EC
S/RControl
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
HFunc.
Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
YQ
Y
XQ
X
H1 DIN S/R EC 2 Four-input function
generators (Look UpTables)
2 Registers : Each can beconfigured as Flip Flop orLatch
Look Up Tables (LUT)Look Up Tables (LUT)
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p ( )p ( )
Capacity is limited by number ofinputs, not complexity
Choose to use each functiongenerator as 4 input logic (LUT) or as
high speed sync.dual port RAM
Combinatorial Logic is stored in 16x1 SRAM Look Up Tables(LUTs) in a CLB
Example:
A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 1
0 1 0 0 10 1 0 1 1
. . .1 1 0 0 01 1 0 1 0
1 1 1 0 01 1 1 1 1
Look Up Table
Combinatorial Logic
AB
CD
Z
4-bit address
GFunc.Gen.
G4
G3G2G1
WE
2(2 )4
= 64K !
XC4000E I/O BlockXC4000E I/O Block DiagramDiagram
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XC4000E I/O BlockXC4000E I/O Block DiagramDiagram
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
OK (Output
Clock)
IK (InputClock)
I1
2I
O
T/OE
Pad
CE
XilinxXilinxFPGAFPGA RoutingRouting
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XilinxFPGAG Routingout g Fast Direct Interconnect - CLB to CLB
General Purpose Interconnect - Uses switch matrix
CLBCLB
CLBCLB
CLBCLB
CLBCLB
SwitchMatrixSwitchMatrix
Long Lines
Segmented acrosschip
Global clocks,lowest skew
2 Tri-states perCLB for busses
Other routing types inCPLDs and XC6200
FPGA : LAYOUTFPGA : LAYOUTProgrammable Interconnect Points PIPs (White)
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CLB(Red)
SwitchMatrix
Long Lines(Purple)
DirectInterconnect(Green)
Routed Wires (Blue)
Programmable Interconnect Points, PIPs (White)
;4 ?@@@ ( ;4 ?@@@ (
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2
12
8
4
3
2
3
CLB
8 4 8 4
Quad
Single
Double
Long
DirectConnect
Direct
ConnectQuad Long Global
ClockLong Double Single Global
ClockCarry
Chain
Long
12 4 4
Courtesy Xilinx
/0+1+ (4 ?4 ?>.@
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56/56/
"
3-.9 : ;.3< "= &> '
"
3-.* : ;
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Xilinx XC4000ex
Courtesy Xilinx
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/*/* 0011"I& J
"I& J
"I&
J
"I&
J
# %6$
% ,: K6$L
% :$ ; 6
Mtal 1
Mtal 2
Dielectric
/*/* 0011
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/-&
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
.*
"
"I& J
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J
"I&
J
.* . ? *J
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? 6
/F#
$ ,?
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.*
/*/*
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8 * 37* 8 *H( ''*' * ( $
+ ' ' ('
-*38 * 37*
8 *H( )*I')( *')( 3
Architectures : du grain fin au grain pais
GRAIN PAISGRAIN FIN
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bit
CLB
ALU + MULT
Reg FILE
mot
DCT
algorithme
Cur
MPEG4
application
Cur
hybride
FPGA
DSP
Cur reconfigurable
Interconnexion ?
Quelle Granularit ?
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%%,,
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- ' 5* 3( ))*'( 3
- ' 5* 3 )( 3J*'**-*( ' '- 3 4! *2'*
5 3
(4 ,43
%% * , * ,
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+
*SRAM SRAM SRAM
SRAM SRAM SRAM
SRAM SRAM SRAM
OPERATING layerOPERATING layer
CONFIGURATION layerCONFIGURATION layer
CLB, LC
Globalinterconnect
Localinterconnect
! "#$
Exemple : XC6200Exemple : XC6200 (abandonn(abandonn)) 1/41/4
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4x4 Block
User I/Os
16x16 Tile
AddressData
FastMAPtm
Interface
UserI/Os U
serI/Os
User I/Os
Control
*Number of tiles varies between devices in family
Function Cell
Conception Grain pais
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CAHIER DES CHARGES
Acclration des applications orientes flots de donnes
Extrapolation aise sur de nouvelles technologies
Flexibilit dutilisation maximale
Personnalisation aise
GRAIN EPAIS Faible surcot
ALU, MULT
Registres
Multiplexeurs
Oprateurs
arithmtiques
Grain fin Grain pais
,- .,- .//0 0 1 0 0 1 /"","&+
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K#$L
+$ ,,,,,, !%
$
% -$
/)",/1- )/ M/ $
)/-","&+ ': 93$ 88(LIBRAIRIE
DE CELLULES
- spcification- schmas symboles- modles simulation
simulation
simulationpost-layout
-&-,"&+
'6: %%%%N #$(
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,- .,- .//0 0 10 0 1
2
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Batterynotin
cluded!
2
"+ "+ )"+ "+ )
Hardware Boards : example
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"+ "+ )"+ "+ )
%!& " '
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CIRCUITS RECONFIGURABLES
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C1
+ )
% #F ' (
% ::3$ 2
% $ 9F C
% $ & M R C
DSP RAM
= ,= ,
FPGA Fabric
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Xilinx Vertex-II Pro
Courtesy Xilinx
High-speed I/O
Embedded PowerPc
Embedded memories
Hardwired multipliers
FPGA Fabric
+1AB!(!)1( ( B1)B! 1501++#%( +1AB!(!)1( ( B1)B! 1501++#%(
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Source: Current and Emerging Embedded Markets and Opportunities ElectronicMarket Forecasters
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market windows
Total Units
Additional ASIC costs:Additional ASIC costs:
FPGAs were ultimately the most cost-effective solution, allowing us to provide new servicesyear after year. With Xilinx, we were able to protect our initial investment.
- Mr. Yoshiko Chika,Director and Sr. General Manager, DDI Pocket
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