chuong 4 - 3 vao ra noi tiep 8251.ppt

7/27/2019 Chuong 4 - 3 Vao Ra Noi Tiep 8251.ppt

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Giao tip ni tip

USART 8251Universal Synchronous

Asynchronous receiver transmitter


2/25

Khi nim chung

CPU lun truyn d liu song song viBus d liu nhiu ng.

Vo ra ni tip c nhim v:Nhn d liu song song t CPU chuyn

thnh d liu ni tip cp ti thit b.

Chuyn d liu ni tip t thit b cp tithnh d liu song song chuyn cho CPU.


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S khi


5/25

Cc tn hiu cung cp

Reset: Ng vo khi ng li 8251

CLK: ng vo cung cp xung nhp nh

thi hot ng vi x l.

Vcc, GND: cp ngun.


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Cc tn hiu kt ni h thng

CS (Chip select): chn mch

WR (write): ng vo iu khin ghi 8251

RD (read): ng vo iu khin c 8251.

C/D (control/data): ng vo xc nh cghi iu khin hoc d liu.


7/25

AddressBUS

Control BUS

Data BUS

D0-D7 CLKResetWRRDC/D

A0

2 (TTL)ResetI/OWI/OR

Gii ma chvo ra

CS

8251

Ni ghp vi BUS h thng ca CPU


8/25

Cc tn hiu iu khin modem

DSR (data set ready): ng vo thng bomodem sn sng.

DTR (data set ready): l ng ra thng bo8251 sn sng. RTS(request to send): l ng ra yu cu

modem truyn d liu. CTS (clear to send): l ng vo nhnthng bo sn sng nhn d liu camodem.


9/25

Modem cnngb

Mch giaotip ngdy in

thoi

B to xungnhp

ng dy in thoi

RxD

DSR

TxD

DTR

CTS

RTS

RxC

TxC

8251

DTR

DSR

CTS

RTS

TxD

RxD

Kt ni vi modem cn ng b


10/25

Kt ni vi modem ng b

Modem ngb

Giao din ngdy in thoi

ng dy in thoi

RxD

DSR

TxD

DTR

CTS

RTS

Syndet

RxC

TxC

8251

RxD

TxD

DSR

DTR

CTS

RTS

Syndet

RxC

TxC


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Cc tn hiu truyn d liu

TxD (transmit data): ng ra truyn d liuti thit b.

TxRDY (transmitter ready): l ng ra thngbo b m truyn sn sng. TxEmpty: ng ra thng bo b m truyn

rng, hoc b truyn khng c chophp. TxC (transmitter clock): ng vo cp clock

truyn d liu.


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Cc tn hiu nhn d liu

RxD (receive data): ng ra truyn d liuti thit b.

RxRDY (receiver ready): l ng ra thngbo b m nhn nhn xong mt dliu.

RxC (receiver clock): ng vo cp clocknhn d liu.


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Tn hiu ng b

SYNDET (synchronous detect):

Trong ch ng b trong: l ng ra khi

8251 nhn xong k t ng b ng.Trong ch ng b ngoi: l ng vo

8251 bt u nhn d liu.

Trong ch cn ng b: l ng ra mcthp sau khi RESET, n tc ng mc cao khic k t break.


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Address BUS

Control BUS

Data BUS

D0-D7 CLKResetWRRDC/D

A0

2 (TTL)ResetI/OWI/OR

Gii m a chvo ra CS

8251

TxDRxC SynDetRxDTxC

Thitb hoc u cui ngb

Kt ni thit b ng b


16/25

T ch

K t ngb 1

K t ngb 2

T lnh

D liu truyn nhn

T lnh

D liu truyn nhn

T lnh

C/D=1

C/D=1

C/D=1

C/D=1

C/D=0

C/D=1

C/D=0

C/D=1

Ch s dng trong

ch ng b

Hnh 5.25: Qui trnh lp trnh cho 8251.

Lp trnh cho 8251


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B1B2L1L2PENEPS1S2

1010

1100

64X16X1XSYN

1010

1100

8 bit7 bit6 bit5 bit

Baud : tc baud

Length : chiu di k t

Stop: s Stop bit

Parity Enable: chophep kim tra chn l1: chophep; 0: khng chophep

Even Parity: chophep kim tra chn1:chn ; 0: l

1010

1100

2 bit1,5 bit1 bitcm

T ch Asynchronous ca 8251


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T ch synchronous ca 8251


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TxENDTRRxESBRKERRTSIREH

Transmit Enable (chopheptruyn) 1: chophep

Data Terminal Ready (D liu u cuisn sng): khi bit ny1 s lm ng ra

DTRtc ng mc 0

Receive Enable (chophep nhn)1: chophep

Send Break Character (Gi k t ngng truyn)1: lm TxD gi mc thp

Enter Hunt Mode (Chophep ch tm kim)1: chophep tm cc k t ng b

Internal Reset (Reset trong)

1: s reset mm cho 8251 tr v trng thi nhn li t ch

Request To Send (yu cu gi):1: s lm ng ra RTS tc ng mc 0

Error Reset (Chophep xa cc c bo li)

1: xa tt c cc c li PE, OE, FE v 0

T lnh ca 8251


20/25

MOV DX,PORT_K ; Np a ch ca iu khin vo thanh ghi DX MOV AL,00H ; Np 0 vo thanh ghi lnh ri to tr m OUT DX,AL ; bo 8251ang ch nhn t lnh trc khi MOV CX,02 ; c reset D0: LOOP D0

OUT DX,AL

MOV CX,02

D1: LOOP D1

OUT DX,AL MOV CX,02

D2: LOOP D2

MOV AL,40H ; Np t lnh reset mm ri to tr chuyn 8251 OUT DX,AL ; v trng thi chun b nhn t lnh ch MOV CX,02

D3: LOOP D3

MOV AL,11001110B ; Np t iu khin nh ngha 8251 hot ng OUT DX,AL ; vi ch cn ng b t s tc baud l MOV CX,02 ; 16x (d1d0=10), chiu di k t 8 bit (d3d2=11), D4: LOOP D4 ; khng cho php kim tra chn l (d4=0), 2 stop MOV AL,00110111B ; bit Np t lnh nh ngha c tnh ca 8251: OUT DX,AL ; cho phep truyn, tac ng ng ra DTR, cho phep nhn, ch

hot ng thng thng (khng gi k t ngng truyn), xa tt c cac c li, tac ng ng raRTS, khng reset mm, khng cho phep ch tim k t ng b.

Vi d lp trnh khi ng 8251


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TxD

Stop bitStart bitCc bit d liu c lp trnh

trc

Bit chn lMakinglm du

Do 8251 to ra khi c lptrnh

Hnh 5.26: Khung truyn d liu bn truyn trong ch cn ngb.

RxD

Stop bitStart bit

Cc bit d liu c lp trnh

trc

Bit chn l

Khng xut hin trndata bus

Hnh 5.27: Khung truyn d liu bn nhn trong ch cn ngb.

Khung truyn nhn d liu trong ch cn ng b


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TxRDYRxRDYTxEPEOEFEDSR SynDetBrkDet

Transmitter Ready

(B m sn sng)Ch th 8251 sn sng nhn mt k

t hoc mt lnh

Receiver Ready (b nhn sn sng): Ch th8251 nhn mt k t trn ng vo ni tip

ca n sn sng truyn cho CPU

Transmitter Empty(B truyn rng)Bit ny ch th b bin i song song sang ni tip cab

truyn rng

Parity Error(li chn l): Bit ny c lp khipht hin c li chn ltrn k t va nhn c. n s c xabng t lnh cbit ER = 1.

Li nykhng cm hot ng ca 8251

Overrun Error(li overrun): Bit ny ch th mt k t b mt do CPU cha c vo k t c trongb m m k t ti sau ti

Frame Error(li khung truyn): bit ny ch tc ng trong ch cn ngb ch thbit Stopkhng hp l cpht hin ti cui mi k t

Synchronous Detect(Pht hin ngb). Khi thit lp cho ch ngb trong ch th 8251 thc hin xongvic ngb sn sng truyn d liu

Data Set Ready(D liu thit lp sn sng): thng s dng cho vic kim tra trng thi Modem

T trng thi ca 8251


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MOV DX,Ctr_Add ;a chthanh ghi trng thi Test1: IN AL,DX ;c thanh ghi trng thi

AND AL,10000001B ; Kim tra DSR v TxRDY CMP AL,10000001B

JNE Test1 ; Ch bt u truyn khi sn sng

MOV DX,Data_Add ;a chthanh ghi d liu

MOV AL, Data_Send ; Np d liu mun truyn vo AL OUT DX,AL ; Gi d liu ti cng truyn

V d v kim tra thanh ghi trng

thi trc khi truyn d liu


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MOV DX,Ctr_Add ;a chthanh ghi trng thi

Test2: IN AL,DX ;c thanh ghi trng thi AND AL,00000010B ; Kim tra RxRDY

JZ Test2 ; Ch bt u nhn khi sn sng

MOV DX,Data_Add ;a chthanh ghi d liu

IN AL,DX ;c d liu

V d v kim tra thanh ghi trng

thi trc khi nhn d liu

chuong 4 - 3 vao ra noi tiep 8251.ppt

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